[mirror_ubuntu-bionic-kernel.git] / include / linux / spi / mxs-spi.h

/*
 * include/linux/spi/mxs-spi.h
 *
 * Freescale i.MX233/i.MX28 SPI controller register definition
 *
 * Copyright 2008 Embedded Alley Solutions, Inc.
 * Copyright 2009-2011 Freescale Semiconductor, Inc.
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; either version 2 of the License, or
 * (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 */

#ifndef __LINUX_SPI_MXS_SPI_H__
#define __LINUX_SPI_MXS_SPI_H__

#include <linux/dmaengine.h>

#define ssp_is_old(host)	((host)->devid == IMX23_SSP)

/* SSP registers */
#define HW_SSP_CTRL0				0x000
#define  BM_SSP_CTRL0_RUN			(1 << 29)
#define  BM_SSP_CTRL0_SDIO_IRQ_CHECK		(1 << 28)
#define  BM_SSP_CTRL0_LOCK_CS			(1 << 27)
#define  BM_SSP_CTRL0_IGNORE_CRC		(1 << 26)
#define  BM_SSP_CTRL0_READ			(1 << 25)
#define  BM_SSP_CTRL0_DATA_XFER			(1 << 24)
#define  BP_SSP_CTRL0_BUS_WIDTH			22
#define  BM_SSP_CTRL0_BUS_WIDTH			(0x3 << 22)
#define  BM_SSP_CTRL0_WAIT_FOR_IRQ		(1 << 21)
#define  BM_SSP_CTRL0_WAIT_FOR_CMD		(1 << 20)
#define  BM_SSP_CTRL0_LONG_RESP			(1 << 19)
#define  BM_SSP_CTRL0_GET_RESP			(1 << 17)
#define  BM_SSP_CTRL0_ENABLE			(1 << 16)
#define  BP_SSP_CTRL0_XFER_COUNT		0
#define  BM_SSP_CTRL0_XFER_COUNT		0xffff
#define HW_SSP_CMD0				0x010
#define  BM_SSP_CMD0_DBL_DATA_RATE_EN		(1 << 25)
#define  BM_SSP_CMD0_SLOW_CLKING_EN		(1 << 22)
#define  BM_SSP_CMD0_CONT_CLKING_EN		(1 << 21)
#define  BM_SSP_CMD0_APPEND_8CYC		(1 << 20)
#define  BP_SSP_CMD0_BLOCK_SIZE			16
#define  BM_SSP_CMD0_BLOCK_SIZE			(0xf << 16)
#define  BP_SSP_CMD0_BLOCK_COUNT		8
#define  BM_SSP_CMD0_BLOCK_COUNT		(0xff << 8)
#define  BP_SSP_CMD0_CMD			0
#define  BM_SSP_CMD0_CMD			0xff
#define HW_SSP_CMD1				0x020
#define HW_SSP_XFER_SIZE			0x030
#define HW_SSP_BLOCK_SIZE			0x040
#define  BP_SSP_BLOCK_SIZE_BLOCK_COUNT		4
#define  BM_SSP_BLOCK_SIZE_BLOCK_COUNT		(0xffffff << 4)
#define  BP_SSP_BLOCK_SIZE_BLOCK_SIZE		0
#define  BM_SSP_BLOCK_SIZE_BLOCK_SIZE		0xf
#define HW_SSP_TIMING(h)			(ssp_is_old(h) ? 0x050 : 0x070)
#define  BP_SSP_TIMING_TIMEOUT			16
#define  BM_SSP_TIMING_TIMEOUT			(0xffff << 16)
#define  BP_SSP_TIMING_CLOCK_DIVIDE		8
#define  BM_SSP_TIMING_CLOCK_DIVIDE		(0xff << 8)
#define  BF_SSP_TIMING_CLOCK_DIVIDE(v)		\
			(((v) << 8) & BM_SSP_TIMING_CLOCK_DIVIDE)
#define  BP_SSP_TIMING_CLOCK_RATE		0
#define  BM_SSP_TIMING_CLOCK_RATE		0xff
#define BF_SSP_TIMING_CLOCK_RATE(v)		\
			(((v) << 0) & BM_SSP_TIMING_CLOCK_RATE)
#define HW_SSP_CTRL1(h)				(ssp_is_old(h) ? 0x060 : 0x080)
#define  BM_SSP_CTRL1_SDIO_IRQ			(1 << 31)
#define  BM_SSP_CTRL1_SDIO_IRQ_EN		(1 << 30)
#define  BM_SSP_CTRL1_RESP_ERR_IRQ		(1 << 29)
#define  BM_SSP_CTRL1_RESP_ERR_IRQ_EN		(1 << 28)
#define  BM_SSP_CTRL1_RESP_TIMEOUT_IRQ		(1 << 27)
#define  BM_SSP_CTRL1_RESP_TIMEOUT_IRQ_EN	(1 << 26)
#define  BM_SSP_CTRL1_DATA_TIMEOUT_IRQ		(1 << 25)
#define  BM_SSP_CTRL1_DATA_TIMEOUT_IRQ_EN	(1 << 24)
#define  BM_SSP_CTRL1_DATA_CRC_IRQ		(1 << 23)
#define  BM_SSP_CTRL1_DATA_CRC_IRQ_EN		(1 << 22)
#define  BM_SSP_CTRL1_FIFO_UNDERRUN_IRQ		(1 << 21)
#define  BM_SSP_CTRL1_FIFO_UNDERRUN_IRQ_EN	(1 << 20)
#define  BM_SSP_CTRL1_RECV_TIMEOUT_IRQ		(1 << 17)
#define  BM_SSP_CTRL1_RECV_TIMEOUT_IRQ_EN	(1 << 16)
#define  BM_SSP_CTRL1_FIFO_OVERRUN_IRQ		(1 << 15)
#define  BM_SSP_CTRL1_FIFO_OVERRUN_IRQ_EN	(1 << 14)
#define  BM_SSP_CTRL1_DMA_ENABLE		(1 << 13)
#define  BM_SSP_CTRL1_PHASE			(1 << 10)
#define  BM_SSP_CTRL1_POLARITY			(1 << 9)
#define  BP_SSP_CTRL1_WORD_LENGTH		4
#define  BM_SSP_CTRL1_WORD_LENGTH		(0xf << 4)
#define  BF_SSP_CTRL1_WORD_LENGTH(v)		\
			(((v) << 4) & BM_SSP_CTRL1_WORD_LENGTH)
#define  BV_SSP_CTRL1_WORD_LENGTH__FOUR_BITS	0x3
#define  BV_SSP_CTRL1_WORD_LENGTH__EIGHT_BITS	0x7
#define  BV_SSP_CTRL1_WORD_LENGTH__SIXTEEN_BITS	0xF
#define  BP_SSP_CTRL1_SSP_MODE			0
#define  BM_SSP_CTRL1_SSP_MODE			0xf
#define  BF_SSP_CTRL1_SSP_MODE(v)		\
			(((v) << 0) & BM_SSP_CTRL1_SSP_MODE)
#define  BV_SSP_CTRL1_SSP_MODE__SPI		0x0
#define  BV_SSP_CTRL1_SSP_MODE__SSI		0x1
#define  BV_SSP_CTRL1_SSP_MODE__SD_MMC		0x3
#define  BV_SSP_CTRL1_SSP_MODE__MS		0x4

#define HW_SSP_DATA(h)				(ssp_is_old(h) ? 0x070 : 0x090)

#define HW_SSP_SDRESP0(h)			(ssp_is_old(h) ? 0x080 : 0x0a0)
#define HW_SSP_SDRESP1(h)			(ssp_is_old(h) ? 0x090 : 0x0b0)
#define HW_SSP_SDRESP2(h)			(ssp_is_old(h) ? 0x0a0 : 0x0c0)
#define HW_SSP_SDRESP3(h)			(ssp_is_old(h) ? 0x0b0 : 0x0d0)
#define HW_SSP_STATUS(h)			(ssp_is_old(h) ? 0x0c0 : 0x100)
#define  BM_SSP_STATUS_CARD_DETECT		(1 << 28)
#define  BM_SSP_STATUS_SDIO_IRQ			(1 << 17)
#define  BM_SSP_STATUS_FIFO_EMPTY		(1 << 5)

#define BF_SSP(value, field)	(((value) << BP_SSP_##field) & BM_SSP_##field)

#define SSP_PIO_NUM	3

enum mxs_ssp_id {
	IMX23_SSP,
	IMX28_SSP,
};

struct mxs_ssp {
	struct device			*dev;
	void __iomem			*base;
	struct clk			*clk;
	unsigned int			clk_rate;
	enum mxs_ssp_id			devid;

	struct dma_chan			*dmach;
	unsigned int			dma_dir;
	enum dma_transfer_direction	slave_dirn;
	u32				ssp_pio_words[SSP_PIO_NUM];
};

void mxs_ssp_set_clk_rate(struct mxs_ssp *ssp, unsigned int rate);

#endif	/* __LINUX_SPI_MXS_SPI_H__ */
Commit	Line	Data
8be3d3b2 MV	1	/*
	2	* include/linux/spi/mxs-spi.h
	3	*
	4	* Freescale i.MX233/i.MX28 SPI controller register definition
	5	*
	6	* Copyright 2008 Embedded Alley Solutions, Inc.
	7	* Copyright 2009-2011 Freescale Semiconductor, Inc.
	8	*
	9	* This program is free software; you can redistribute it and/or modify
	10	* it under the terms of the GNU General Public License as published by
	11	* the Free Software Foundation; either version 2 of the License, or
	12	* (at your option) any later version.
	13	*
	14	* This program is distributed in the hope that it will be useful,
	15	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	16	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	17	* GNU General Public License for more details.
8be3d3b2 MV	18	*/
	19
	20	#ifndef __LINUX_SPI_MXS_SPI_H__
	21	#define __LINUX_SPI_MXS_SPI_H__
	22
26aafa77	23	#include <linux/dmaengine.h>
65defb9b	24
600a991f	25	#define ssp_is_old(host) ((host)->devid == IMX23_SSP)
8be3d3b2 MV	26
	27	/* SSP registers */
	28	#define HW_SSP_CTRL0 0x000
	29	#define BM_SSP_CTRL0_RUN (1 << 29)
	30	#define BM_SSP_CTRL0_SDIO_IRQ_CHECK (1 << 28)
f83b7380	31	#define BM_SSP_CTRL0_LOCK_CS (1 << 27)
8be3d3b2 MV	32	#define BM_SSP_CTRL0_IGNORE_CRC (1 << 26)
	33	#define BM_SSP_CTRL0_READ (1 << 25)
	34	#define BM_SSP_CTRL0_DATA_XFER (1 << 24)
	35	#define BP_SSP_CTRL0_BUS_WIDTH 22
	36	#define BM_SSP_CTRL0_BUS_WIDTH (0x3 << 22)
	37	#define BM_SSP_CTRL0_WAIT_FOR_IRQ (1 << 21)
f83b7380	38	#define BM_SSP_CTRL0_WAIT_FOR_CMD (1 << 20)
8be3d3b2 MV	39	#define BM_SSP_CTRL0_LONG_RESP (1 << 19)
	40	#define BM_SSP_CTRL0_GET_RESP (1 << 17)
	41	#define BM_SSP_CTRL0_ENABLE (1 << 16)
	42	#define BP_SSP_CTRL0_XFER_COUNT 0
	43	#define BM_SSP_CTRL0_XFER_COUNT 0xffff
	44	#define HW_SSP_CMD0 0x010
	45	#define BM_SSP_CMD0_DBL_DATA_RATE_EN (1 << 25)
	46	#define BM_SSP_CMD0_SLOW_CLKING_EN (1 << 22)
	47	#define BM_SSP_CMD0_CONT_CLKING_EN (1 << 21)
	48	#define BM_SSP_CMD0_APPEND_8CYC (1 << 20)
	49	#define BP_SSP_CMD0_BLOCK_SIZE 16
	50	#define BM_SSP_CMD0_BLOCK_SIZE (0xf << 16)
	51	#define BP_SSP_CMD0_BLOCK_COUNT 8
	52	#define BM_SSP_CMD0_BLOCK_COUNT (0xff << 8)
	53	#define BP_SSP_CMD0_CMD 0
	54	#define BM_SSP_CMD0_CMD 0xff
	55	#define HW_SSP_CMD1 0x020
	56	#define HW_SSP_XFER_SIZE 0x030
	57	#define HW_SSP_BLOCK_SIZE 0x040
	58	#define BP_SSP_BLOCK_SIZE_BLOCK_COUNT 4
	59	#define BM_SSP_BLOCK_SIZE_BLOCK_COUNT (0xffffff << 4)
	60	#define BP_SSP_BLOCK_SIZE_BLOCK_SIZE 0
	61	#define BM_SSP_BLOCK_SIZE_BLOCK_SIZE 0xf
	62	#define HW_SSP_TIMING(h) (ssp_is_old(h) ? 0x050 : 0x070)
	63	#define BP_SSP_TIMING_TIMEOUT 16
	64	#define BM_SSP_TIMING_TIMEOUT (0xffff << 16)
	65	#define BP_SSP_TIMING_CLOCK_DIVIDE 8
	66	#define BM_SSP_TIMING_CLOCK_DIVIDE (0xff << 8)
f83b7380 MV	67	#define BF_SSP_TIMING_CLOCK_DIVIDE(v) \
f83b7380 MV	68	(((v) << 8) & BM_SSP_TIMING_CLOCK_DIVIDE)
8be3d3b2 MV	69	#define BP_SSP_TIMING_CLOCK_RATE 0
8be3d3b2 MV	70	#define BM_SSP_TIMING_CLOCK_RATE 0xff
f83b7380 MV	71	#define BF_SSP_TIMING_CLOCK_RATE(v) \
f83b7380 MV	72	(((v) << 0) & BM_SSP_TIMING_CLOCK_RATE)
8be3d3b2 MV	73	#define HW_SSP_CTRL1(h) (ssp_is_old(h) ? 0x060 : 0x080)
	74	#define BM_SSP_CTRL1_SDIO_IRQ (1 << 31)
	75	#define BM_SSP_CTRL1_SDIO_IRQ_EN (1 << 30)
	76	#define BM_SSP_CTRL1_RESP_ERR_IRQ (1 << 29)
	77	#define BM_SSP_CTRL1_RESP_ERR_IRQ_EN (1 << 28)
	78	#define BM_SSP_CTRL1_RESP_TIMEOUT_IRQ (1 << 27)
	79	#define BM_SSP_CTRL1_RESP_TIMEOUT_IRQ_EN (1 << 26)
	80	#define BM_SSP_CTRL1_DATA_TIMEOUT_IRQ (1 << 25)
	81	#define BM_SSP_CTRL1_DATA_TIMEOUT_IRQ_EN (1 << 24)
	82	#define BM_SSP_CTRL1_DATA_CRC_IRQ (1 << 23)
	83	#define BM_SSP_CTRL1_DATA_CRC_IRQ_EN (1 << 22)
	84	#define BM_SSP_CTRL1_FIFO_UNDERRUN_IRQ (1 << 21)
	85	#define BM_SSP_CTRL1_FIFO_UNDERRUN_IRQ_EN (1 << 20)
	86	#define BM_SSP_CTRL1_RECV_TIMEOUT_IRQ (1 << 17)
	87	#define BM_SSP_CTRL1_RECV_TIMEOUT_IRQ_EN (1 << 16)
	88	#define BM_SSP_CTRL1_FIFO_OVERRUN_IRQ (1 << 15)
	89	#define BM_SSP_CTRL1_FIFO_OVERRUN_IRQ_EN (1 << 14)
	90	#define BM_SSP_CTRL1_DMA_ENABLE (1 << 13)
f83b7380	91	#define BM_SSP_CTRL1_PHASE (1 << 10)
8be3d3b2 MV	92	#define BM_SSP_CTRL1_POLARITY (1 << 9)
	93	#define BP_SSP_CTRL1_WORD_LENGTH 4
	94	#define BM_SSP_CTRL1_WORD_LENGTH (0xf << 4)
f83b7380 MV	95	#define BF_SSP_CTRL1_WORD_LENGTH(v) \
	96	(((v) << 4) & BM_SSP_CTRL1_WORD_LENGTH)
	97	#define BV_SSP_CTRL1_WORD_LENGTH__FOUR_BITS 0x3
	98	#define BV_SSP_CTRL1_WORD_LENGTH__EIGHT_BITS 0x7
	99	#define BV_SSP_CTRL1_WORD_LENGTH__SIXTEEN_BITS 0xF
8be3d3b2 MV	100	#define BP_SSP_CTRL1_SSP_MODE 0
8be3d3b2 MV	101	#define BM_SSP_CTRL1_SSP_MODE 0xf
f83b7380 MV	102	#define BF_SSP_CTRL1_SSP_MODE(v) \
	103	(((v) << 0) & BM_SSP_CTRL1_SSP_MODE)
	104	#define BV_SSP_CTRL1_SSP_MODE__SPI 0x0
	105	#define BV_SSP_CTRL1_SSP_MODE__SSI 0x1
	106	#define BV_SSP_CTRL1_SSP_MODE__SD_MMC 0x3
	107	#define BV_SSP_CTRL1_SSP_MODE__MS 0x4
	108
	109	#define HW_SSP_DATA(h) (ssp_is_old(h) ? 0x070 : 0x090)
	110
8be3d3b2 MV	111	#define HW_SSP_SDRESP0(h) (ssp_is_old(h) ? 0x080 : 0x0a0)
	112	#define HW_SSP_SDRESP1(h) (ssp_is_old(h) ? 0x090 : 0x0b0)
	113	#define HW_SSP_SDRESP2(h) (ssp_is_old(h) ? 0x0a0 : 0x0c0)
	114	#define HW_SSP_SDRESP3(h) (ssp_is_old(h) ? 0x0b0 : 0x0d0)
	115	#define HW_SSP_STATUS(h) (ssp_is_old(h) ? 0x0c0 : 0x100)
	116	#define BM_SSP_STATUS_CARD_DETECT (1 << 28)
	117	#define BM_SSP_STATUS_SDIO_IRQ (1 << 17)
f83b7380	118	#define BM_SSP_STATUS_FIFO_EMPTY (1 << 5)
8be3d3b2 MV	119
	120	#define BF_SSP(value, field) (((value) << BP_SSP_##field) & BM_SSP_##field)
	121
	122	#define SSP_PIO_NUM 3
	123
600a991f MV	124	enum mxs_ssp_id {
	125	IMX23_SSP,
	126	IMX28_SSP,
8be3d3b2 MV	127	};
8be3d3b2 MV	128
829c1bf4 MV	129	struct mxs_ssp {
	130	struct device *dev;
	131	void __iomem *base;
	132	struct clk *clk;
	133	unsigned int clk_rate;
	134	enum mxs_ssp_id devid;
65defb9b	135
65defb9b	136	struct dma_chan *dmach;
65defb9b MV	137	unsigned int dma_dir;
	138	enum dma_transfer_direction slave_dirn;
	139	u32 ssp_pio_words[SSP_PIO_NUM];
829c1bf4 MV	140	};
829c1bf4 MV	141
13082398 MV	142	void mxs_ssp_set_clk_rate(struct mxs_ssp *ssp, unsigned int rate);
13082398 MV	143
8be3d3b2	144	#endif /* __LINUX_SPI_MXS_SPI_H__ */