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8ae12a0d DB |
1 | /* |
2 | * Copyright (C) 2005 David Brownell | |
3 | * | |
4 | * This program is free software; you can redistribute it and/or modify | |
5 | * it under the terms of the GNU General Public License as published by | |
6 | * the Free Software Foundation; either version 2 of the License, or | |
7 | * (at your option) any later version. | |
8 | * | |
9 | * This program is distributed in the hope that it will be useful, | |
10 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
11 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
12 | * GNU General Public License for more details. | |
13 | * | |
14 | * You should have received a copy of the GNU General Public License | |
15 | * along with this program; if not, write to the Free Software | |
16 | * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. | |
17 | */ | |
18 | ||
19 | #ifndef __LINUX_SPI_H | |
20 | #define __LINUX_SPI_H | |
21 | ||
0a30c5ce | 22 | #include <linux/device.h> |
75368bf6 | 23 | #include <linux/mod_devicetable.h> |
5a0e3ad6 | 24 | #include <linux/slab.h> |
ffbbdd21 | 25 | #include <linux/kthread.h> |
0a30c5ce | 26 | |
8ae12a0d | 27 | /* |
b885244e | 28 | * INTERFACES between SPI master-side drivers and SPI infrastructure. |
8ae12a0d | 29 | * (There's no SPI slave support for Linux yet...) |
8ae12a0d DB |
30 | */ |
31 | extern struct bus_type spi_bus_type; | |
32 | ||
33 | /** | |
34 | * struct spi_device - Master side proxy for an SPI slave device | |
35 | * @dev: Driver model representation of the device. | |
36 | * @master: SPI controller used with the device. | |
37 | * @max_speed_hz: Maximum clock rate to be used with this chip | |
38 | * (on this board); may be changed by the device's driver. | |
4cff33f9 | 39 | * The spi_transfer.speed_hz can override this for each transfer. |
33e34dc6 | 40 | * @chip_select: Chipselect, distinguishing chips handled by @master. |
8ae12a0d DB |
41 | * @mode: The spi mode defines how data is clocked out and in. |
42 | * This may be changed by the device's driver. | |
33e34dc6 DB |
43 | * The "active low" default for chipselect mode can be overridden |
44 | * (by specifying SPI_CS_HIGH) as can the "MSB first" default for | |
45 | * each word in a transfer (by specifying SPI_LSB_FIRST). | |
8ae12a0d | 46 | * @bits_per_word: Data transfers involve one or more words; word sizes |
747d844e | 47 | * like eight or 12 bits are common. In-memory wordsizes are |
8ae12a0d | 48 | * powers of two bytes (e.g. 20 bit samples use 32 bits). |
ccf77cc4 DB |
49 | * This may be changed by the device's driver, or left at the |
50 | * default (0) indicating protocol words are eight bit bytes. | |
4cff33f9 | 51 | * The spi_transfer.bits_per_word can override this for each transfer. |
8ae12a0d | 52 | * @irq: Negative, or the number passed to request_irq() to receive |
747d844e | 53 | * interrupts from this device. |
8ae12a0d | 54 | * @controller_state: Controller's runtime state |
b885244e | 55 | * @controller_data: Board-specific definitions for controller, such as |
747d844e | 56 | * FIFO initialization parameters; from board_info.controller_data |
33e34dc6 DB |
57 | * @modalias: Name of the driver to use with this device, or an alias |
58 | * for that name. This appears in the sysfs "modalias" attribute | |
59 | * for driver coldplugging, and in uevents used for hotplugging | |
446411e1 | 60 | * @cs_gpio: gpio number of the chipselect line (optional, -ENOENT when |
095c3752 | 61 | * when not using a GPIO line) |
8ae12a0d | 62 | * |
33e34dc6 | 63 | * A @spi_device is used to interchange data between an SPI slave |
8ae12a0d DB |
64 | * (usually a discrete chip) and CPU memory. |
65 | * | |
33e34dc6 | 66 | * In @dev, the platform_data is used to hold information about this |
8ae12a0d DB |
67 | * device that's meaningful to the device's protocol driver, but not |
68 | * to its controller. One example might be an identifier for a chip | |
33e34dc6 DB |
69 | * variant with slightly different functionality; another might be |
70 | * information about how this particular board wires the chip's pins. | |
8ae12a0d DB |
71 | */ |
72 | struct spi_device { | |
73 | struct device dev; | |
74 | struct spi_master *master; | |
75 | u32 max_speed_hz; | |
76 | u8 chip_select; | |
77 | u8 mode; | |
b885244e DB |
78 | #define SPI_CPHA 0x01 /* clock phase */ |
79 | #define SPI_CPOL 0x02 /* clock polarity */ | |
0c868461 DB |
80 | #define SPI_MODE_0 (0|0) /* (original MicroWire) */ |
81 | #define SPI_MODE_1 (0|SPI_CPHA) | |
8ae12a0d DB |
82 | #define SPI_MODE_2 (SPI_CPOL|0) |
83 | #define SPI_MODE_3 (SPI_CPOL|SPI_CPHA) | |
b885244e | 84 | #define SPI_CS_HIGH 0x04 /* chipselect active high? */ |
ccf77cc4 | 85 | #define SPI_LSB_FIRST 0x08 /* per-word bits-on-wire */ |
c06e677a | 86 | #define SPI_3WIRE 0x10 /* SI/SO signals shared */ |
4ef7af50 | 87 | #define SPI_LOOP 0x20 /* loopback mode */ |
b55f627f DB |
88 | #define SPI_NO_CS 0x40 /* 1 dev/bus, no chipselect */ |
89 | #define SPI_READY 0x80 /* slave pulls low to pause */ | |
8ae12a0d DB |
90 | u8 bits_per_word; |
91 | int irq; | |
92 | void *controller_state; | |
b885244e | 93 | void *controller_data; |
75368bf6 | 94 | char modalias[SPI_NAME_SIZE]; |
74317984 | 95 | int cs_gpio; /* chip select gpio */ |
8ae12a0d | 96 | |
33e34dc6 DB |
97 | /* |
98 | * likely need more hooks for more protocol options affecting how | |
99 | * the controller talks to each chip, like: | |
100 | * - memory packing (12 bit samples into low bits, others zeroed) | |
101 | * - priority | |
102 | * - drop chipselect after each word | |
103 | * - chipselect delays | |
104 | * - ... | |
105 | */ | |
8ae12a0d DB |
106 | }; |
107 | ||
108 | static inline struct spi_device *to_spi_device(struct device *dev) | |
109 | { | |
b885244e | 110 | return dev ? container_of(dev, struct spi_device, dev) : NULL; |
8ae12a0d DB |
111 | } |
112 | ||
113 | /* most drivers won't need to care about device refcounting */ | |
114 | static inline struct spi_device *spi_dev_get(struct spi_device *spi) | |
115 | { | |
116 | return (spi && get_device(&spi->dev)) ? spi : NULL; | |
117 | } | |
118 | ||
119 | static inline void spi_dev_put(struct spi_device *spi) | |
120 | { | |
121 | if (spi) | |
122 | put_device(&spi->dev); | |
123 | } | |
124 | ||
125 | /* ctldata is for the bus_master driver's runtime state */ | |
126 | static inline void *spi_get_ctldata(struct spi_device *spi) | |
127 | { | |
128 | return spi->controller_state; | |
129 | } | |
130 | ||
131 | static inline void spi_set_ctldata(struct spi_device *spi, void *state) | |
132 | { | |
133 | spi->controller_state = state; | |
134 | } | |
135 | ||
9b40ff4d BD |
136 | /* device driver data */ |
137 | ||
138 | static inline void spi_set_drvdata(struct spi_device *spi, void *data) | |
139 | { | |
140 | dev_set_drvdata(&spi->dev, data); | |
141 | } | |
142 | ||
143 | static inline void *spi_get_drvdata(struct spi_device *spi) | |
144 | { | |
145 | return dev_get_drvdata(&spi->dev); | |
146 | } | |
8ae12a0d DB |
147 | |
148 | struct spi_message; | |
149 | ||
150 | ||
b885244e | 151 | |
2604288f DB |
152 | /** |
153 | * struct spi_driver - Host side "protocol" driver | |
75368bf6 | 154 | * @id_table: List of SPI devices supported by this driver |
2604288f DB |
155 | * @probe: Binds this driver to the spi device. Drivers can verify |
156 | * that the device is actually present, and may need to configure | |
157 | * characteristics (such as bits_per_word) which weren't needed for | |
158 | * the initial configuration done during system setup. | |
159 | * @remove: Unbinds this driver from the spi device | |
160 | * @shutdown: Standard shutdown callback used during system state | |
161 | * transitions such as powerdown/halt and kexec | |
162 | * @suspend: Standard suspend callback used during system state transitions | |
163 | * @resume: Standard resume callback used during system state transitions | |
164 | * @driver: SPI device drivers should initialize the name and owner | |
165 | * field of this structure. | |
166 | * | |
167 | * This represents the kind of device driver that uses SPI messages to | |
168 | * interact with the hardware at the other end of a SPI link. It's called | |
169 | * a "protocol" driver because it works through messages rather than talking | |
170 | * directly to SPI hardware (which is what the underlying SPI controller | |
171 | * driver does to pass those messages). These protocols are defined in the | |
172 | * specification for the device(s) supported by the driver. | |
173 | * | |
174 | * As a rule, those device protocols represent the lowest level interface | |
175 | * supported by a driver, and it will support upper level interfaces too. | |
176 | * Examples of such upper levels include frameworks like MTD, networking, | |
177 | * MMC, RTC, filesystem character device nodes, and hardware monitoring. | |
178 | */ | |
b885244e | 179 | struct spi_driver { |
75368bf6 | 180 | const struct spi_device_id *id_table; |
b885244e DB |
181 | int (*probe)(struct spi_device *spi); |
182 | int (*remove)(struct spi_device *spi); | |
183 | void (*shutdown)(struct spi_device *spi); | |
184 | int (*suspend)(struct spi_device *spi, pm_message_t mesg); | |
185 | int (*resume)(struct spi_device *spi); | |
186 | struct device_driver driver; | |
187 | }; | |
188 | ||
189 | static inline struct spi_driver *to_spi_driver(struct device_driver *drv) | |
190 | { | |
191 | return drv ? container_of(drv, struct spi_driver, driver) : NULL; | |
192 | } | |
193 | ||
194 | extern int spi_register_driver(struct spi_driver *sdrv); | |
195 | ||
33e34dc6 DB |
196 | /** |
197 | * spi_unregister_driver - reverse effect of spi_register_driver | |
198 | * @sdrv: the driver to unregister | |
199 | * Context: can sleep | |
200 | */ | |
b885244e DB |
201 | static inline void spi_unregister_driver(struct spi_driver *sdrv) |
202 | { | |
ddc1e975 BD |
203 | if (sdrv) |
204 | driver_unregister(&sdrv->driver); | |
b885244e DB |
205 | } |
206 | ||
3acbb014 LPC |
207 | /** |
208 | * module_spi_driver() - Helper macro for registering a SPI driver | |
209 | * @__spi_driver: spi_driver struct | |
210 | * | |
211 | * Helper macro for SPI drivers which do not do anything special in module | |
212 | * init/exit. This eliminates a lot of boilerplate. Each module may only | |
213 | * use this macro once, and calling it replaces module_init() and module_exit() | |
214 | */ | |
215 | #define module_spi_driver(__spi_driver) \ | |
216 | module_driver(__spi_driver, spi_register_driver, \ | |
217 | spi_unregister_driver) | |
b885244e | 218 | |
8ae12a0d DB |
219 | /** |
220 | * struct spi_master - interface to SPI master controller | |
49dce689 | 221 | * @dev: device interface to this driver |
2b9603a0 | 222 | * @list: link with the global spi_master list |
8ae12a0d | 223 | * @bus_num: board-specific (and often SOC-specific) identifier for a |
747d844e | 224 | * given SPI controller. |
b885244e | 225 | * @num_chipselect: chipselects are used to distinguish individual |
747d844e DB |
226 | * SPI slaves, and are numbered from zero to num_chipselects. |
227 | * each slave has a chipselect signal, but it's common that not | |
228 | * every chipselect is connected to a slave. | |
fd5e191e | 229 | * @dma_alignment: SPI controller constraint on DMA buffers alignment. |
b73b2559 | 230 | * @mode_bits: flags understood by this controller driver |
543bb255 SW |
231 | * @bits_per_word_mask: A mask indicating which values of bits_per_word are |
232 | * supported by the driver. Bit n indicates that a bits_per_word n+1 is | |
233 | * suported. If set, the SPI core will reject any transfer with an | |
234 | * unsupported bits_per_word. If not set, this value is simply ignored, | |
235 | * and it's up to the individual driver to perform any validation. | |
b73b2559 | 236 | * @flags: other constraints relevant to this driver |
5c79a5ae ES |
237 | * @bus_lock_spinlock: spinlock for SPI bus locking |
238 | * @bus_lock_mutex: mutex for SPI bus locking | |
239 | * @bus_lock_flag: indicates that the SPI bus is locked for exclusive use | |
8ae12a0d | 240 | * @setup: updates the device mode and clocking records used by a |
80224561 DB |
241 | * device's SPI controller; protocol code may call this. This |
242 | * must fail if an unrecognized or unsupported mode is requested. | |
33e34dc6 DB |
243 | * It's always safe to call this unless transfers are pending on |
244 | * the device whose settings are being modified. | |
8ae12a0d DB |
245 | * @transfer: adds a message to the controller's transfer queue. |
246 | * @cleanup: frees controller-specific state | |
ffbbdd21 LW |
247 | * @queued: whether this master is providing an internal message queue |
248 | * @kworker: thread struct for message pump | |
249 | * @kworker_task: pointer to task for message pump kworker thread | |
250 | * @pump_messages: work struct for scheduling work to the message pump | |
251 | * @queue_lock: spinlock to syncronise access to message queue | |
252 | * @queue: message queue | |
253 | * @cur_msg: the currently in-flight message | |
254 | * @busy: message pump is busy | |
255 | * @running: message pump is running | |
256 | * @rt: whether this queue is set to run as a realtime task | |
257 | * @prepare_transfer_hardware: a message will soon arrive from the queue | |
258 | * so the subsystem requests the driver to prepare the transfer hardware | |
259 | * by issuing this call | |
260 | * @transfer_one_message: the subsystem calls the driver to transfer a single | |
261 | * message while queuing transfers that arrive in the meantime. When the | |
262 | * driver is finished with this message, it must call | |
263 | * spi_finalize_current_message() so the subsystem can issue the next | |
264 | * transfer | |
dbabe0d6 | 265 | * @unprepare_transfer_hardware: there are currently no more messages on the |
ffbbdd21 LW |
266 | * queue so the subsystem notifies the driver that it may relax the |
267 | * hardware by issuing this call | |
095c3752 | 268 | * @cs_gpios: Array of GPIOs to use as chip select lines; one per CS |
446411e1 | 269 | * number. Any individual value may be -ENOENT for CS lines that |
095c3752 | 270 | * are not GPIOs (driven by the SPI controller itself). |
8ae12a0d | 271 | * |
33e34dc6 | 272 | * Each SPI master controller can communicate with one or more @spi_device |
8ae12a0d DB |
273 | * children. These make a small bus, sharing MOSI, MISO and SCK signals |
274 | * but not chip select signals. Each device may be configured to use a | |
275 | * different clock rate, since those shared signals are ignored unless | |
276 | * the chip is selected. | |
277 | * | |
278 | * The driver for an SPI controller manages access to those devices through | |
33e34dc6 DB |
279 | * a queue of spi_message transactions, copying data between CPU memory and |
280 | * an SPI slave device. For each such message it queues, it calls the | |
8ae12a0d DB |
281 | * message's completion function when the transaction completes. |
282 | */ | |
283 | struct spi_master { | |
49dce689 | 284 | struct device dev; |
8ae12a0d | 285 | |
2b9603a0 FT |
286 | struct list_head list; |
287 | ||
a020ed75 | 288 | /* other than negative (== assign one dynamically), bus_num is fully |
8ae12a0d | 289 | * board-specific. usually that simplifies to being SOC-specific. |
a020ed75 | 290 | * example: one SOC has three SPI controllers, numbered 0..2, |
8ae12a0d DB |
291 | * and one board's schematics might show it using SPI-2. software |
292 | * would normally use bus_num=2 for that controller. | |
293 | */ | |
a020ed75 | 294 | s16 bus_num; |
8ae12a0d DB |
295 | |
296 | /* chipselects will be integral to many controllers; some others | |
297 | * might use board-specific GPIOs. | |
298 | */ | |
299 | u16 num_chipselect; | |
300 | ||
fd5e191e MR |
301 | /* some SPI controllers pose alignment requirements on DMAable |
302 | * buffers; let protocol drivers know about these requirements. | |
303 | */ | |
304 | u16 dma_alignment; | |
305 | ||
e7db06b5 DB |
306 | /* spi_device.mode flags understood by this controller driver */ |
307 | u16 mode_bits; | |
308 | ||
543bb255 SW |
309 | /* bitmask of supported bits_per_word for transfers */ |
310 | u32 bits_per_word_mask; | |
2922a8de | 311 | #define SPI_BPW_MASK(bits) BIT((bits) - 1) |
4dd9572a | 312 | #define SPI_BIT_MASK(bits) (((bits) == 32) ? ~0UL : (BIT(bits) - 1)) |
eca8960a | 313 | #define SPI_BPW_RANGE_MASK(min, max) (SPI_BIT_MASK(max) - SPI_BIT_MASK(min - 1)) |
543bb255 | 314 | |
70d6027f DB |
315 | /* other constraints relevant to this driver */ |
316 | u16 flags; | |
317 | #define SPI_MASTER_HALF_DUPLEX BIT(0) /* can't do full duplex */ | |
568d0697 DB |
318 | #define SPI_MASTER_NO_RX BIT(1) /* can't do buffer read */ |
319 | #define SPI_MASTER_NO_TX BIT(2) /* can't do buffer write */ | |
70d6027f | 320 | |
cf32b71e ES |
321 | /* lock and mutex for SPI bus locking */ |
322 | spinlock_t bus_lock_spinlock; | |
323 | struct mutex bus_lock_mutex; | |
324 | ||
325 | /* flag indicating that the SPI bus is locked for exclusive use */ | |
326 | bool bus_lock_flag; | |
327 | ||
6e538aaf DB |
328 | /* Setup mode and clock, etc (spi driver may call many times). |
329 | * | |
330 | * IMPORTANT: this may be called when transfers to another | |
331 | * device are active. DO NOT UPDATE SHARED REGISTERS in ways | |
332 | * which could break those transfers. | |
333 | */ | |
8ae12a0d DB |
334 | int (*setup)(struct spi_device *spi); |
335 | ||
336 | /* bidirectional bulk transfers | |
337 | * | |
338 | * + The transfer() method may not sleep; its main role is | |
339 | * just to add the message to the queue. | |
340 | * + For now there's no remove-from-queue operation, or | |
341 | * any other request management | |
342 | * + To a given spi_device, message queueing is pure fifo | |
343 | * | |
344 | * + The master's main job is to process its message queue, | |
345 | * selecting a chip then transferring data | |
346 | * + If there are multiple spi_device children, the i/o queue | |
347 | * arbitration algorithm is unspecified (round robin, fifo, | |
348 | * priority, reservations, preemption, etc) | |
349 | * | |
350 | * + Chipselect stays active during the entire message | |
351 | * (unless modified by spi_transfer.cs_change != 0). | |
352 | * + The message transfers use clock and SPI mode parameters | |
353 | * previously established by setup() for this device | |
354 | */ | |
355 | int (*transfer)(struct spi_device *spi, | |
356 | struct spi_message *mesg); | |
357 | ||
358 | /* called on release() to free memory provided by spi_master */ | |
0ffa0285 | 359 | void (*cleanup)(struct spi_device *spi); |
ffbbdd21 LW |
360 | |
361 | /* | |
362 | * These hooks are for drivers that want to use the generic | |
363 | * master transfer queueing mechanism. If these are used, the | |
364 | * transfer() function above must NOT be specified by the driver. | |
365 | * Over time we expect SPI drivers to be phased over to this API. | |
366 | */ | |
367 | bool queued; | |
368 | struct kthread_worker kworker; | |
369 | struct task_struct *kworker_task; | |
370 | struct kthread_work pump_messages; | |
371 | spinlock_t queue_lock; | |
372 | struct list_head queue; | |
373 | struct spi_message *cur_msg; | |
374 | bool busy; | |
375 | bool running; | |
376 | bool rt; | |
377 | ||
378 | int (*prepare_transfer_hardware)(struct spi_master *master); | |
379 | int (*transfer_one_message)(struct spi_master *master, | |
380 | struct spi_message *mesg); | |
381 | int (*unprepare_transfer_hardware)(struct spi_master *master); | |
74317984 JCPV |
382 | /* gpio chip select */ |
383 | int *cs_gpios; | |
8ae12a0d DB |
384 | }; |
385 | ||
0c868461 DB |
386 | static inline void *spi_master_get_devdata(struct spi_master *master) |
387 | { | |
49dce689 | 388 | return dev_get_drvdata(&master->dev); |
0c868461 DB |
389 | } |
390 | ||
391 | static inline void spi_master_set_devdata(struct spi_master *master, void *data) | |
392 | { | |
49dce689 | 393 | dev_set_drvdata(&master->dev, data); |
0c868461 DB |
394 | } |
395 | ||
396 | static inline struct spi_master *spi_master_get(struct spi_master *master) | |
397 | { | |
49dce689 | 398 | if (!master || !get_device(&master->dev)) |
0c868461 DB |
399 | return NULL; |
400 | return master; | |
401 | } | |
402 | ||
403 | static inline void spi_master_put(struct spi_master *master) | |
404 | { | |
405 | if (master) | |
49dce689 | 406 | put_device(&master->dev); |
0c868461 DB |
407 | } |
408 | ||
ffbbdd21 LW |
409 | /* PM calls that need to be issued by the driver */ |
410 | extern int spi_master_suspend(struct spi_master *master); | |
411 | extern int spi_master_resume(struct spi_master *master); | |
412 | ||
413 | /* Calls the driver make to interact with the message queue */ | |
414 | extern struct spi_message *spi_get_next_queued_message(struct spi_master *master); | |
415 | extern void spi_finalize_current_message(struct spi_master *master); | |
0c868461 | 416 | |
8ae12a0d DB |
417 | /* the spi driver core manages memory for the spi_master classdev */ |
418 | extern struct spi_master * | |
419 | spi_alloc_master(struct device *host, unsigned size); | |
420 | ||
421 | extern int spi_register_master(struct spi_master *master); | |
422 | extern void spi_unregister_master(struct spi_master *master); | |
423 | ||
424 | extern struct spi_master *spi_busnum_to_master(u16 busnum); | |
425 | ||
426 | /*---------------------------------------------------------------------------*/ | |
427 | ||
428 | /* | |
429 | * I/O INTERFACE between SPI controller and protocol drivers | |
430 | * | |
431 | * Protocol drivers use a queue of spi_messages, each transferring data | |
432 | * between the controller and memory buffers. | |
433 | * | |
434 | * The spi_messages themselves consist of a series of read+write transfer | |
435 | * segments. Those segments always read the same number of bits as they | |
436 | * write; but one or the other is easily ignored by passing a null buffer | |
437 | * pointer. (This is unlike most types of I/O API, because SPI hardware | |
438 | * is full duplex.) | |
439 | * | |
440 | * NOTE: Allocation of spi_transfer and spi_message memory is entirely | |
441 | * up to the protocol driver, which guarantees the integrity of both (as | |
442 | * well as the data buffers) for as long as the message is queued. | |
443 | */ | |
444 | ||
445 | /** | |
446 | * struct spi_transfer - a read/write buffer pair | |
8275c642 VW |
447 | * @tx_buf: data to be written (dma-safe memory), or NULL |
448 | * @rx_buf: data to be read (dma-safe memory), or NULL | |
33e34dc6 DB |
449 | * @tx_dma: DMA address of tx_buf, if @spi_message.is_dma_mapped |
450 | * @rx_dma: DMA address of rx_buf, if @spi_message.is_dma_mapped | |
8ae12a0d | 451 | * @len: size of rx and tx buffers (in bytes) |
025dfdaf | 452 | * @speed_hz: Select a speed other than the device default for this |
33e34dc6 | 453 | * transfer. If 0 the default (from @spi_device) is used. |
025dfdaf | 454 | * @bits_per_word: select a bits_per_word other than the device default |
33e34dc6 | 455 | * for this transfer. If 0 the default (from @spi_device) is used. |
8ae12a0d DB |
456 | * @cs_change: affects chipselect after this transfer completes |
457 | * @delay_usecs: microseconds to delay after this transfer before | |
747d844e | 458 | * (optionally) changing the chipselect status, then starting |
33e34dc6 DB |
459 | * the next transfer or completing this @spi_message. |
460 | * @transfer_list: transfers are sequenced through @spi_message.transfers | |
8ae12a0d DB |
461 | * |
462 | * SPI transfers always write the same number of bytes as they read. | |
33e34dc6 | 463 | * Protocol drivers should always provide @rx_buf and/or @tx_buf. |
8ae12a0d DB |
464 | * In some cases, they may also want to provide DMA addresses for |
465 | * the data being transferred; that may reduce overhead, when the | |
466 | * underlying driver uses dma. | |
467 | * | |
4b1badf5 | 468 | * If the transmit buffer is null, zeroes will be shifted out |
33e34dc6 | 469 | * while filling @rx_buf. If the receive buffer is null, the data |
8275c642 VW |
470 | * shifted in will be discarded. Only "len" bytes shift out (or in). |
471 | * It's an error to try to shift out a partial word. (For example, by | |
472 | * shifting out three bytes with word size of sixteen or twenty bits; | |
473 | * the former uses two bytes per word, the latter uses four bytes.) | |
474 | * | |
80224561 DB |
475 | * In-memory data values are always in native CPU byte order, translated |
476 | * from the wire byte order (big-endian except with SPI_LSB_FIRST). So | |
477 | * for example when bits_per_word is sixteen, buffers are 2N bytes long | |
33e34dc6 | 478 | * (@len = 2N) and hold N sixteen bit words in CPU byte order. |
80224561 DB |
479 | * |
480 | * When the word size of the SPI transfer is not a power-of-two multiple | |
481 | * of eight bits, those in-memory words include extra bits. In-memory | |
482 | * words are always seen by protocol drivers as right-justified, so the | |
483 | * undefined (rx) or unused (tx) bits are always the most significant bits. | |
484 | * | |
8275c642 VW |
485 | * All SPI transfers start with the relevant chipselect active. Normally |
486 | * it stays selected until after the last transfer in a message. Drivers | |
33e34dc6 | 487 | * can affect the chipselect signal using cs_change. |
8ae12a0d DB |
488 | * |
489 | * (i) If the transfer isn't the last one in the message, this flag is | |
490 | * used to make the chipselect briefly go inactive in the middle of the | |
491 | * message. Toggling chipselect in this way may be needed to terminate | |
492 | * a chip command, letting a single spi_message perform all of group of | |
493 | * chip transactions together. | |
494 | * | |
495 | * (ii) When the transfer is the last one in the message, the chip may | |
f5a9c77d DB |
496 | * stay selected until the next transfer. On multi-device SPI busses |
497 | * with nothing blocking messages going to other devices, this is just | |
498 | * a performance hint; starting a message to another device deselects | |
499 | * this one. But in other cases, this can be used to ensure correctness. | |
500 | * Some devices need protocol transactions to be built from a series of | |
501 | * spi_message submissions, where the content of one message is determined | |
502 | * by the results of previous messages and where the whole transaction | |
503 | * ends when the chipselect goes intactive. | |
0c868461 DB |
504 | * |
505 | * The code that submits an spi_message (and its spi_transfers) | |
506 | * to the lower layers is responsible for managing its memory. | |
507 | * Zero-initialize every field you don't set up explicitly, to | |
8275c642 VW |
508 | * insulate against future API updates. After you submit a message |
509 | * and its transfers, ignore them until its completion callback. | |
8ae12a0d DB |
510 | */ |
511 | struct spi_transfer { | |
512 | /* it's ok if tx_buf == rx_buf (right?) | |
513 | * for MicroWire, one buffer must be null | |
0c868461 DB |
514 | * buffers must work with dma_*map_single() calls, unless |
515 | * spi_message.is_dma_mapped reports a pre-existing mapping | |
8ae12a0d DB |
516 | */ |
517 | const void *tx_buf; | |
518 | void *rx_buf; | |
519 | unsigned len; | |
520 | ||
521 | dma_addr_t tx_dma; | |
522 | dma_addr_t rx_dma; | |
523 | ||
524 | unsigned cs_change:1; | |
4cff33f9 | 525 | u8 bits_per_word; |
8ae12a0d | 526 | u16 delay_usecs; |
4cff33f9 | 527 | u32 speed_hz; |
8275c642 VW |
528 | |
529 | struct list_head transfer_list; | |
8ae12a0d DB |
530 | }; |
531 | ||
532 | /** | |
533 | * struct spi_message - one multi-segment SPI transaction | |
8275c642 | 534 | * @transfers: list of transfer segments in this transaction |
8ae12a0d DB |
535 | * @spi: SPI device to which the transaction is queued |
536 | * @is_dma_mapped: if true, the caller provided both dma and cpu virtual | |
537 | * addresses for each transfer buffer | |
538 | * @complete: called to report transaction completions | |
539 | * @context: the argument to complete() when it's called | |
b885244e DB |
540 | * @actual_length: the total number of bytes that were transferred in all |
541 | * successful segments | |
8ae12a0d DB |
542 | * @status: zero for success, else negative errno |
543 | * @queue: for use by whichever driver currently owns the message | |
544 | * @state: for use by whichever driver currently owns the message | |
0c868461 | 545 | * |
33e34dc6 | 546 | * A @spi_message is used to execute an atomic sequence of data transfers, |
8275c642 VW |
547 | * each represented by a struct spi_transfer. The sequence is "atomic" |
548 | * in the sense that no other spi_message may use that SPI bus until that | |
549 | * sequence completes. On some systems, many such sequences can execute as | |
550 | * as single programmed DMA transfer. On all systems, these messages are | |
551 | * queued, and might complete after transactions to other devices. Messages | |
552 | * sent to a given spi_device are alway executed in FIFO order. | |
553 | * | |
0c868461 DB |
554 | * The code that submits an spi_message (and its spi_transfers) |
555 | * to the lower layers is responsible for managing its memory. | |
556 | * Zero-initialize every field you don't set up explicitly, to | |
8275c642 VW |
557 | * insulate against future API updates. After you submit a message |
558 | * and its transfers, ignore them until its completion callback. | |
8ae12a0d DB |
559 | */ |
560 | struct spi_message { | |
747d844e | 561 | struct list_head transfers; |
8ae12a0d DB |
562 | |
563 | struct spi_device *spi; | |
564 | ||
565 | unsigned is_dma_mapped:1; | |
566 | ||
567 | /* REVISIT: we might want a flag affecting the behavior of the | |
568 | * last transfer ... allowing things like "read 16 bit length L" | |
569 | * immediately followed by "read L bytes". Basically imposing | |
570 | * a specific message scheduling algorithm. | |
571 | * | |
572 | * Some controller drivers (message-at-a-time queue processing) | |
573 | * could provide that as their default scheduling algorithm. But | |
b885244e | 574 | * others (with multi-message pipelines) could need a flag to |
8ae12a0d DB |
575 | * tell them about such special cases. |
576 | */ | |
577 | ||
578 | /* completion is reported through a callback */ | |
747d844e | 579 | void (*complete)(void *context); |
8ae12a0d DB |
580 | void *context; |
581 | unsigned actual_length; | |
582 | int status; | |
583 | ||
584 | /* for optional use by whatever driver currently owns the | |
585 | * spi_message ... between calls to spi_async and then later | |
586 | * complete(), that's the spi_master controller driver. | |
587 | */ | |
588 | struct list_head queue; | |
589 | void *state; | |
590 | }; | |
591 | ||
8275c642 VW |
592 | static inline void spi_message_init(struct spi_message *m) |
593 | { | |
594 | memset(m, 0, sizeof *m); | |
595 | INIT_LIST_HEAD(&m->transfers); | |
596 | } | |
597 | ||
598 | static inline void | |
599 | spi_message_add_tail(struct spi_transfer *t, struct spi_message *m) | |
600 | { | |
601 | list_add_tail(&t->transfer_list, &m->transfers); | |
602 | } | |
603 | ||
604 | static inline void | |
605 | spi_transfer_del(struct spi_transfer *t) | |
606 | { | |
607 | list_del(&t->transfer_list); | |
608 | } | |
609 | ||
6d9eecd4 LPC |
610 | /** |
611 | * spi_message_init_with_transfers - Initialize spi_message and append transfers | |
612 | * @m: spi_message to be initialized | |
613 | * @xfers: An array of spi transfers | |
614 | * @num_xfers: Number of items in the xfer array | |
615 | * | |
616 | * This function initializes the given spi_message and adds each spi_transfer in | |
617 | * the given array to the message. | |
618 | */ | |
619 | static inline void | |
620 | spi_message_init_with_transfers(struct spi_message *m, | |
621 | struct spi_transfer *xfers, unsigned int num_xfers) | |
622 | { | |
623 | unsigned int i; | |
624 | ||
625 | spi_message_init(m); | |
626 | for (i = 0; i < num_xfers; ++i) | |
627 | spi_message_add_tail(&xfers[i], m); | |
628 | } | |
629 | ||
0c868461 DB |
630 | /* It's fine to embed message and transaction structures in other data |
631 | * structures so long as you don't free them while they're in use. | |
632 | */ | |
633 | ||
634 | static inline struct spi_message *spi_message_alloc(unsigned ntrans, gfp_t flags) | |
635 | { | |
636 | struct spi_message *m; | |
637 | ||
638 | m = kzalloc(sizeof(struct spi_message) | |
639 | + ntrans * sizeof(struct spi_transfer), | |
640 | flags); | |
641 | if (m) { | |
8f53602b | 642 | unsigned i; |
8275c642 VW |
643 | struct spi_transfer *t = (struct spi_transfer *)(m + 1); |
644 | ||
645 | INIT_LIST_HEAD(&m->transfers); | |
646 | for (i = 0; i < ntrans; i++, t++) | |
647 | spi_message_add_tail(t, m); | |
0c868461 DB |
648 | } |
649 | return m; | |
650 | } | |
651 | ||
652 | static inline void spi_message_free(struct spi_message *m) | |
653 | { | |
654 | kfree(m); | |
655 | } | |
656 | ||
7d077197 | 657 | extern int spi_setup(struct spi_device *spi); |
568d0697 | 658 | extern int spi_async(struct spi_device *spi, struct spi_message *message); |
cf32b71e ES |
659 | extern int spi_async_locked(struct spi_device *spi, |
660 | struct spi_message *message); | |
8ae12a0d DB |
661 | |
662 | /*---------------------------------------------------------------------------*/ | |
663 | ||
664 | /* All these synchronous SPI transfer routines are utilities layered | |
665 | * over the core async transfer primitive. Here, "synchronous" means | |
666 | * they will sleep uninterruptibly until the async transfer completes. | |
667 | */ | |
668 | ||
669 | extern int spi_sync(struct spi_device *spi, struct spi_message *message); | |
cf32b71e ES |
670 | extern int spi_sync_locked(struct spi_device *spi, struct spi_message *message); |
671 | extern int spi_bus_lock(struct spi_master *master); | |
672 | extern int spi_bus_unlock(struct spi_master *master); | |
8ae12a0d DB |
673 | |
674 | /** | |
675 | * spi_write - SPI synchronous write | |
676 | * @spi: device to which data will be written | |
677 | * @buf: data buffer | |
678 | * @len: data buffer size | |
33e34dc6 | 679 | * Context: can sleep |
8ae12a0d DB |
680 | * |
681 | * This writes the buffer and returns zero or a negative error code. | |
682 | * Callable only from contexts that can sleep. | |
683 | */ | |
684 | static inline int | |
0c4a1590 | 685 | spi_write(struct spi_device *spi, const void *buf, size_t len) |
8ae12a0d DB |
686 | { |
687 | struct spi_transfer t = { | |
688 | .tx_buf = buf, | |
8ae12a0d | 689 | .len = len, |
8ae12a0d | 690 | }; |
8275c642 | 691 | struct spi_message m; |
8ae12a0d | 692 | |
8275c642 VW |
693 | spi_message_init(&m); |
694 | spi_message_add_tail(&t, &m); | |
8ae12a0d DB |
695 | return spi_sync(spi, &m); |
696 | } | |
697 | ||
698 | /** | |
699 | * spi_read - SPI synchronous read | |
700 | * @spi: device from which data will be read | |
701 | * @buf: data buffer | |
702 | * @len: data buffer size | |
33e34dc6 | 703 | * Context: can sleep |
8ae12a0d | 704 | * |
33e34dc6 | 705 | * This reads the buffer and returns zero or a negative error code. |
8ae12a0d DB |
706 | * Callable only from contexts that can sleep. |
707 | */ | |
708 | static inline int | |
0c4a1590 | 709 | spi_read(struct spi_device *spi, void *buf, size_t len) |
8ae12a0d DB |
710 | { |
711 | struct spi_transfer t = { | |
8ae12a0d DB |
712 | .rx_buf = buf, |
713 | .len = len, | |
8ae12a0d | 714 | }; |
8275c642 | 715 | struct spi_message m; |
8ae12a0d | 716 | |
8275c642 VW |
717 | spi_message_init(&m); |
718 | spi_message_add_tail(&t, &m); | |
8ae12a0d DB |
719 | return spi_sync(spi, &m); |
720 | } | |
721 | ||
6d9eecd4 LPC |
722 | /** |
723 | * spi_sync_transfer - synchronous SPI data transfer | |
724 | * @spi: device with which data will be exchanged | |
725 | * @xfers: An array of spi_transfers | |
726 | * @num_xfers: Number of items in the xfer array | |
727 | * Context: can sleep | |
728 | * | |
729 | * Does a synchronous SPI data transfer of the given spi_transfer array. | |
730 | * | |
731 | * For more specific semantics see spi_sync(). | |
732 | * | |
733 | * It returns zero on success, else a negative error code. | |
734 | */ | |
735 | static inline int | |
736 | spi_sync_transfer(struct spi_device *spi, struct spi_transfer *xfers, | |
737 | unsigned int num_xfers) | |
738 | { | |
739 | struct spi_message msg; | |
740 | ||
741 | spi_message_init_with_transfers(&msg, xfers, num_xfers); | |
742 | ||
743 | return spi_sync(spi, &msg); | |
744 | } | |
745 | ||
0c868461 | 746 | /* this copies txbuf and rxbuf data; for small transfers only! */ |
8ae12a0d | 747 | extern int spi_write_then_read(struct spi_device *spi, |
0c4a1590 MB |
748 | const void *txbuf, unsigned n_tx, |
749 | void *rxbuf, unsigned n_rx); | |
8ae12a0d DB |
750 | |
751 | /** | |
752 | * spi_w8r8 - SPI synchronous 8 bit write followed by 8 bit read | |
753 | * @spi: device with which data will be exchanged | |
754 | * @cmd: command to be written before data is read back | |
33e34dc6 | 755 | * Context: can sleep |
8ae12a0d DB |
756 | * |
757 | * This returns the (unsigned) eight bit number returned by the | |
758 | * device, or else a negative error code. Callable only from | |
759 | * contexts that can sleep. | |
760 | */ | |
761 | static inline ssize_t spi_w8r8(struct spi_device *spi, u8 cmd) | |
762 | { | |
763 | ssize_t status; | |
764 | u8 result; | |
765 | ||
766 | status = spi_write_then_read(spi, &cmd, 1, &result, 1); | |
767 | ||
768 | /* return negative errno or unsigned value */ | |
769 | return (status < 0) ? status : result; | |
770 | } | |
771 | ||
772 | /** | |
773 | * spi_w8r16 - SPI synchronous 8 bit write followed by 16 bit read | |
774 | * @spi: device with which data will be exchanged | |
775 | * @cmd: command to be written before data is read back | |
33e34dc6 | 776 | * Context: can sleep |
8ae12a0d DB |
777 | * |
778 | * This returns the (unsigned) sixteen bit number returned by the | |
779 | * device, or else a negative error code. Callable only from | |
780 | * contexts that can sleep. | |
781 | * | |
782 | * The number is returned in wire-order, which is at least sometimes | |
783 | * big-endian. | |
784 | */ | |
785 | static inline ssize_t spi_w8r16(struct spi_device *spi, u8 cmd) | |
786 | { | |
787 | ssize_t status; | |
788 | u16 result; | |
789 | ||
790 | status = spi_write_then_read(spi, &cmd, 1, (u8 *) &result, 2); | |
791 | ||
792 | /* return negative errno or unsigned value */ | |
793 | return (status < 0) ? status : result; | |
794 | } | |
795 | ||
796 | /*---------------------------------------------------------------------------*/ | |
797 | ||
798 | /* | |
799 | * INTERFACE between board init code and SPI infrastructure. | |
800 | * | |
801 | * No SPI driver ever sees these SPI device table segments, but | |
802 | * it's how the SPI core (or adapters that get hotplugged) grows | |
803 | * the driver model tree. | |
804 | * | |
805 | * As a rule, SPI devices can't be probed. Instead, board init code | |
806 | * provides a table listing the devices which are present, with enough | |
807 | * information to bind and set up the device's driver. There's basic | |
808 | * support for nonstatic configurations too; enough to handle adding | |
809 | * parport adapters, or microcontrollers acting as USB-to-SPI bridges. | |
810 | */ | |
811 | ||
2604288f DB |
812 | /** |
813 | * struct spi_board_info - board-specific template for a SPI device | |
814 | * @modalias: Initializes spi_device.modalias; identifies the driver. | |
815 | * @platform_data: Initializes spi_device.platform_data; the particular | |
816 | * data stored there is driver-specific. | |
817 | * @controller_data: Initializes spi_device.controller_data; some | |
818 | * controllers need hints about hardware setup, e.g. for DMA. | |
819 | * @irq: Initializes spi_device.irq; depends on how the board is wired. | |
820 | * @max_speed_hz: Initializes spi_device.max_speed_hz; based on limits | |
821 | * from the chip datasheet and board-specific signal quality issues. | |
822 | * @bus_num: Identifies which spi_master parents the spi_device; unused | |
823 | * by spi_new_device(), and otherwise depends on board wiring. | |
824 | * @chip_select: Initializes spi_device.chip_select; depends on how | |
825 | * the board is wired. | |
826 | * @mode: Initializes spi_device.mode; based on the chip datasheet, board | |
827 | * wiring (some devices support both 3WIRE and standard modes), and | |
828 | * possibly presence of an inverter in the chipselect path. | |
829 | * | |
830 | * When adding new SPI devices to the device tree, these structures serve | |
831 | * as a partial device template. They hold information which can't always | |
832 | * be determined by drivers. Information that probe() can establish (such | |
833 | * as the default transfer wordsize) is not included here. | |
834 | * | |
835 | * These structures are used in two places. Their primary role is to | |
836 | * be stored in tables of board-specific device descriptors, which are | |
837 | * declared early in board initialization and then used (much later) to | |
838 | * populate a controller's device tree after the that controller's driver | |
839 | * initializes. A secondary (and atypical) role is as a parameter to | |
840 | * spi_new_device() call, which happens after those controller drivers | |
841 | * are active in some dynamic board configuration models. | |
842 | */ | |
8ae12a0d DB |
843 | struct spi_board_info { |
844 | /* the device name and module name are coupled, like platform_bus; | |
845 | * "modalias" is normally the driver name. | |
846 | * | |
847 | * platform_data goes to spi_device.dev.platform_data, | |
b885244e | 848 | * controller_data goes to spi_device.controller_data, |
8ae12a0d DB |
849 | * irq is copied too |
850 | */ | |
75368bf6 | 851 | char modalias[SPI_NAME_SIZE]; |
8ae12a0d | 852 | const void *platform_data; |
b885244e | 853 | void *controller_data; |
8ae12a0d DB |
854 | int irq; |
855 | ||
856 | /* slower signaling on noisy or low voltage boards */ | |
857 | u32 max_speed_hz; | |
858 | ||
859 | ||
860 | /* bus_num is board specific and matches the bus_num of some | |
861 | * spi_master that will probably be registered later. | |
862 | * | |
863 | * chip_select reflects how this chip is wired to that master; | |
864 | * it's less than num_chipselect. | |
865 | */ | |
866 | u16 bus_num; | |
867 | u16 chip_select; | |
868 | ||
980a01c9 DB |
869 | /* mode becomes spi_device.mode, and is essential for chips |
870 | * where the default of SPI_CS_HIGH = 0 is wrong. | |
871 | */ | |
872 | u8 mode; | |
873 | ||
8ae12a0d DB |
874 | /* ... may need additional spi_device chip config data here. |
875 | * avoid stuff protocol drivers can set; but include stuff | |
876 | * needed to behave without being bound to a driver: | |
8ae12a0d DB |
877 | * - quirks like clock rate mattering when not selected |
878 | */ | |
879 | }; | |
880 | ||
881 | #ifdef CONFIG_SPI | |
882 | extern int | |
883 | spi_register_board_info(struct spi_board_info const *info, unsigned n); | |
884 | #else | |
885 | /* board init code may ignore whether SPI is configured or not */ | |
886 | static inline int | |
887 | spi_register_board_info(struct spi_board_info const *info, unsigned n) | |
888 | { return 0; } | |
889 | #endif | |
890 | ||
891 | ||
892 | /* If you're hotplugging an adapter with devices (parport, usb, etc) | |
0c868461 DB |
893 | * use spi_new_device() to describe each device. You can also call |
894 | * spi_unregister_device() to start making that device vanish, but | |
895 | * normally that would be handled by spi_unregister_master(). | |
dc87c98e GL |
896 | * |
897 | * You can also use spi_alloc_device() and spi_add_device() to use a two | |
898 | * stage registration sequence for each spi_device. This gives the caller | |
899 | * some more control over the spi_device structure before it is registered, | |
900 | * but requires that caller to initialize fields that would otherwise | |
901 | * be defined using the board info. | |
8ae12a0d | 902 | */ |
dc87c98e GL |
903 | extern struct spi_device * |
904 | spi_alloc_device(struct spi_master *master); | |
905 | ||
906 | extern int | |
907 | spi_add_device(struct spi_device *spi); | |
908 | ||
8ae12a0d DB |
909 | extern struct spi_device * |
910 | spi_new_device(struct spi_master *, struct spi_board_info *); | |
911 | ||
912 | static inline void | |
913 | spi_unregister_device(struct spi_device *spi) | |
914 | { | |
915 | if (spi) | |
916 | device_unregister(&spi->dev); | |
917 | } | |
918 | ||
75368bf6 AV |
919 | extern const struct spi_device_id * |
920 | spi_get_device_id(const struct spi_device *sdev); | |
921 | ||
8ae12a0d | 922 | #endif /* __LINUX_SPI_H */ |