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1 | /* |
2 | * Copyright (C) 2005 David Brownell | |
3 | * | |
4 | * This program is free software; you can redistribute it and/or modify | |
5 | * it under the terms of the GNU General Public License as published by | |
6 | * the Free Software Foundation; either version 2 of the License, or | |
7 | * (at your option) any later version. | |
8 | * | |
9 | * This program is distributed in the hope that it will be useful, | |
10 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
11 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
12 | * GNU General Public License for more details. | |
13 | * | |
14 | * You should have received a copy of the GNU General Public License | |
15 | * along with this program; if not, write to the Free Software | |
16 | * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. | |
17 | */ | |
18 | ||
19 | #ifndef __LINUX_SPI_H | |
20 | #define __LINUX_SPI_H | |
21 | ||
22 | /* | |
b885244e | 23 | * INTERFACES between SPI master-side drivers and SPI infrastructure. |
8ae12a0d | 24 | * (There's no SPI slave support for Linux yet...) |
8ae12a0d DB |
25 | */ |
26 | extern struct bus_type spi_bus_type; | |
27 | ||
28 | /** | |
29 | * struct spi_device - Master side proxy for an SPI slave device | |
30 | * @dev: Driver model representation of the device. | |
31 | * @master: SPI controller used with the device. | |
32 | * @max_speed_hz: Maximum clock rate to be used with this chip | |
33 | * (on this board); may be changed by the device's driver. | |
4cff33f9 | 34 | * The spi_transfer.speed_hz can override this for each transfer. |
8ae12a0d DB |
35 | * @chip-select: Chipselect, distinguishing chips handled by "master". |
36 | * @mode: The spi mode defines how data is clocked out and in. | |
37 | * This may be changed by the device's driver. | |
38 | * @bits_per_word: Data transfers involve one or more words; word sizes | |
747d844e | 39 | * like eight or 12 bits are common. In-memory wordsizes are |
8ae12a0d DB |
40 | * powers of two bytes (e.g. 20 bit samples use 32 bits). |
41 | * This may be changed by the device's driver. | |
4cff33f9 | 42 | * The spi_transfer.bits_per_word can override this for each transfer. |
8ae12a0d | 43 | * @irq: Negative, or the number passed to request_irq() to receive |
747d844e | 44 | * interrupts from this device. |
8ae12a0d | 45 | * @controller_state: Controller's runtime state |
b885244e | 46 | * @controller_data: Board-specific definitions for controller, such as |
747d844e | 47 | * FIFO initialization parameters; from board_info.controller_data |
8ae12a0d DB |
48 | * |
49 | * An spi_device is used to interchange data between an SPI slave | |
50 | * (usually a discrete chip) and CPU memory. | |
51 | * | |
52 | * In "dev", the platform_data is used to hold information about this | |
53 | * device that's meaningful to the device's protocol driver, but not | |
54 | * to its controller. One example might be an identifier for a chip | |
55 | * variant with slightly different functionality. | |
56 | */ | |
57 | struct spi_device { | |
58 | struct device dev; | |
59 | struct spi_master *master; | |
60 | u32 max_speed_hz; | |
61 | u8 chip_select; | |
62 | u8 mode; | |
b885244e DB |
63 | #define SPI_CPHA 0x01 /* clock phase */ |
64 | #define SPI_CPOL 0x02 /* clock polarity */ | |
0c868461 DB |
65 | #define SPI_MODE_0 (0|0) /* (original MicroWire) */ |
66 | #define SPI_MODE_1 (0|SPI_CPHA) | |
8ae12a0d DB |
67 | #define SPI_MODE_2 (SPI_CPOL|0) |
68 | #define SPI_MODE_3 (SPI_CPOL|SPI_CPHA) | |
b885244e | 69 | #define SPI_CS_HIGH 0x04 /* chipselect active high? */ |
8ae12a0d DB |
70 | u8 bits_per_word; |
71 | int irq; | |
72 | void *controller_state; | |
b885244e | 73 | void *controller_data; |
8ae12a0d DB |
74 | const char *modalias; |
75 | ||
76 | // likely need more hooks for more protocol options affecting how | |
b885244e | 77 | // the controller talks to each chip, like: |
8ae12a0d DB |
78 | // - bit order (default is wordwise msb-first) |
79 | // - memory packing (12 bit samples into low bits, others zeroed) | |
80 | // - priority | |
b885244e | 81 | // - drop chipselect after each word |
8ae12a0d DB |
82 | // - chipselect delays |
83 | // - ... | |
84 | }; | |
85 | ||
86 | static inline struct spi_device *to_spi_device(struct device *dev) | |
87 | { | |
b885244e | 88 | return dev ? container_of(dev, struct spi_device, dev) : NULL; |
8ae12a0d DB |
89 | } |
90 | ||
91 | /* most drivers won't need to care about device refcounting */ | |
92 | static inline struct spi_device *spi_dev_get(struct spi_device *spi) | |
93 | { | |
94 | return (spi && get_device(&spi->dev)) ? spi : NULL; | |
95 | } | |
96 | ||
97 | static inline void spi_dev_put(struct spi_device *spi) | |
98 | { | |
99 | if (spi) | |
100 | put_device(&spi->dev); | |
101 | } | |
102 | ||
103 | /* ctldata is for the bus_master driver's runtime state */ | |
104 | static inline void *spi_get_ctldata(struct spi_device *spi) | |
105 | { | |
106 | return spi->controller_state; | |
107 | } | |
108 | ||
109 | static inline void spi_set_ctldata(struct spi_device *spi, void *state) | |
110 | { | |
111 | spi->controller_state = state; | |
112 | } | |
113 | ||
114 | ||
115 | struct spi_message; | |
116 | ||
117 | ||
b885244e DB |
118 | |
119 | struct spi_driver { | |
120 | int (*probe)(struct spi_device *spi); | |
121 | int (*remove)(struct spi_device *spi); | |
122 | void (*shutdown)(struct spi_device *spi); | |
123 | int (*suspend)(struct spi_device *spi, pm_message_t mesg); | |
124 | int (*resume)(struct spi_device *spi); | |
125 | struct device_driver driver; | |
126 | }; | |
127 | ||
128 | static inline struct spi_driver *to_spi_driver(struct device_driver *drv) | |
129 | { | |
130 | return drv ? container_of(drv, struct spi_driver, driver) : NULL; | |
131 | } | |
132 | ||
133 | extern int spi_register_driver(struct spi_driver *sdrv); | |
134 | ||
135 | static inline void spi_unregister_driver(struct spi_driver *sdrv) | |
136 | { | |
137 | if (!sdrv) | |
138 | return; | |
139 | driver_unregister(&sdrv->driver); | |
140 | } | |
141 | ||
142 | ||
143 | ||
8ae12a0d DB |
144 | /** |
145 | * struct spi_master - interface to SPI master controller | |
146 | * @cdev: class interface to this driver | |
147 | * @bus_num: board-specific (and often SOC-specific) identifier for a | |
747d844e | 148 | * given SPI controller. |
b885244e | 149 | * @num_chipselect: chipselects are used to distinguish individual |
747d844e DB |
150 | * SPI slaves, and are numbered from zero to num_chipselects. |
151 | * each slave has a chipselect signal, but it's common that not | |
152 | * every chipselect is connected to a slave. | |
8ae12a0d | 153 | * @setup: updates the device mode and clocking records used by a |
747d844e | 154 | * device's SPI controller; protocol code may call this. |
8ae12a0d DB |
155 | * @transfer: adds a message to the controller's transfer queue. |
156 | * @cleanup: frees controller-specific state | |
157 | * | |
158 | * Each SPI master controller can communicate with one or more spi_device | |
159 | * children. These make a small bus, sharing MOSI, MISO and SCK signals | |
160 | * but not chip select signals. Each device may be configured to use a | |
161 | * different clock rate, since those shared signals are ignored unless | |
162 | * the chip is selected. | |
163 | * | |
164 | * The driver for an SPI controller manages access to those devices through | |
165 | * a queue of spi_message transactions, copyin data between CPU memory and | |
166 | * an SPI slave device). For each such message it queues, it calls the | |
167 | * message's completion function when the transaction completes. | |
168 | */ | |
169 | struct spi_master { | |
170 | struct class_device cdev; | |
171 | ||
172 | /* other than zero (== assign one dynamically), bus_num is fully | |
173 | * board-specific. usually that simplifies to being SOC-specific. | |
174 | * example: one SOC has three SPI controllers, numbered 1..3, | |
175 | * and one board's schematics might show it using SPI-2. software | |
176 | * would normally use bus_num=2 for that controller. | |
177 | */ | |
178 | u16 bus_num; | |
179 | ||
180 | /* chipselects will be integral to many controllers; some others | |
181 | * might use board-specific GPIOs. | |
182 | */ | |
183 | u16 num_chipselect; | |
184 | ||
185 | /* setup mode and clock, etc (spi driver may call many times) */ | |
186 | int (*setup)(struct spi_device *spi); | |
187 | ||
188 | /* bidirectional bulk transfers | |
189 | * | |
190 | * + The transfer() method may not sleep; its main role is | |
191 | * just to add the message to the queue. | |
192 | * + For now there's no remove-from-queue operation, or | |
193 | * any other request management | |
194 | * + To a given spi_device, message queueing is pure fifo | |
195 | * | |
196 | * + The master's main job is to process its message queue, | |
197 | * selecting a chip then transferring data | |
198 | * + If there are multiple spi_device children, the i/o queue | |
199 | * arbitration algorithm is unspecified (round robin, fifo, | |
200 | * priority, reservations, preemption, etc) | |
201 | * | |
202 | * + Chipselect stays active during the entire message | |
203 | * (unless modified by spi_transfer.cs_change != 0). | |
204 | * + The message transfers use clock and SPI mode parameters | |
205 | * previously established by setup() for this device | |
206 | */ | |
207 | int (*transfer)(struct spi_device *spi, | |
208 | struct spi_message *mesg); | |
209 | ||
210 | /* called on release() to free memory provided by spi_master */ | |
211 | void (*cleanup)(const struct spi_device *spi); | |
212 | }; | |
213 | ||
0c868461 DB |
214 | static inline void *spi_master_get_devdata(struct spi_master *master) |
215 | { | |
216 | return class_get_devdata(&master->cdev); | |
217 | } | |
218 | ||
219 | static inline void spi_master_set_devdata(struct spi_master *master, void *data) | |
220 | { | |
221 | class_set_devdata(&master->cdev, data); | |
222 | } | |
223 | ||
224 | static inline struct spi_master *spi_master_get(struct spi_master *master) | |
225 | { | |
226 | if (!master || !class_device_get(&master->cdev)) | |
227 | return NULL; | |
228 | return master; | |
229 | } | |
230 | ||
231 | static inline void spi_master_put(struct spi_master *master) | |
232 | { | |
233 | if (master) | |
234 | class_device_put(&master->cdev); | |
235 | } | |
236 | ||
237 | ||
8ae12a0d DB |
238 | /* the spi driver core manages memory for the spi_master classdev */ |
239 | extern struct spi_master * | |
240 | spi_alloc_master(struct device *host, unsigned size); | |
241 | ||
242 | extern int spi_register_master(struct spi_master *master); | |
243 | extern void spi_unregister_master(struct spi_master *master); | |
244 | ||
245 | extern struct spi_master *spi_busnum_to_master(u16 busnum); | |
246 | ||
247 | /*---------------------------------------------------------------------------*/ | |
248 | ||
249 | /* | |
250 | * I/O INTERFACE between SPI controller and protocol drivers | |
251 | * | |
252 | * Protocol drivers use a queue of spi_messages, each transferring data | |
253 | * between the controller and memory buffers. | |
254 | * | |
255 | * The spi_messages themselves consist of a series of read+write transfer | |
256 | * segments. Those segments always read the same number of bits as they | |
257 | * write; but one or the other is easily ignored by passing a null buffer | |
258 | * pointer. (This is unlike most types of I/O API, because SPI hardware | |
259 | * is full duplex.) | |
260 | * | |
261 | * NOTE: Allocation of spi_transfer and spi_message memory is entirely | |
262 | * up to the protocol driver, which guarantees the integrity of both (as | |
263 | * well as the data buffers) for as long as the message is queued. | |
264 | */ | |
265 | ||
266 | /** | |
267 | * struct spi_transfer - a read/write buffer pair | |
8275c642 VW |
268 | * @tx_buf: data to be written (dma-safe memory), or NULL |
269 | * @rx_buf: data to be read (dma-safe memory), or NULL | |
270 | * @tx_dma: DMA address of tx_buf, if spi_message.is_dma_mapped | |
271 | * @rx_dma: DMA address of rx_buf, if spi_message.is_dma_mapped | |
8ae12a0d | 272 | * @len: size of rx and tx buffers (in bytes) |
4cff33f9 ID |
273 | * @speed_hz: Select a speed other then the device default for this |
274 | * transfer. If 0 the default (from spi_device) is used. | |
275 | * @bits_per_word: select a bits_per_word other then the device default | |
276 | * for this transfer. If 0 the default (from spi_device) is used. | |
8ae12a0d DB |
277 | * @cs_change: affects chipselect after this transfer completes |
278 | * @delay_usecs: microseconds to delay after this transfer before | |
747d844e DB |
279 | * (optionally) changing the chipselect status, then starting |
280 | * the next transfer or completing this spi_message. | |
8275c642 | 281 | * @transfer_list: transfers are sequenced through spi_message.transfers |
8ae12a0d DB |
282 | * |
283 | * SPI transfers always write the same number of bytes as they read. | |
284 | * Protocol drivers should always provide rx_buf and/or tx_buf. | |
285 | * In some cases, they may also want to provide DMA addresses for | |
286 | * the data being transferred; that may reduce overhead, when the | |
287 | * underlying driver uses dma. | |
288 | * | |
8275c642 VW |
289 | * If the transmit buffer is null, undefined data will be shifted out |
290 | * while filling rx_buf. If the receive buffer is null, the data | |
291 | * shifted in will be discarded. Only "len" bytes shift out (or in). | |
292 | * It's an error to try to shift out a partial word. (For example, by | |
293 | * shifting out three bytes with word size of sixteen or twenty bits; | |
294 | * the former uses two bytes per word, the latter uses four bytes.) | |
295 | * | |
296 | * All SPI transfers start with the relevant chipselect active. Normally | |
297 | * it stays selected until after the last transfer in a message. Drivers | |
298 | * can affect the chipselect signal using cs_change: | |
8ae12a0d DB |
299 | * |
300 | * (i) If the transfer isn't the last one in the message, this flag is | |
301 | * used to make the chipselect briefly go inactive in the middle of the | |
302 | * message. Toggling chipselect in this way may be needed to terminate | |
303 | * a chip command, letting a single spi_message perform all of group of | |
304 | * chip transactions together. | |
305 | * | |
306 | * (ii) When the transfer is the last one in the message, the chip may | |
307 | * stay selected until the next transfer. This is purely a performance | |
308 | * hint; the controller driver may need to select a different device | |
309 | * for the next message. | |
0c868461 DB |
310 | * |
311 | * The code that submits an spi_message (and its spi_transfers) | |
312 | * to the lower layers is responsible for managing its memory. | |
313 | * Zero-initialize every field you don't set up explicitly, to | |
8275c642 VW |
314 | * insulate against future API updates. After you submit a message |
315 | * and its transfers, ignore them until its completion callback. | |
8ae12a0d DB |
316 | */ |
317 | struct spi_transfer { | |
318 | /* it's ok if tx_buf == rx_buf (right?) | |
319 | * for MicroWire, one buffer must be null | |
0c868461 DB |
320 | * buffers must work with dma_*map_single() calls, unless |
321 | * spi_message.is_dma_mapped reports a pre-existing mapping | |
8ae12a0d DB |
322 | */ |
323 | const void *tx_buf; | |
324 | void *rx_buf; | |
325 | unsigned len; | |
326 | ||
327 | dma_addr_t tx_dma; | |
328 | dma_addr_t rx_dma; | |
329 | ||
330 | unsigned cs_change:1; | |
4cff33f9 | 331 | u8 bits_per_word; |
8ae12a0d | 332 | u16 delay_usecs; |
4cff33f9 | 333 | u32 speed_hz; |
8275c642 VW |
334 | |
335 | struct list_head transfer_list; | |
8ae12a0d DB |
336 | }; |
337 | ||
338 | /** | |
339 | * struct spi_message - one multi-segment SPI transaction | |
8275c642 | 340 | * @transfers: list of transfer segments in this transaction |
8ae12a0d DB |
341 | * @spi: SPI device to which the transaction is queued |
342 | * @is_dma_mapped: if true, the caller provided both dma and cpu virtual | |
343 | * addresses for each transfer buffer | |
344 | * @complete: called to report transaction completions | |
345 | * @context: the argument to complete() when it's called | |
b885244e DB |
346 | * @actual_length: the total number of bytes that were transferred in all |
347 | * successful segments | |
8ae12a0d DB |
348 | * @status: zero for success, else negative errno |
349 | * @queue: for use by whichever driver currently owns the message | |
350 | * @state: for use by whichever driver currently owns the message | |
0c868461 | 351 | * |
8275c642 VW |
352 | * An spi_message is used to execute an atomic sequence of data transfers, |
353 | * each represented by a struct spi_transfer. The sequence is "atomic" | |
354 | * in the sense that no other spi_message may use that SPI bus until that | |
355 | * sequence completes. On some systems, many such sequences can execute as | |
356 | * as single programmed DMA transfer. On all systems, these messages are | |
357 | * queued, and might complete after transactions to other devices. Messages | |
358 | * sent to a given spi_device are alway executed in FIFO order. | |
359 | * | |
0c868461 DB |
360 | * The code that submits an spi_message (and its spi_transfers) |
361 | * to the lower layers is responsible for managing its memory. | |
362 | * Zero-initialize every field you don't set up explicitly, to | |
8275c642 VW |
363 | * insulate against future API updates. After you submit a message |
364 | * and its transfers, ignore them until its completion callback. | |
8ae12a0d DB |
365 | */ |
366 | struct spi_message { | |
747d844e | 367 | struct list_head transfers; |
8ae12a0d DB |
368 | |
369 | struct spi_device *spi; | |
370 | ||
371 | unsigned is_dma_mapped:1; | |
372 | ||
373 | /* REVISIT: we might want a flag affecting the behavior of the | |
374 | * last transfer ... allowing things like "read 16 bit length L" | |
375 | * immediately followed by "read L bytes". Basically imposing | |
376 | * a specific message scheduling algorithm. | |
377 | * | |
378 | * Some controller drivers (message-at-a-time queue processing) | |
379 | * could provide that as their default scheduling algorithm. But | |
b885244e | 380 | * others (with multi-message pipelines) could need a flag to |
8ae12a0d DB |
381 | * tell them about such special cases. |
382 | */ | |
383 | ||
384 | /* completion is reported through a callback */ | |
747d844e | 385 | void (*complete)(void *context); |
8ae12a0d DB |
386 | void *context; |
387 | unsigned actual_length; | |
388 | int status; | |
389 | ||
390 | /* for optional use by whatever driver currently owns the | |
391 | * spi_message ... between calls to spi_async and then later | |
392 | * complete(), that's the spi_master controller driver. | |
393 | */ | |
394 | struct list_head queue; | |
395 | void *state; | |
396 | }; | |
397 | ||
8275c642 VW |
398 | static inline void spi_message_init(struct spi_message *m) |
399 | { | |
400 | memset(m, 0, sizeof *m); | |
401 | INIT_LIST_HEAD(&m->transfers); | |
402 | } | |
403 | ||
404 | static inline void | |
405 | spi_message_add_tail(struct spi_transfer *t, struct spi_message *m) | |
406 | { | |
407 | list_add_tail(&t->transfer_list, &m->transfers); | |
408 | } | |
409 | ||
410 | static inline void | |
411 | spi_transfer_del(struct spi_transfer *t) | |
412 | { | |
413 | list_del(&t->transfer_list); | |
414 | } | |
415 | ||
0c868461 DB |
416 | /* It's fine to embed message and transaction structures in other data |
417 | * structures so long as you don't free them while they're in use. | |
418 | */ | |
419 | ||
420 | static inline struct spi_message *spi_message_alloc(unsigned ntrans, gfp_t flags) | |
421 | { | |
422 | struct spi_message *m; | |
423 | ||
424 | m = kzalloc(sizeof(struct spi_message) | |
425 | + ntrans * sizeof(struct spi_transfer), | |
426 | flags); | |
427 | if (m) { | |
8275c642 VW |
428 | int i; |
429 | struct spi_transfer *t = (struct spi_transfer *)(m + 1); | |
430 | ||
431 | INIT_LIST_HEAD(&m->transfers); | |
432 | for (i = 0; i < ntrans; i++, t++) | |
433 | spi_message_add_tail(t, m); | |
0c868461 DB |
434 | } |
435 | return m; | |
436 | } | |
437 | ||
438 | static inline void spi_message_free(struct spi_message *m) | |
439 | { | |
440 | kfree(m); | |
441 | } | |
442 | ||
8ae12a0d DB |
443 | /** |
444 | * spi_setup -- setup SPI mode and clock rate | |
445 | * @spi: the device whose settings are being modified | |
446 | * | |
447 | * SPI protocol drivers may need to update the transfer mode if the | |
448 | * device doesn't work with the mode 0 default. They may likewise need | |
449 | * to update clock rates or word sizes from initial values. This function | |
450 | * changes those settings, and must be called from a context that can sleep. | |
8275c642 VW |
451 | * The changes take effect the next time the device is selected and data |
452 | * is transferred to or from it. | |
8ae12a0d DB |
453 | */ |
454 | static inline int | |
455 | spi_setup(struct spi_device *spi) | |
456 | { | |
457 | return spi->master->setup(spi); | |
458 | } | |
459 | ||
460 | ||
461 | /** | |
462 | * spi_async -- asynchronous SPI transfer | |
463 | * @spi: device with which data will be exchanged | |
464 | * @message: describes the data transfers, including completion callback | |
465 | * | |
466 | * This call may be used in_irq and other contexts which can't sleep, | |
467 | * as well as from task contexts which can sleep. | |
468 | * | |
469 | * The completion callback is invoked in a context which can't sleep. | |
470 | * Before that invocation, the value of message->status is undefined. | |
471 | * When the callback is issued, message->status holds either zero (to | |
0c868461 DB |
472 | * indicate complete success) or a negative error code. After that |
473 | * callback returns, the driver which issued the transfer request may | |
474 | * deallocate the associated memory; it's no longer in use by any SPI | |
475 | * core or controller driver code. | |
8ae12a0d DB |
476 | * |
477 | * Note that although all messages to a spi_device are handled in | |
478 | * FIFO order, messages may go to different devices in other orders. | |
479 | * Some device might be higher priority, or have various "hard" access | |
480 | * time requirements, for example. | |
b885244e DB |
481 | * |
482 | * On detection of any fault during the transfer, processing of | |
483 | * the entire message is aborted, and the device is deselected. | |
484 | * Until returning from the associated message completion callback, | |
485 | * no other spi_message queued to that device will be processed. | |
486 | * (This rule applies equally to all the synchronous transfer calls, | |
487 | * which are wrappers around this core asynchronous primitive.) | |
8ae12a0d DB |
488 | */ |
489 | static inline int | |
490 | spi_async(struct spi_device *spi, struct spi_message *message) | |
491 | { | |
492 | message->spi = spi; | |
493 | return spi->master->transfer(spi, message); | |
494 | } | |
495 | ||
496 | /*---------------------------------------------------------------------------*/ | |
497 | ||
498 | /* All these synchronous SPI transfer routines are utilities layered | |
499 | * over the core async transfer primitive. Here, "synchronous" means | |
500 | * they will sleep uninterruptibly until the async transfer completes. | |
501 | */ | |
502 | ||
503 | extern int spi_sync(struct spi_device *spi, struct spi_message *message); | |
504 | ||
505 | /** | |
506 | * spi_write - SPI synchronous write | |
507 | * @spi: device to which data will be written | |
508 | * @buf: data buffer | |
509 | * @len: data buffer size | |
510 | * | |
511 | * This writes the buffer and returns zero or a negative error code. | |
512 | * Callable only from contexts that can sleep. | |
513 | */ | |
514 | static inline int | |
515 | spi_write(struct spi_device *spi, const u8 *buf, size_t len) | |
516 | { | |
517 | struct spi_transfer t = { | |
518 | .tx_buf = buf, | |
8ae12a0d | 519 | .len = len, |
8ae12a0d | 520 | }; |
8275c642 | 521 | struct spi_message m; |
8ae12a0d | 522 | |
8275c642 VW |
523 | spi_message_init(&m); |
524 | spi_message_add_tail(&t, &m); | |
8ae12a0d DB |
525 | return spi_sync(spi, &m); |
526 | } | |
527 | ||
528 | /** | |
529 | * spi_read - SPI synchronous read | |
530 | * @spi: device from which data will be read | |
531 | * @buf: data buffer | |
532 | * @len: data buffer size | |
533 | * | |
534 | * This writes the buffer and returns zero or a negative error code. | |
535 | * Callable only from contexts that can sleep. | |
536 | */ | |
537 | static inline int | |
538 | spi_read(struct spi_device *spi, u8 *buf, size_t len) | |
539 | { | |
540 | struct spi_transfer t = { | |
8ae12a0d DB |
541 | .rx_buf = buf, |
542 | .len = len, | |
8ae12a0d | 543 | }; |
8275c642 | 544 | struct spi_message m; |
8ae12a0d | 545 | |
8275c642 VW |
546 | spi_message_init(&m); |
547 | spi_message_add_tail(&t, &m); | |
8ae12a0d DB |
548 | return spi_sync(spi, &m); |
549 | } | |
550 | ||
0c868461 | 551 | /* this copies txbuf and rxbuf data; for small transfers only! */ |
8ae12a0d DB |
552 | extern int spi_write_then_read(struct spi_device *spi, |
553 | const u8 *txbuf, unsigned n_tx, | |
554 | u8 *rxbuf, unsigned n_rx); | |
555 | ||
556 | /** | |
557 | * spi_w8r8 - SPI synchronous 8 bit write followed by 8 bit read | |
558 | * @spi: device with which data will be exchanged | |
559 | * @cmd: command to be written before data is read back | |
560 | * | |
561 | * This returns the (unsigned) eight bit number returned by the | |
562 | * device, or else a negative error code. Callable only from | |
563 | * contexts that can sleep. | |
564 | */ | |
565 | static inline ssize_t spi_w8r8(struct spi_device *spi, u8 cmd) | |
566 | { | |
567 | ssize_t status; | |
568 | u8 result; | |
569 | ||
570 | status = spi_write_then_read(spi, &cmd, 1, &result, 1); | |
571 | ||
572 | /* return negative errno or unsigned value */ | |
573 | return (status < 0) ? status : result; | |
574 | } | |
575 | ||
576 | /** | |
577 | * spi_w8r16 - SPI synchronous 8 bit write followed by 16 bit read | |
578 | * @spi: device with which data will be exchanged | |
579 | * @cmd: command to be written before data is read back | |
580 | * | |
581 | * This returns the (unsigned) sixteen bit number returned by the | |
582 | * device, or else a negative error code. Callable only from | |
583 | * contexts that can sleep. | |
584 | * | |
585 | * The number is returned in wire-order, which is at least sometimes | |
586 | * big-endian. | |
587 | */ | |
588 | static inline ssize_t spi_w8r16(struct spi_device *spi, u8 cmd) | |
589 | { | |
590 | ssize_t status; | |
591 | u16 result; | |
592 | ||
593 | status = spi_write_then_read(spi, &cmd, 1, (u8 *) &result, 2); | |
594 | ||
595 | /* return negative errno or unsigned value */ | |
596 | return (status < 0) ? status : result; | |
597 | } | |
598 | ||
599 | /*---------------------------------------------------------------------------*/ | |
600 | ||
601 | /* | |
602 | * INTERFACE between board init code and SPI infrastructure. | |
603 | * | |
604 | * No SPI driver ever sees these SPI device table segments, but | |
605 | * it's how the SPI core (or adapters that get hotplugged) grows | |
606 | * the driver model tree. | |
607 | * | |
608 | * As a rule, SPI devices can't be probed. Instead, board init code | |
609 | * provides a table listing the devices which are present, with enough | |
610 | * information to bind and set up the device's driver. There's basic | |
611 | * support for nonstatic configurations too; enough to handle adding | |
612 | * parport adapters, or microcontrollers acting as USB-to-SPI bridges. | |
613 | */ | |
614 | ||
615 | /* board-specific information about each SPI device */ | |
616 | struct spi_board_info { | |
617 | /* the device name and module name are coupled, like platform_bus; | |
618 | * "modalias" is normally the driver name. | |
619 | * | |
620 | * platform_data goes to spi_device.dev.platform_data, | |
b885244e | 621 | * controller_data goes to spi_device.controller_data, |
8ae12a0d DB |
622 | * irq is copied too |
623 | */ | |
624 | char modalias[KOBJ_NAME_LEN]; | |
625 | const void *platform_data; | |
b885244e | 626 | void *controller_data; |
8ae12a0d DB |
627 | int irq; |
628 | ||
629 | /* slower signaling on noisy or low voltage boards */ | |
630 | u32 max_speed_hz; | |
631 | ||
632 | ||
633 | /* bus_num is board specific and matches the bus_num of some | |
634 | * spi_master that will probably be registered later. | |
635 | * | |
636 | * chip_select reflects how this chip is wired to that master; | |
637 | * it's less than num_chipselect. | |
638 | */ | |
639 | u16 bus_num; | |
640 | u16 chip_select; | |
641 | ||
642 | /* ... may need additional spi_device chip config data here. | |
643 | * avoid stuff protocol drivers can set; but include stuff | |
644 | * needed to behave without being bound to a driver: | |
645 | * - chipselect polarity | |
646 | * - quirks like clock rate mattering when not selected | |
647 | */ | |
648 | }; | |
649 | ||
650 | #ifdef CONFIG_SPI | |
651 | extern int | |
652 | spi_register_board_info(struct spi_board_info const *info, unsigned n); | |
653 | #else | |
654 | /* board init code may ignore whether SPI is configured or not */ | |
655 | static inline int | |
656 | spi_register_board_info(struct spi_board_info const *info, unsigned n) | |
657 | { return 0; } | |
658 | #endif | |
659 | ||
660 | ||
661 | /* If you're hotplugging an adapter with devices (parport, usb, etc) | |
0c868461 DB |
662 | * use spi_new_device() to describe each device. You can also call |
663 | * spi_unregister_device() to start making that device vanish, but | |
664 | * normally that would be handled by spi_unregister_master(). | |
8ae12a0d DB |
665 | */ |
666 | extern struct spi_device * | |
667 | spi_new_device(struct spi_master *, struct spi_board_info *); | |
668 | ||
669 | static inline void | |
670 | spi_unregister_device(struct spi_device *spi) | |
671 | { | |
672 | if (spi) | |
673 | device_unregister(&spi->dev); | |
674 | } | |
675 | ||
676 | #endif /* __LINUX_SPI_H */ |