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61e115a5 MB |
1 | #ifndef LINUX_SSB_H_ |
2 | #define LINUX_SSB_H_ | |
3 | ||
4 | #include <linux/device.h> | |
5 | #include <linux/list.h> | |
6 | #include <linux/types.h> | |
7 | #include <linux/spinlock.h> | |
8 | #include <linux/pci.h> | |
ec43b08b | 9 | #include <linux/gpio.h> |
61e115a5 | 10 | #include <linux/mod_devicetable.h> |
9c0c7a42 | 11 | #include <linux/dma-mapping.h> |
bde327ef | 12 | #include <linux/platform_device.h> |
61e115a5 MB |
13 | |
14 | #include <linux/ssb/ssb_regs.h> | |
15 | ||
16 | ||
17 | struct pcmcia_device; | |
18 | struct ssb_bus; | |
19 | struct ssb_driver; | |
20 | ||
b0f70292 RM |
21 | struct ssb_sprom_core_pwr_info { |
22 | u8 itssi_2g, itssi_5g; | |
23 | u8 maxpwr_2g, maxpwr_5gl, maxpwr_5g, maxpwr_5gh; | |
3b64e6f9 | 24 | u16 pa_2g[4], pa_5gl[4], pa_5g[4], pa_5gh[4]; |
b0f70292 RM |
25 | }; |
26 | ||
61e115a5 MB |
27 | struct ssb_sprom { |
28 | u8 revision; | |
85249828 HM |
29 | u8 il0mac[6] __aligned(sizeof(u16)); /* MAC address for 802.11b/g */ |
30 | u8 et0mac[6] __aligned(sizeof(u16)); /* MAC address for Ethernet */ | |
31 | u8 et1mac[6] __aligned(sizeof(u16)); /* MAC address for 802.11a */ | |
6e122ac0 | 32 | u8 et2mac[6] __aligned(sizeof(u16)); /* MAC address for extra Ethernet */ |
ac82fab4 LF |
33 | u8 et0phyaddr; /* MII address for enet0 */ |
34 | u8 et1phyaddr; /* MII address for enet1 */ | |
6e122ac0 | 35 | u8 et2phyaddr; /* MII address for enet2 */ |
e861b98d MB |
36 | u8 et0mdcport; /* MDIO for enet0 */ |
37 | u8 et1mdcport; /* MDIO for enet1 */ | |
6e122ac0 | 38 | u8 et2mdcport; /* MDIO for enet2 */ |
4f4aa2ec | 39 | u16 dev_id; /* Device ID overriding e.g. PCI ID */ |
e2d646ce | 40 | u16 board_rev; /* Board revision number from SPROM. */ |
52aa63f5 HM |
41 | u16 board_num; /* Board number from SPROM. */ |
42 | u16 board_type; /* Board type from SPROM. */ | |
ac82fab4 | 43 | u8 country_code; /* Country Code */ |
03a5642b | 44 | char alpha2[2]; /* Country Code as two chars like EU or US */ |
edd8d90b HM |
45 | u8 leddc_on_time; /* LED Powersave Duty Cycle On Count */ |
46 | u8 leddc_off_time; /* LED Powersave Duty Cycle Off Count */ | |
f679056b GS |
47 | u8 ant_available_a; /* 2GHz antenna available bits (up to 4) */ |
48 | u8 ant_available_bg; /* 5GHz antenna available bits (up to 4) */ | |
ac82fab4 LF |
49 | u16 pa0b0; |
50 | u16 pa0b1; | |
51 | u16 pa0b2; | |
52 | u16 pa1b0; | |
53 | u16 pa1b1; | |
54 | u16 pa1b2; | |
f679056b GS |
55 | u16 pa1lob0; |
56 | u16 pa1lob1; | |
57 | u16 pa1lob2; | |
58 | u16 pa1hib0; | |
59 | u16 pa1hib1; | |
60 | u16 pa1hib2; | |
ac82fab4 LF |
61 | u8 gpio0; /* GPIO pin 0 */ |
62 | u8 gpio1; /* GPIO pin 1 */ | |
63 | u8 gpio2; /* GPIO pin 2 */ | |
64 | u8 gpio3; /* GPIO pin 3 */ | |
edd8d90b HM |
65 | u8 maxpwr_bg; /* 2.4GHz Amplifier Max Power (in dBm Q5.2) */ |
66 | u8 maxpwr_al; /* 5.2GHz Amplifier Max Power (in dBm Q5.2) */ | |
67 | u8 maxpwr_a; /* 5.3GHz Amplifier Max Power (in dBm Q5.2) */ | |
68 | u8 maxpwr_ah; /* 5.8GHz Amplifier Max Power (in dBm Q5.2) */ | |
ac82fab4 LF |
69 | u8 itssi_a; /* Idle TSSI Target for A-PHY */ |
70 | u8 itssi_bg; /* Idle TSSI Target for B/G-PHY */ | |
f679056b GS |
71 | u8 tri2g; /* 2.4GHz TX isolation */ |
72 | u8 tri5gl; /* 5.2GHz TX isolation */ | |
73 | u8 tri5g; /* 5.3GHz TX isolation */ | |
74 | u8 tri5gh; /* 5.8GHz TX isolation */ | |
172c69a4 RM |
75 | u8 txpid2g[4]; /* 2GHz TX power index */ |
76 | u8 txpid5gl[4]; /* 4.9 - 5.1GHz TX power index */ | |
77 | u8 txpid5g[4]; /* 5.1 - 5.5GHz TX power index */ | |
78 | u8 txpid5gh[4]; /* 5.5 - ...GHz TX power index */ | |
edd8d90b HM |
79 | s8 rxpo2g; /* 2GHz RX power offset */ |
80 | s8 rxpo5g; /* 5GHz RX power offset */ | |
f679056b GS |
81 | u8 rssisav2g; /* 2GHz RSSI params */ |
82 | u8 rssismc2g; | |
83 | u8 rssismf2g; | |
84 | u8 bxa2g; /* 2GHz BX arch */ | |
85 | u8 rssisav5g; /* 5GHz RSSI params */ | |
86 | u8 rssismc5g; | |
87 | u8 rssismf5g; | |
88 | u8 bxa5g; /* 5GHz BX arch */ | |
89 | u16 cck2gpo; /* CCK power offset */ | |
90 | u32 ofdm2gpo; /* 2.4GHz OFDM power offset */ | |
91 | u32 ofdm5glpo; /* 5.2GHz OFDM power offset */ | |
92 | u32 ofdm5gpo; /* 5.3GHz OFDM power offset */ | |
93 | u32 ofdm5ghpo; /* 5.8GHz OFDM power offset */ | |
1387fe7d RM |
94 | u32 boardflags; |
95 | u32 boardflags2; | |
96 | u32 boardflags3; | |
97 | /* TODO: Switch all drivers to new u32 fields and drop below ones */ | |
f679056b GS |
98 | u16 boardflags_lo; /* Board flags (bits 0-15) */ |
99 | u16 boardflags_hi; /* Board flags (bits 16-31) */ | |
100 | u16 boardflags2_lo; /* Board flags (bits 32-47) */ | |
101 | u16 boardflags2_hi; /* Board flags (bits 48-63) */ | |
e861b98d | 102 | |
b0f70292 RM |
103 | struct ssb_sprom_core_pwr_info core_pwr_info[4]; |
104 | ||
e861b98d MB |
105 | /* Antenna gain values for up to 4 antennas |
106 | * on each band. Values in dBm/4 (Q5.2). Negative gain means the | |
107 | * loss in the connectors is bigger than the gain. */ | |
108 | struct { | |
f8f8a660 | 109 | s8 a0, a1, a2, a3; |
e861b98d | 110 | } antenna_gain; |
ac82fab4 | 111 | |
8a5ac6ec RM |
112 | struct { |
113 | struct { | |
114 | u8 tssipos, extpa_gain, pdet_range, tr_iso, antswlut; | |
115 | } ghz2; | |
116 | struct { | |
117 | u8 tssipos, extpa_gain, pdet_range, tr_iso, antswlut; | |
118 | } ghz5; | |
119 | } fem; | |
120 | ||
52aa63f5 HM |
121 | u16 mcs2gpo[8]; |
122 | u16 mcs5gpo[8]; | |
123 | u16 mcs5glpo[8]; | |
124 | u16 mcs5ghpo[8]; | |
125 | u8 opo; | |
126 | ||
127 | u8 rxgainerr2ga[3]; | |
128 | u8 rxgainerr5gla[3]; | |
129 | u8 rxgainerr5gma[3]; | |
130 | u8 rxgainerr5gha[3]; | |
131 | u8 rxgainerr5gua[3]; | |
132 | ||
133 | u8 noiselvl2ga[3]; | |
134 | u8 noiselvl5gla[3]; | |
135 | u8 noiselvl5gma[3]; | |
136 | u8 noiselvl5gha[3]; | |
137 | u8 noiselvl5gua[3]; | |
138 | ||
139 | u8 regrev; | |
140 | u8 txchain; | |
141 | u8 rxchain; | |
142 | u8 antswitch; | |
143 | u16 cddpo; | |
144 | u16 stbcpo; | |
145 | u16 bw40po; | |
146 | u16 bwduppo; | |
147 | ||
148 | u8 tempthresh; | |
149 | u8 tempoffset; | |
150 | u16 rawtempsense; | |
151 | u8 measpower; | |
152 | u8 tempsense_slope; | |
153 | u8 tempcorrx; | |
154 | u8 tempsense_option; | |
155 | u8 freqoffset_corr; | |
156 | u8 iqcal_swp_dis; | |
157 | u8 hw_iqcal_en; | |
158 | u8 elna2g; | |
159 | u8 elna5g; | |
160 | u8 phycal_tempdelta; | |
161 | u8 temps_period; | |
162 | u8 temps_hysteresis; | |
163 | u8 measpower1; | |
164 | u8 measpower2; | |
165 | u8 pcieingress_war; | |
166 | ||
167 | /* power per rate from sromrev 9 */ | |
168 | u16 cckbw202gpo; | |
169 | u16 cckbw20ul2gpo; | |
170 | u32 legofdmbw202gpo; | |
171 | u32 legofdmbw20ul2gpo; | |
172 | u32 legofdmbw205glpo; | |
173 | u32 legofdmbw20ul5glpo; | |
174 | u32 legofdmbw205gmpo; | |
175 | u32 legofdmbw20ul5gmpo; | |
176 | u32 legofdmbw205ghpo; | |
177 | u32 legofdmbw20ul5ghpo; | |
178 | u32 mcsbw202gpo; | |
179 | u32 mcsbw20ul2gpo; | |
180 | u32 mcsbw402gpo; | |
181 | u32 mcsbw205glpo; | |
182 | u32 mcsbw20ul5glpo; | |
183 | u32 mcsbw405glpo; | |
184 | u32 mcsbw205gmpo; | |
185 | u32 mcsbw20ul5gmpo; | |
186 | u32 mcsbw405gmpo; | |
187 | u32 mcsbw205ghpo; | |
188 | u32 mcsbw20ul5ghpo; | |
189 | u32 mcsbw405ghpo; | |
190 | u16 mcs32po; | |
191 | u16 legofdm40duppo; | |
192 | u8 sar2g; | |
193 | u8 sar5g; | |
61e115a5 MB |
194 | }; |
195 | ||
196 | /* Information about the PCB the circuitry is soldered on. */ | |
197 | struct ssb_boardinfo { | |
198 | u16 vendor; | |
199 | u16 type; | |
61e115a5 MB |
200 | }; |
201 | ||
202 | ||
203 | struct ssb_device; | |
204 | /* Lowlevel read/write operations on the device MMIO. | |
205 | * Internal, don't use that outside of ssb. */ | |
206 | struct ssb_bus_ops { | |
ffc7689d | 207 | u8 (*read8)(struct ssb_device *dev, u16 offset); |
61e115a5 MB |
208 | u16 (*read16)(struct ssb_device *dev, u16 offset); |
209 | u32 (*read32)(struct ssb_device *dev, u16 offset); | |
ffc7689d | 210 | void (*write8)(struct ssb_device *dev, u16 offset, u8 value); |
61e115a5 MB |
211 | void (*write16)(struct ssb_device *dev, u16 offset, u16 value); |
212 | void (*write32)(struct ssb_device *dev, u16 offset, u32 value); | |
d625a29b MB |
213 | #ifdef CONFIG_SSB_BLOCKIO |
214 | void (*block_read)(struct ssb_device *dev, void *buffer, | |
215 | size_t count, u16 offset, u8 reg_width); | |
216 | void (*block_write)(struct ssb_device *dev, const void *buffer, | |
217 | size_t count, u16 offset, u8 reg_width); | |
218 | #endif | |
61e115a5 MB |
219 | }; |
220 | ||
221 | ||
222 | /* Core-ID values. */ | |
223 | #define SSB_DEV_CHIPCOMMON 0x800 | |
224 | #define SSB_DEV_ILINE20 0x801 | |
225 | #define SSB_DEV_SDRAM 0x803 | |
226 | #define SSB_DEV_PCI 0x804 | |
227 | #define SSB_DEV_MIPS 0x805 | |
228 | #define SSB_DEV_ETHERNET 0x806 | |
229 | #define SSB_DEV_V90 0x807 | |
230 | #define SSB_DEV_USB11_HOSTDEV 0x808 | |
231 | #define SSB_DEV_ADSL 0x809 | |
232 | #define SSB_DEV_ILINE100 0x80A | |
233 | #define SSB_DEV_IPSEC 0x80B | |
234 | #define SSB_DEV_PCMCIA 0x80D | |
235 | #define SSB_DEV_INTERNAL_MEM 0x80E | |
236 | #define SSB_DEV_MEMC_SDRAM 0x80F | |
237 | #define SSB_DEV_EXTIF 0x811 | |
238 | #define SSB_DEV_80211 0x812 | |
239 | #define SSB_DEV_MIPS_3302 0x816 | |
240 | #define SSB_DEV_USB11_HOST 0x817 | |
241 | #define SSB_DEV_USB11_DEV 0x818 | |
242 | #define SSB_DEV_USB20_HOST 0x819 | |
243 | #define SSB_DEV_USB20_DEV 0x81A | |
244 | #define SSB_DEV_SDIO_HOST 0x81B | |
245 | #define SSB_DEV_ROBOSWITCH 0x81C | |
246 | #define SSB_DEV_PARA_ATA 0x81D | |
247 | #define SSB_DEV_SATA_XORDMA 0x81E | |
248 | #define SSB_DEV_ETHERNET_GBIT 0x81F | |
249 | #define SSB_DEV_PCIE 0x820 | |
250 | #define SSB_DEV_MIMO_PHY 0x821 | |
251 | #define SSB_DEV_SRAM_CTRLR 0x822 | |
252 | #define SSB_DEV_MINI_MACPHY 0x823 | |
253 | #define SSB_DEV_ARM_1176 0x824 | |
254 | #define SSB_DEV_ARM_7TDMI 0x825 | |
ccaf8c32 | 255 | #define SSB_DEV_ARM_CM3 0x82A |
61e115a5 MB |
256 | |
257 | /* Vendor-ID values */ | |
258 | #define SSB_VENDOR_BROADCOM 0x4243 | |
259 | ||
260 | /* Some kernel subsystems poke with dev->drvdata, so we must use the | |
261 | * following ugly workaround to get from struct device to struct ssb_device */ | |
262 | struct __ssb_dev_wrapper { | |
263 | struct device dev; | |
264 | struct ssb_device *sdev; | |
265 | }; | |
266 | ||
267 | struct ssb_device { | |
268 | /* Having a copy of the ops pointer in each dev struct | |
269 | * is an optimization. */ | |
270 | const struct ssb_bus_ops *ops; | |
271 | ||
14f92952 | 272 | struct device *dev, *dma_dev; |
4ac58469 | 273 | |
61e115a5 MB |
274 | struct ssb_bus *bus; |
275 | struct ssb_device_id id; | |
276 | ||
277 | u8 core_index; | |
278 | unsigned int irq; | |
279 | ||
280 | /* Internal-only stuff follows. */ | |
281 | void *drvdata; /* Per-device data */ | |
282 | void *devtypedata; /* Per-devicetype (eg 802.11) data */ | |
283 | }; | |
284 | ||
285 | /* Go from struct device to struct ssb_device. */ | |
286 | static inline | |
287 | struct ssb_device * dev_to_ssb_dev(struct device *dev) | |
288 | { | |
289 | struct __ssb_dev_wrapper *wrap; | |
290 | wrap = container_of(dev, struct __ssb_dev_wrapper, dev); | |
291 | return wrap->sdev; | |
292 | } | |
293 | ||
294 | /* Device specific user data */ | |
295 | static inline | |
296 | void ssb_set_drvdata(struct ssb_device *dev, void *data) | |
297 | { | |
298 | dev->drvdata = data; | |
299 | } | |
300 | static inline | |
301 | void * ssb_get_drvdata(struct ssb_device *dev) | |
302 | { | |
303 | return dev->drvdata; | |
304 | } | |
305 | ||
306 | /* Devicetype specific user data. This is per device-type (not per device) */ | |
307 | void ssb_set_devtypedata(struct ssb_device *dev, void *data); | |
308 | static inline | |
309 | void * ssb_get_devtypedata(struct ssb_device *dev) | |
310 | { | |
311 | return dev->devtypedata; | |
312 | } | |
313 | ||
314 | ||
315 | struct ssb_driver { | |
316 | const char *name; | |
317 | const struct ssb_device_id *id_table; | |
318 | ||
319 | int (*probe)(struct ssb_device *dev, const struct ssb_device_id *id); | |
320 | void (*remove)(struct ssb_device *dev); | |
321 | int (*suspend)(struct ssb_device *dev, pm_message_t state); | |
322 | int (*resume)(struct ssb_device *dev); | |
323 | void (*shutdown)(struct ssb_device *dev); | |
324 | ||
325 | struct device_driver drv; | |
326 | }; | |
327 | #define drv_to_ssb_drv(_drv) container_of(_drv, struct ssb_driver, drv) | |
328 | ||
329 | extern int __ssb_driver_register(struct ssb_driver *drv, struct module *owner); | |
eb5589a8 PG |
330 | #define ssb_driver_register(drv) \ |
331 | __ssb_driver_register(drv, THIS_MODULE) | |
332 | ||
61e115a5 MB |
333 | extern void ssb_driver_unregister(struct ssb_driver *drv); |
334 | ||
335 | ||
336 | ||
337 | ||
338 | enum ssb_bustype { | |
339 | SSB_BUSTYPE_SSB, /* This SSB bus is the system bus */ | |
340 | SSB_BUSTYPE_PCI, /* SSB is connected to PCI bus */ | |
341 | SSB_BUSTYPE_PCMCIA, /* SSB is connected to PCMCIA bus */ | |
24ea602e | 342 | SSB_BUSTYPE_SDIO, /* SSB is connected to SDIO bus */ |
61e115a5 MB |
343 | }; |
344 | ||
345 | /* board_vendor */ | |
346 | #define SSB_BOARDVENDOR_BCM 0x14E4 /* Broadcom */ | |
347 | #define SSB_BOARDVENDOR_DELL 0x1028 /* Dell */ | |
348 | #define SSB_BOARDVENDOR_HP 0x0E11 /* HP */ | |
349 | /* board_type */ | |
c5116e9d RM |
350 | #define SSB_BOARD_BCM94301CB 0x0406 |
351 | #define SSB_BOARD_BCM94301MP 0x0407 | |
352 | #define SSB_BOARD_BU4309 0x040A | |
353 | #define SSB_BOARD_BCM94309CB 0x040B | |
354 | #define SSB_BOARD_BCM4309MP 0x040C | |
355 | #define SSB_BOARD_BU4306 0x0416 | |
61e115a5 MB |
356 | #define SSB_BOARD_BCM94306MP 0x0418 |
357 | #define SSB_BOARD_BCM4309G 0x0421 | |
358 | #define SSB_BOARD_BCM4306CB 0x0417 | |
c5116e9d RM |
359 | #define SSB_BOARD_BCM94306PC 0x0425 /* pcmcia 3.3v 4306 card */ |
360 | #define SSB_BOARD_BCM94306CBSG 0x042B /* with SiGe PA */ | |
361 | #define SSB_BOARD_PCSG94306 0x042D /* with SiGe PA */ | |
362 | #define SSB_BOARD_BU4704SD 0x042E /* with sdram */ | |
363 | #define SSB_BOARD_BCM94704AGR 0x042F /* dual 11a/11g Router */ | |
364 | #define SSB_BOARD_BCM94308MP 0x0430 /* 11a-only minipci */ | |
365 | #define SSB_BOARD_BU4318 0x0447 | |
366 | #define SSB_BOARD_CB4318 0x0448 | |
367 | #define SSB_BOARD_MPG4318 0x0449 | |
61e115a5 | 368 | #define SSB_BOARD_MP4318 0x044A |
c5116e9d RM |
369 | #define SSB_BOARD_SD4318 0x044B |
370 | #define SSB_BOARD_BCM94306P 0x044C /* with SiGe */ | |
371 | #define SSB_BOARD_BCM94303MP 0x044E | |
372 | #define SSB_BOARD_BCM94306MPM 0x0450 | |
373 | #define SSB_BOARD_BCM94306MPL 0x0453 | |
374 | #define SSB_BOARD_PC4303 0x0454 /* pcmcia */ | |
375 | #define SSB_BOARD_BCM94306MPLNA 0x0457 | |
376 | #define SSB_BOARD_BCM94306MPH 0x045B | |
377 | #define SSB_BOARD_BCM94306PCIV 0x045C | |
378 | #define SSB_BOARD_BCM94318MPGH 0x0463 | |
379 | #define SSB_BOARD_BU4311 0x0464 | |
380 | #define SSB_BOARD_BCM94311MC 0x0465 | |
381 | #define SSB_BOARD_BCM94311MCAG 0x0466 | |
382 | /* 4321 boards */ | |
383 | #define SSB_BOARD_BU4321 0x046B | |
384 | #define SSB_BOARD_BU4321E 0x047C | |
385 | #define SSB_BOARD_MP4321 0x046C | |
386 | #define SSB_BOARD_CB2_4321 0x046D | |
387 | #define SSB_BOARD_CB2_4321_AG 0x0066 | |
388 | #define SSB_BOARD_MC4321 0x046E | |
389 | /* 4325 boards */ | |
390 | #define SSB_BOARD_BCM94325DEVBU 0x0490 | |
391 | #define SSB_BOARD_BCM94325BGABU 0x0491 | |
392 | #define SSB_BOARD_BCM94325SDGWB 0x0492 | |
393 | #define SSB_BOARD_BCM94325SDGMDL 0x04AA | |
394 | #define SSB_BOARD_BCM94325SDGMDL2 0x04C6 | |
395 | #define SSB_BOARD_BCM94325SDGMDL3 0x04C9 | |
396 | #define SSB_BOARD_BCM94325SDABGWBA 0x04E1 | |
397 | /* 4322 boards */ | |
398 | #define SSB_BOARD_BCM94322MC 0x04A4 | |
399 | #define SSB_BOARD_BCM94322USB 0x04A8 /* dualband */ | |
400 | #define SSB_BOARD_BCM94322HM 0x04B0 | |
401 | #define SSB_BOARD_BCM94322USB2D 0x04Bf /* single band discrete front end */ | |
402 | /* 4312 boards */ | |
403 | #define SSB_BOARD_BU4312 0x048A | |
404 | #define SSB_BOARD_BCM4312MCGSG 0x04B5 | |
61e115a5 MB |
405 | /* chip_package */ |
406 | #define SSB_CHIPPACK_BCM4712S 1 /* Small 200pin 4712 */ | |
407 | #define SSB_CHIPPACK_BCM4712M 2 /* Medium 225pin 4712 */ | |
408 | #define SSB_CHIPPACK_BCM4712L 0 /* Large 340pin 4712 */ | |
409 | ||
410 | #include <linux/ssb/ssb_driver_chipcommon.h> | |
411 | #include <linux/ssb/ssb_driver_mips.h> | |
412 | #include <linux/ssb/ssb_driver_extif.h> | |
413 | #include <linux/ssb/ssb_driver_pci.h> | |
414 | ||
415 | struct ssb_bus { | |
416 | /* The MMIO area. */ | |
417 | void __iomem *mmio; | |
418 | ||
419 | const struct ssb_bus_ops *ops; | |
420 | ||
8b45499c MB |
421 | /* The core currently mapped into the MMIO window. |
422 | * Not valid on all host-buses. So don't use outside of SSB. */ | |
61e115a5 | 423 | struct ssb_device *mapped_device; |
24ea602e AH |
424 | union { |
425 | /* Currently mapped PCMCIA segment. (bustype == SSB_BUSTYPE_PCMCIA only) */ | |
426 | u8 mapped_pcmcia_seg; | |
427 | /* Current SSB base address window for SDIO. */ | |
428 | u32 sdio_sbaddr; | |
429 | }; | |
993e1c78 MB |
430 | /* Lock for core and segment switching. |
431 | * On PCMCIA-host busses this is used to protect the whole MMIO access. */ | |
61e115a5 MB |
432 | spinlock_t bar_lock; |
433 | ||
8b45499c | 434 | /* The host-bus this backplane is running on. */ |
61e115a5 | 435 | enum ssb_bustype bustype; |
8b45499c MB |
436 | /* Pointers to the host-bus. Check bustype before using any of these pointers. */ |
437 | union { | |
438 | /* Pointer to the PCI bus (only valid if bustype == SSB_BUSTYPE_PCI). */ | |
439 | struct pci_dev *host_pci; | |
440 | /* Pointer to the PCMCIA device (only if bustype == SSB_BUSTYPE_PCMCIA). */ | |
441 | struct pcmcia_device *host_pcmcia; | |
442 | /* Pointer to the SDIO device (only if bustype == SSB_BUSTYPE_SDIO). */ | |
443 | struct sdio_func *host_sdio; | |
444 | }; | |
24ea602e AH |
445 | |
446 | /* See enum ssb_quirks */ | |
447 | unsigned int quirks; | |
61e115a5 | 448 | |
e7ec2e32 | 449 | #ifdef CONFIG_SSB_SPROM |
61e115a5 | 450 | /* Mutex to protect the SPROM writing. */ |
e7ec2e32 | 451 | struct mutex sprom_mutex; |
61e115a5 MB |
452 | #endif |
453 | ||
454 | /* ID information about the Chip. */ | |
455 | u16 chip_id; | |
ce57d9e6 | 456 | u8 chip_rev; |
ea2db495 | 457 | u16 sprom_offset; |
c272ef44 | 458 | u16 sprom_size; /* number of words in sprom */ |
61e115a5 MB |
459 | u8 chip_package; |
460 | ||
461 | /* List of devices (cores) on the backplane. */ | |
462 | struct ssb_device devices[SSB_MAX_NR_CORES]; | |
463 | u8 nr_devices; | |
464 | ||
61e115a5 MB |
465 | /* Software ID number for this bus. */ |
466 | unsigned int busnumber; | |
467 | ||
468 | /* The ChipCommon device (if available). */ | |
469 | struct ssb_chipcommon chipco; | |
470 | /* The PCI-core device (if available). */ | |
471 | struct ssb_pcicore pcicore; | |
472 | /* The MIPS-core device (if available). */ | |
473 | struct ssb_mipscore mipscore; | |
474 | /* The EXTif-core device (if available). */ | |
475 | struct ssb_extif extif; | |
476 | ||
477 | /* The following structure elements are not available in early | |
478 | * SSB initialization. Though, they are available for regular | |
479 | * registered drivers at any stage. So be careful when | |
480 | * using them in the ssb core code. */ | |
481 | ||
482 | /* ID information about the PCB. */ | |
483 | struct ssb_boardinfo boardinfo; | |
484 | /* Contents of the SPROM. */ | |
485 | struct ssb_sprom sprom; | |
7cb44615 MB |
486 | /* If the board has a cardbus slot, this is set to true. */ |
487 | bool has_cardbus_slot; | |
61e115a5 | 488 | |
53521d8c MB |
489 | #ifdef CONFIG_SSB_EMBEDDED |
490 | /* Lock for GPIO register access. */ | |
491 | spinlock_t gpio_lock; | |
bde327ef | 492 | struct platform_device *watchdog; |
53521d8c | 493 | #endif /* EMBEDDED */ |
ec43b08b HM |
494 | #ifdef CONFIG_SSB_DRIVER_GPIO |
495 | struct gpio_chip gpio; | |
7c1bc0da | 496 | struct irq_domain *irq_domain; |
ec43b08b | 497 | #endif /* DRIVER_GPIO */ |
53521d8c | 498 | |
61e115a5 MB |
499 | /* Internal-only stuff follows. Do not touch. */ |
500 | struct list_head list; | |
501 | #ifdef CONFIG_SSB_DEBUG | |
502 | /* Is the bus already powered up? */ | |
503 | bool powered_up; | |
504 | int power_warn_count; | |
505 | #endif /* DEBUG */ | |
506 | }; | |
507 | ||
24ea602e AH |
508 | enum ssb_quirks { |
509 | /* SDIO connected card requires performing a read after writing a 32-bit value */ | |
510 | SSB_QUIRK_SDIO_READ_AFTER_WRITE32 = (1 << 0), | |
511 | }; | |
512 | ||
61e115a5 MB |
513 | /* The initialization-invariants. */ |
514 | struct ssb_init_invariants { | |
7cb44615 | 515 | /* Versioning information about the PCB. */ |
61e115a5 | 516 | struct ssb_boardinfo boardinfo; |
7cb44615 MB |
517 | /* The SPROM information. That's either stored in an |
518 | * EEPROM or NVRAM on the board. */ | |
61e115a5 | 519 | struct ssb_sprom sprom; |
7cb44615 MB |
520 | /* If the board has a cardbus slot, this is set to true. */ |
521 | bool has_cardbus_slot; | |
61e115a5 MB |
522 | }; |
523 | /* Type of function to fetch the invariants. */ | |
524 | typedef int (*ssb_invariants_func_t)(struct ssb_bus *bus, | |
525 | struct ssb_init_invariants *iv); | |
526 | ||
541c9a84 RM |
527 | /* Register SoC bus. */ |
528 | extern int ssb_bus_host_soc_register(struct ssb_bus *bus, | |
529 | unsigned long baseaddr); | |
61e115a5 MB |
530 | #ifdef CONFIG_SSB_PCIHOST |
531 | extern int ssb_bus_pcibus_register(struct ssb_bus *bus, | |
532 | struct pci_dev *host_pci); | |
533 | #endif /* CONFIG_SSB_PCIHOST */ | |
534 | #ifdef CONFIG_SSB_PCMCIAHOST | |
535 | extern int ssb_bus_pcmciabus_register(struct ssb_bus *bus, | |
536 | struct pcmcia_device *pcmcia_dev, | |
537 | unsigned long baseaddr); | |
538 | #endif /* CONFIG_SSB_PCMCIAHOST */ | |
24ea602e AH |
539 | #ifdef CONFIG_SSB_SDIOHOST |
540 | extern int ssb_bus_sdiobus_register(struct ssb_bus *bus, | |
541 | struct sdio_func *sdio_func, | |
542 | unsigned int quirks); | |
543 | #endif /* CONFIG_SSB_SDIOHOST */ | |
544 | ||
61e115a5 MB |
545 | |
546 | extern void ssb_bus_unregister(struct ssb_bus *bus); | |
547 | ||
d53cdbb9 JL |
548 | /* Does the device have an SPROM? */ |
549 | extern bool ssb_is_sprom_available(struct ssb_bus *bus); | |
550 | ||
e79c1ba8 MB |
551 | /* Set a fallback SPROM. |
552 | * See kdoc at the function definition for complete documentation. */ | |
b3ae52b6 HM |
553 | extern int ssb_arch_register_fallback_sprom( |
554 | int (*sprom_callback)(struct ssb_bus *bus, | |
555 | struct ssb_sprom *out)); | |
e79c1ba8 | 556 | |
8fe2b65a MB |
557 | /* Suspend a SSB bus. |
558 | * Call this from the parent bus suspend routine. */ | |
559 | extern int ssb_bus_suspend(struct ssb_bus *bus); | |
560 | /* Resume a SSB bus. | |
561 | * Call this from the parent bus resume routine. */ | |
562 | extern int ssb_bus_resume(struct ssb_bus *bus); | |
563 | ||
61e115a5 MB |
564 | extern u32 ssb_clockspeed(struct ssb_bus *bus); |
565 | ||
566 | /* Is the device enabled in hardware? */ | |
567 | int ssb_device_is_enabled(struct ssb_device *dev); | |
568 | /* Enable a device and pass device-specific SSB_TMSLOW flags. | |
569 | * If no device-specific flags are available, use 0. */ | |
570 | void ssb_device_enable(struct ssb_device *dev, u32 core_specific_flags); | |
571 | /* Disable a device in hardware and pass SSB_TMSLOW flags (if any). */ | |
572 | void ssb_device_disable(struct ssb_device *dev, u32 core_specific_flags); | |
573 | ||
574 | ||
575 | /* Device MMIO register read/write functions. */ | |
ffc7689d MB |
576 | static inline u8 ssb_read8(struct ssb_device *dev, u16 offset) |
577 | { | |
578 | return dev->ops->read8(dev, offset); | |
579 | } | |
61e115a5 MB |
580 | static inline u16 ssb_read16(struct ssb_device *dev, u16 offset) |
581 | { | |
582 | return dev->ops->read16(dev, offset); | |
583 | } | |
584 | static inline u32 ssb_read32(struct ssb_device *dev, u16 offset) | |
585 | { | |
586 | return dev->ops->read32(dev, offset); | |
587 | } | |
ffc7689d MB |
588 | static inline void ssb_write8(struct ssb_device *dev, u16 offset, u8 value) |
589 | { | |
590 | dev->ops->write8(dev, offset, value); | |
591 | } | |
61e115a5 MB |
592 | static inline void ssb_write16(struct ssb_device *dev, u16 offset, u16 value) |
593 | { | |
594 | dev->ops->write16(dev, offset, value); | |
595 | } | |
596 | static inline void ssb_write32(struct ssb_device *dev, u16 offset, u32 value) | |
597 | { | |
598 | dev->ops->write32(dev, offset, value); | |
599 | } | |
d625a29b MB |
600 | #ifdef CONFIG_SSB_BLOCKIO |
601 | static inline void ssb_block_read(struct ssb_device *dev, void *buffer, | |
602 | size_t count, u16 offset, u8 reg_width) | |
603 | { | |
604 | dev->ops->block_read(dev, buffer, count, offset, reg_width); | |
605 | } | |
606 | ||
607 | static inline void ssb_block_write(struct ssb_device *dev, const void *buffer, | |
608 | size_t count, u16 offset, u8 reg_width) | |
609 | { | |
610 | dev->ops->block_write(dev, buffer, count, offset, reg_width); | |
611 | } | |
612 | #endif /* CONFIG_SSB_BLOCKIO */ | |
61e115a5 MB |
613 | |
614 | ||
f225763a MB |
615 | /* The SSB DMA API. Use this API for any DMA operation on the device. |
616 | * This API basically is a wrapper that calls the correct DMA API for | |
617 | * the host device type the SSB device is attached to. */ | |
618 | ||
61e115a5 MB |
619 | /* Translation (routing) bits that need to be ORed to DMA |
620 | * addresses before they are given to a device. */ | |
621 | extern u32 ssb_dma_translation(struct ssb_device *dev); | |
622 | #define SSB_DMA_TRANSLATION_MASK 0xC0000000 | |
623 | #define SSB_DMA_TRANSLATION_SHIFT 30 | |
624 | ||
f225763a MB |
625 | static inline void __cold __ssb_dma_not_implemented(struct ssb_device *dev) |
626 | { | |
627 | #ifdef CONFIG_SSB_DEBUG | |
628 | printk(KERN_ERR "SSB: BUG! Calling DMA API for " | |
629 | "unsupported bustype %d\n", dev->bus->bustype); | |
630 | #endif /* DEBUG */ | |
631 | } | |
632 | ||
61e115a5 MB |
633 | #ifdef CONFIG_SSB_PCIHOST |
634 | /* PCI-host wrapper driver */ | |
635 | extern int ssb_pcihost_register(struct pci_driver *driver); | |
636 | static inline void ssb_pcihost_unregister(struct pci_driver *driver) | |
637 | { | |
638 | pci_unregister_driver(driver); | |
639 | } | |
961d57c8 MB |
640 | |
641 | static inline | |
642 | void ssb_pcihost_set_power_state(struct ssb_device *sdev, pci_power_t state) | |
643 | { | |
644 | if (sdev->bus->bustype == SSB_BUSTYPE_PCI) | |
645 | pci_set_power_state(sdev->bus->host_pci, state); | |
646 | } | |
532031d7 AM |
647 | #else |
648 | static inline void ssb_pcihost_unregister(struct pci_driver *driver) | |
649 | { | |
650 | } | |
651 | ||
652 | static inline | |
653 | void ssb_pcihost_set_power_state(struct ssb_device *sdev, pci_power_t state) | |
654 | { | |
655 | } | |
61e115a5 MB |
656 | #endif /* CONFIG_SSB_PCIHOST */ |
657 | ||
658 | ||
659 | /* If a driver is shutdown or suspended, call this to signal | |
660 | * that the bus may be completely powered down. SSB will decide, | |
661 | * if it's really time to power down the bus, based on if there | |
662 | * are other devices that want to run. */ | |
663 | extern int ssb_bus_may_powerdown(struct ssb_bus *bus); | |
664 | /* Before initializing and enabling a device, call this to power-up the bus. | |
665 | * If you want to allow use of dynamic-power-control, pass the flag. | |
666 | * Otherwise static always-on powercontrol will be used. */ | |
667 | extern int ssb_bus_powerup(struct ssb_bus *bus, bool dynamic_pctl); | |
668 | ||
8576f815 | 669 | extern void ssb_commit_settings(struct ssb_bus *bus); |
61e115a5 MB |
670 | |
671 | /* Various helper functions */ | |
672 | extern u32 ssb_admatch_base(u32 adm); | |
673 | extern u32 ssb_admatch_size(u32 adm); | |
674 | ||
aab547ce MB |
675 | /* PCI device mapping and fixup routines. |
676 | * Called from the architecture pcibios init code. | |
677 | * These are only available on SSB_EMBEDDED configurations. */ | |
678 | #ifdef CONFIG_SSB_EMBEDDED | |
679 | int ssb_pcibios_plat_dev_init(struct pci_dev *dev); | |
680 | int ssb_pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin); | |
681 | #endif /* CONFIG_SSB_EMBEDDED */ | |
61e115a5 MB |
682 | |
683 | #endif /* LINUX_SSB_H_ */ |