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61e115a5 MB |
1 | #ifndef LINUX_SSB_CHIPCO_H_ |
2 | #define LINUX_SSB_CHIPCO_H_ | |
3 | ||
4 | /* SonicsSiliconBackplane CHIPCOMMON core hardware definitions | |
5 | * | |
6 | * The chipcommon core provides chip identification, SB control, | |
7 | * jtag, 0/1/2 uarts, clock frequency control, a watchdog interrupt timer, | |
8 | * gpio interface, extbus, and support for serial and parallel flashes. | |
9 | * | |
10 | * Copyright 2005, Broadcom Corporation | |
11 | * Copyright 2006, Michael Buesch <mb@bu3sch.de> | |
12 | * | |
13 | * Licensed under the GPL version 2. See COPYING for details. | |
14 | */ | |
15 | ||
16 | /** ChipCommon core registers. **/ | |
17 | ||
18 | #define SSB_CHIPCO_CHIPID 0x0000 | |
19 | #define SSB_CHIPCO_IDMASK 0x0000FFFF | |
20 | #define SSB_CHIPCO_REVMASK 0x000F0000 | |
21 | #define SSB_CHIPCO_REVSHIFT 16 | |
22 | #define SSB_CHIPCO_PACKMASK 0x00F00000 | |
23 | #define SSB_CHIPCO_PACKSHIFT 20 | |
24 | #define SSB_CHIPCO_NRCORESMASK 0x0F000000 | |
25 | #define SSB_CHIPCO_NRCORESSHIFT 24 | |
26 | #define SSB_CHIPCO_CAP 0x0004 /* Capabilities */ | |
27 | #define SSB_CHIPCO_CAP_NRUART 0x00000003 /* # of UARTs */ | |
28 | #define SSB_CHIPCO_CAP_MIPSEB 0x00000004 /* MIPS in BigEndian Mode */ | |
29 | #define SSB_CHIPCO_CAP_UARTCLK 0x00000018 /* UART clock select */ | |
30 | #define SSB_CHIPCO_CAP_UARTCLK_INT 0x00000008 /* UARTs are driven by internal divided clock */ | |
31 | #define SSB_CHIPCO_CAP_UARTGPIO 0x00000020 /* UARTs on GPIO 15-12 */ | |
32 | #define SSB_CHIPCO_CAP_EXTBUS 0x000000C0 /* External buses present */ | |
33 | #define SSB_CHIPCO_CAP_FLASHT 0x00000700 /* Flash Type */ | |
34 | #define SSB_CHIPCO_FLASHT_NONE 0x00000000 /* No flash */ | |
35 | #define SSB_CHIPCO_FLASHT_STSER 0x00000100 /* ST serial flash */ | |
36 | #define SSB_CHIPCO_FLASHT_ATSER 0x00000200 /* Atmel serial flash */ | |
37 | #define SSB_CHIPCO_FLASHT_PARA 0x00000700 /* Parallel flash */ | |
38 | #define SSB_CHIPCO_CAP_PLLT 0x00038000 /* PLL Type */ | |
39 | #define SSB_PLLTYPE_NONE 0x00000000 | |
40 | #define SSB_PLLTYPE_1 0x00010000 /* 48Mhz base, 3 dividers */ | |
41 | #define SSB_PLLTYPE_2 0x00020000 /* 48Mhz, 4 dividers */ | |
42 | #define SSB_PLLTYPE_3 0x00030000 /* 25Mhz, 2 dividers */ | |
43 | #define SSB_PLLTYPE_4 0x00008000 /* 48Mhz, 4 dividers */ | |
44 | #define SSB_PLLTYPE_5 0x00018000 /* 25Mhz, 4 dividers */ | |
45 | #define SSB_PLLTYPE_6 0x00028000 /* 100/200 or 120/240 only */ | |
46 | #define SSB_PLLTYPE_7 0x00038000 /* 25Mhz, 4 dividers */ | |
47 | #define SSB_CHIPCO_CAP_PCTL 0x00040000 /* Power Control */ | |
48 | #define SSB_CHIPCO_CAP_OTPS 0x00380000 /* OTP size */ | |
49 | #define SSB_CHIPCO_CAP_OTPS_SHIFT 19 | |
50 | #define SSB_CHIPCO_CAP_OTPS_BASE 5 | |
51 | #define SSB_CHIPCO_CAP_JTAGM 0x00400000 /* JTAG master present */ | |
52 | #define SSB_CHIPCO_CAP_BROM 0x00800000 /* Internal boot ROM active */ | |
53 | #define SSB_CHIPCO_CAP_64BIT 0x08000000 /* 64-bit Backplane */ | |
58ff70d4 MB |
54 | #define SSB_CHIPCO_CAP_PMU 0x10000000 /* PMU available (rev >= 20) */ |
55 | #define SSB_CHIPCO_CAP_ECI 0x20000000 /* ECI available (rev >= 20) */ | |
61e115a5 MB |
56 | #define SSB_CHIPCO_CORECTL 0x0008 |
57 | #define SSB_CHIPCO_CORECTL_UARTCLK0 0x00000001 /* Drive UART with internal clock */ | |
58 | #define SSB_CHIPCO_CORECTL_SE 0x00000002 /* sync clk out enable (corerev >= 3) */ | |
58ff70d4 | 59 | #define SSB_CHIPCO_CORECTL_UARTCLKEN 0x00000008 /* UART clock enable (rev >= 21) */ |
61e115a5 MB |
60 | #define SSB_CHIPCO_BIST 0x000C |
61 | #define SSB_CHIPCO_OTPS 0x0010 /* OTP status */ | |
62 | #define SSB_CHIPCO_OTPS_PROGFAIL 0x80000000 | |
63 | #define SSB_CHIPCO_OTPS_PROTECT 0x00000007 | |
64 | #define SSB_CHIPCO_OTPS_HW_PROTECT 0x00000001 | |
65 | #define SSB_CHIPCO_OTPS_SW_PROTECT 0x00000002 | |
66 | #define SSB_CHIPCO_OTPS_CID_PROTECT 0x00000004 | |
67 | #define SSB_CHIPCO_OTPC 0x0014 /* OTP control */ | |
68 | #define SSB_CHIPCO_OTPC_RECWAIT 0xFF000000 | |
69 | #define SSB_CHIPCO_OTPC_PROGWAIT 0x00FFFF00 | |
70 | #define SSB_CHIPCO_OTPC_PRW_SHIFT 8 | |
71 | #define SSB_CHIPCO_OTPC_MAXFAIL 0x00000038 | |
72 | #define SSB_CHIPCO_OTPC_VSEL 0x00000006 | |
73 | #define SSB_CHIPCO_OTPC_SELVL 0x00000001 | |
74 | #define SSB_CHIPCO_OTPP 0x0018 /* OTP prog */ | |
75 | #define SSB_CHIPCO_OTPP_COL 0x000000FF | |
76 | #define SSB_CHIPCO_OTPP_ROW 0x0000FF00 | |
77 | #define SSB_CHIPCO_OTPP_ROW_SHIFT 8 | |
78 | #define SSB_CHIPCO_OTPP_READERR 0x10000000 | |
79 | #define SSB_CHIPCO_OTPP_VALUE 0x20000000 | |
80 | #define SSB_CHIPCO_OTPP_READ 0x40000000 | |
81 | #define SSB_CHIPCO_OTPP_START 0x80000000 | |
82 | #define SSB_CHIPCO_OTPP_BUSY 0x80000000 | |
83 | #define SSB_CHIPCO_IRQSTAT 0x0020 | |
84 | #define SSB_CHIPCO_IRQMASK 0x0024 | |
85 | #define SSB_CHIPCO_IRQ_GPIO 0x00000001 /* gpio intr */ | |
86 | #define SSB_CHIPCO_IRQ_EXT 0x00000002 /* ro: ext intr pin (corerev >= 3) */ | |
87 | #define SSB_CHIPCO_IRQ_WDRESET 0x80000000 /* watchdog reset occurred */ | |
88 | #define SSB_CHIPCO_CHIPCTL 0x0028 /* Rev >= 11 only */ | |
89 | #define SSB_CHIPCO_CHIPSTAT 0x002C /* Rev >= 11 only */ | |
90 | #define SSB_CHIPCO_JCMD 0x0030 /* Rev >= 10 only */ | |
91 | #define SSB_CHIPCO_JCMD_START 0x80000000 | |
92 | #define SSB_CHIPCO_JCMD_BUSY 0x80000000 | |
93 | #define SSB_CHIPCO_JCMD_PAUSE 0x40000000 | |
94 | #define SSB_CHIPCO_JCMD0_ACC_MASK 0x0000F000 | |
95 | #define SSB_CHIPCO_JCMD0_ACC_IRDR 0x00000000 | |
96 | #define SSB_CHIPCO_JCMD0_ACC_DR 0x00001000 | |
97 | #define SSB_CHIPCO_JCMD0_ACC_IR 0x00002000 | |
98 | #define SSB_CHIPCO_JCMD0_ACC_RESET 0x00003000 | |
99 | #define SSB_CHIPCO_JCMD0_ACC_IRPDR 0x00004000 | |
100 | #define SSB_CHIPCO_JCMD0_ACC_PDR 0x00005000 | |
101 | #define SSB_CHIPCO_JCMD0_IRW_MASK 0x00000F00 | |
102 | #define SSB_CHIPCO_JCMD_ACC_MASK 0x000F0000 /* Changes for corerev 11 */ | |
103 | #define SSB_CHIPCO_JCMD_ACC_IRDR 0x00000000 | |
104 | #define SSB_CHIPCO_JCMD_ACC_DR 0x00010000 | |
105 | #define SSB_CHIPCO_JCMD_ACC_IR 0x00020000 | |
106 | #define SSB_CHIPCO_JCMD_ACC_RESET 0x00030000 | |
107 | #define SSB_CHIPCO_JCMD_ACC_IRPDR 0x00040000 | |
108 | #define SSB_CHIPCO_JCMD_ACC_PDR 0x00050000 | |
109 | #define SSB_CHIPCO_JCMD_IRW_MASK 0x00001F00 | |
110 | #define SSB_CHIPCO_JCMD_IRW_SHIFT 8 | |
111 | #define SSB_CHIPCO_JCMD_DRW_MASK 0x0000003F | |
112 | #define SSB_CHIPCO_JIR 0x0034 /* Rev >= 10 only */ | |
113 | #define SSB_CHIPCO_JDR 0x0038 /* Rev >= 10 only */ | |
114 | #define SSB_CHIPCO_JCTL 0x003C /* Rev >= 10 only */ | |
115 | #define SSB_CHIPCO_JCTL_FORCE_CLK 4 /* Force clock */ | |
116 | #define SSB_CHIPCO_JCTL_EXT_EN 2 /* Enable external targets */ | |
117 | #define SSB_CHIPCO_JCTL_EN 1 /* Enable Jtag master */ | |
118 | #define SSB_CHIPCO_FLASHCTL 0x0040 | |
119 | #define SSB_CHIPCO_FLASHCTL_START 0x80000000 | |
120 | #define SSB_CHIPCO_FLASHCTL_BUSY SSB_CHIPCO_FLASHCTL_START | |
121 | #define SSB_CHIPCO_FLASHADDR 0x0044 | |
122 | #define SSB_CHIPCO_FLASHDATA 0x0048 | |
123 | #define SSB_CHIPCO_BCAST_ADDR 0x0050 | |
124 | #define SSB_CHIPCO_BCAST_DATA 0x0054 | |
125 | #define SSB_CHIPCO_GPIOIN 0x0060 | |
126 | #define SSB_CHIPCO_GPIOOUT 0x0064 | |
127 | #define SSB_CHIPCO_GPIOOUTEN 0x0068 | |
128 | #define SSB_CHIPCO_GPIOCTL 0x006C | |
129 | #define SSB_CHIPCO_GPIOPOL 0x0070 | |
130 | #define SSB_CHIPCO_GPIOIRQ 0x0074 | |
131 | #define SSB_CHIPCO_WATCHDOG 0x0080 | |
132 | #define SSB_CHIPCO_GPIOTIMER 0x0088 /* LED powersave (corerev >= 16) */ | |
133 | #define SSB_CHIPCO_GPIOTIMER_ONTIME_SHIFT 16 | |
134 | #define SSB_CHIPCO_GPIOTOUTM 0x008C /* LED powersave (corerev >= 16) */ | |
135 | #define SSB_CHIPCO_CLOCK_N 0x0090 | |
136 | #define SSB_CHIPCO_CLOCK_SB 0x0094 | |
137 | #define SSB_CHIPCO_CLOCK_PCI 0x0098 | |
138 | #define SSB_CHIPCO_CLOCK_M2 0x009C | |
139 | #define SSB_CHIPCO_CLOCK_MIPS 0x00A0 | |
140 | #define SSB_CHIPCO_CLKDIV 0x00A4 /* Rev >= 3 only */ | |
141 | #define SSB_CHIPCO_CLKDIV_SFLASH 0x0F000000 | |
142 | #define SSB_CHIPCO_CLKDIV_SFLASH_SHIFT 24 | |
143 | #define SSB_CHIPCO_CLKDIV_OTP 0x000F0000 | |
144 | #define SSB_CHIPCO_CLKDIV_OTP_SHIFT 16 | |
145 | #define SSB_CHIPCO_CLKDIV_JTAG 0x00000F00 | |
146 | #define SSB_CHIPCO_CLKDIV_JTAG_SHIFT 8 | |
147 | #define SSB_CHIPCO_CLKDIV_UART 0x000000FF | |
148 | #define SSB_CHIPCO_PLLONDELAY 0x00B0 /* Rev >= 4 only */ | |
149 | #define SSB_CHIPCO_FREFSELDELAY 0x00B4 /* Rev >= 4 only */ | |
150 | #define SSB_CHIPCO_SLOWCLKCTL 0x00B8 /* 6 <= Rev <= 9 only */ | |
151 | #define SSB_CHIPCO_SLOWCLKCTL_SRC 0x00000007 /* slow clock source mask */ | |
152 | #define SSB_CHIPCO_SLOWCLKCTL_SRC_LPO 0x00000000 /* source of slow clock is LPO */ | |
153 | #define SSB_CHIPCO_SLOWCLKCTL_SRC_XTAL 0x00000001 /* source of slow clock is crystal */ | |
154 | #define SSB_CHIPCO_SLOECLKCTL_SRC_PCI 0x00000002 /* source of slow clock is PCI */ | |
155 | #define SSB_CHIPCO_SLOWCLKCTL_LPOFREQ 0x00000200 /* LPOFreqSel, 1: 160Khz, 0: 32KHz */ | |
156 | #define SSB_CHIPCO_SLOWCLKCTL_LPOPD 0x00000400 /* LPOPowerDown, 1: LPO is disabled, 0: LPO is enabled */ | |
157 | #define SSB_CHIPCO_SLOWCLKCTL_FSLOW 0x00000800 /* ForceSlowClk, 1: sb/cores running on slow clock, 0: power logic control */ | |
158 | #define SSB_CHIPCO_SLOWCLKCTL_IPLL 0x00001000 /* IgnorePllOffReq, 1/0: power logic ignores/honors PLL clock disable requests from core */ | |
159 | #define SSB_CHIPCO_SLOWCLKCTL_ENXTAL 0x00002000 /* XtalControlEn, 1/0: power logic does/doesn't disable crystal when appropriate */ | |
160 | #define SSB_CHIPCO_SLOWCLKCTL_XTALPU 0x00004000 /* XtalPU (RO), 1/0: crystal running/disabled */ | |
161 | #define SSB_CHIPCO_SLOWCLKCTL_CLKDIV 0xFFFF0000 /* ClockDivider (SlowClk = 1/(4+divisor)) */ | |
162 | #define SSB_CHIPCO_SLOWCLKCTL_CLKDIV_SHIFT 16 | |
163 | #define SSB_CHIPCO_SYSCLKCTL 0x00C0 /* Rev >= 3 only */ | |
164 | #define SSB_CHIPCO_SYSCLKCTL_IDLPEN 0x00000001 /* ILPen: Enable Idle Low Power */ | |
165 | #define SSB_CHIPCO_SYSCLKCTL_ALPEN 0x00000002 /* ALPen: Enable Active Low Power */ | |
166 | #define SSB_CHIPCO_SYSCLKCTL_PLLEN 0x00000004 /* ForcePLLOn */ | |
167 | #define SSB_CHIPCO_SYSCLKCTL_FORCEALP 0x00000008 /* Force ALP (or HT if ALPen is not set */ | |
168 | #define SSB_CHIPCO_SYSCLKCTL_FORCEHT 0x00000010 /* Force HT */ | |
169 | #define SSB_CHIPCO_SYSCLKCTL_CLKDIV 0xFFFF0000 /* ClkDiv (ILP = 1/(4+divisor)) */ | |
170 | #define SSB_CHIPCO_SYSCLKCTL_CLKDIV_SHIFT 16 | |
171 | #define SSB_CHIPCO_CLKSTSTR 0x00C4 /* Rev >= 3 only */ | |
172 | #define SSB_CHIPCO_PCMCIA_CFG 0x0100 | |
173 | #define SSB_CHIPCO_PCMCIA_MEMWAIT 0x0104 | |
174 | #define SSB_CHIPCO_PCMCIA_ATTRWAIT 0x0108 | |
175 | #define SSB_CHIPCO_PCMCIA_IOWAIT 0x010C | |
176 | #define SSB_CHIPCO_IDE_CFG 0x0110 | |
177 | #define SSB_CHIPCO_IDE_MEMWAIT 0x0114 | |
178 | #define SSB_CHIPCO_IDE_ATTRWAIT 0x0118 | |
179 | #define SSB_CHIPCO_IDE_IOWAIT 0x011C | |
180 | #define SSB_CHIPCO_PROG_CFG 0x0120 | |
181 | #define SSB_CHIPCO_PROG_WAITCNT 0x0124 | |
182 | #define SSB_CHIPCO_FLASH_CFG 0x0128 | |
183 | #define SSB_CHIPCO_FLASH_WAITCNT 0x012C | |
c9703146 MB |
184 | #define SSB_CHIPCO_CLKCTLST 0x01E0 /* Clock control and status (rev >= 20) */ |
185 | #define SSB_CHIPCO_CLKCTLST_FORCEALP 0x00000001 /* Force ALP request */ | |
186 | #define SSB_CHIPCO_CLKCTLST_FORCEHT 0x00000002 /* Force HT request */ | |
187 | #define SSB_CHIPCO_CLKCTLST_FORCEILP 0x00000004 /* Force ILP request */ | |
188 | #define SSB_CHIPCO_CLKCTLST_HAVEALPREQ 0x00000008 /* ALP available request */ | |
189 | #define SSB_CHIPCO_CLKCTLST_HAVEHTREQ 0x00000010 /* HT available request */ | |
190 | #define SSB_CHIPCO_CLKCTLST_HWCROFF 0x00000020 /* Force HW clock request off */ | |
191 | #define SSB_CHIPCO_CLKCTLST_HAVEHT 0x00010000 /* HT available */ | |
192 | #define SSB_CHIPCO_CLKCTLST_HAVEALP 0x00020000 /* APL available */ | |
193 | #define SSB_CHIPCO_HW_WORKAROUND 0x01E4 /* Hardware workaround (rev >= 20) */ | |
61e115a5 MB |
194 | #define SSB_CHIPCO_UART0_DATA 0x0300 |
195 | #define SSB_CHIPCO_UART0_IMR 0x0304 | |
196 | #define SSB_CHIPCO_UART0_FCR 0x0308 | |
197 | #define SSB_CHIPCO_UART0_LCR 0x030C | |
198 | #define SSB_CHIPCO_UART0_MCR 0x0310 | |
199 | #define SSB_CHIPCO_UART0_LSR 0x0314 | |
200 | #define SSB_CHIPCO_UART0_MSR 0x0318 | |
201 | #define SSB_CHIPCO_UART0_SCRATCH 0x031C | |
202 | #define SSB_CHIPCO_UART1_DATA 0x0400 | |
203 | #define SSB_CHIPCO_UART1_IMR 0x0404 | |
204 | #define SSB_CHIPCO_UART1_FCR 0x0408 | |
205 | #define SSB_CHIPCO_UART1_LCR 0x040C | |
206 | #define SSB_CHIPCO_UART1_MCR 0x0410 | |
207 | #define SSB_CHIPCO_UART1_LSR 0x0414 | |
208 | #define SSB_CHIPCO_UART1_MSR 0x0418 | |
209 | #define SSB_CHIPCO_UART1_SCRATCH 0x041C | |
c9703146 MB |
210 | /* PMU registers (rev >= 20) */ |
211 | #define SSB_CHIPCO_PMU_CTL 0x0600 /* PMU control */ | |
212 | #define SSB_CHIPCO_PMU_CTL_ILP_DIV 0xFFFF0000 /* ILP div mask */ | |
213 | #define SSB_CHIPCO_PMU_CTL_ILP_DIV_SHIFT 16 | |
214 | #define SSB_CHIPCO_PMU_CTL_NOILPONW 0x00000200 /* No ILP on wait */ | |
215 | #define SSB_CHIPCO_PMU_CTL_HTREQEN 0x00000100 /* HT req enable */ | |
216 | #define SSB_CHIPCO_PMU_CTL_ALPREQEN 0x00000080 /* ALP req enable */ | |
217 | #define SSB_CHIPCO_PMU_CTL_XTALFREQ 0x0000007C /* Crystal freq */ | |
218 | #define SSB_CHIPCO_PMU_CTL_XTALFREQ_SHIFT 2 | |
219 | #define SSB_CHIPCO_PMU_CTL_ILPDIVEN 0x00000002 /* ILP div enable */ | |
220 | #define SSB_CHIPCO_PMU_CTL_LPOSEL 0x00000001 /* LPO sel */ | |
221 | #define SSB_CHIPCO_PMU_CAP 0x0604 /* PMU capabilities */ | |
222 | #define SSB_CHIPCO_PMU_CAP_REVISION 0x000000FF /* Revision mask */ | |
223 | #define SSB_CHIPCO_PMU_STAT 0x0608 /* PMU status */ | |
224 | #define SSB_CHIPCO_PMU_STAT_INTPEND 0x00000040 /* Interrupt pending */ | |
225 | #define SSB_CHIPCO_PMU_STAT_SBCLKST 0x00000030 /* Backplane clock status? */ | |
226 | #define SSB_CHIPCO_PMU_STAT_HAVEALP 0x00000008 /* ALP available */ | |
227 | #define SSB_CHIPCO_PMU_STAT_HAVEHT 0x00000004 /* HT available */ | |
228 | #define SSB_CHIPCO_PMU_STAT_RESINIT 0x00000003 /* Res init */ | |
229 | #define SSB_CHIPCO_PMU_RES_STAT 0x060C /* PMU res status */ | |
230 | #define SSB_CHIPCO_PMU_RES_PEND 0x0610 /* PMU res pending */ | |
231 | #define SSB_CHIPCO_PMU_TIMER 0x0614 /* PMU timer */ | |
232 | #define SSB_CHIPCO_PMU_MINRES_MSK 0x0618 /* PMU min res mask */ | |
233 | #define SSB_CHIPCO_PMU_MAXRES_MSK 0x061C /* PMU max res mask */ | |
234 | #define SSB_CHIPCO_PMU_RES_TABSEL 0x0620 /* PMU res table sel */ | |
235 | #define SSB_CHIPCO_PMU_RES_DEPMSK 0x0624 /* PMU res dep mask */ | |
236 | #define SSB_CHIPCO_PMU_RES_UPDNTM 0x0628 /* PMU res updown timer */ | |
237 | #define SSB_CHIPCO_PMU_RES_TIMER 0x062C /* PMU res timer */ | |
238 | #define SSB_CHIPCO_PMU_CLKSTRETCH 0x0630 /* PMU clockstretch */ | |
239 | #define SSB_CHIPCO_PMU_WATCHDOG 0x0634 /* PMU watchdog */ | |
240 | #define SSB_CHIPCO_PMU_RES_REQTS 0x0640 /* PMU res req timer sel */ | |
241 | #define SSB_CHIPCO_PMU_RES_REQT 0x0644 /* PMU res req timer */ | |
242 | #define SSB_CHIPCO_PMU_RES_REQM 0x0648 /* PMU res req mask */ | |
243 | #define SSB_CHIPCO_CHIPCTL_ADDR 0x0650 | |
244 | #define SSB_CHIPCO_CHIPCTL_DATA 0x0654 | |
245 | #define SSB_CHIPCO_REGCTL_ADDR 0x0658 | |
246 | #define SSB_CHIPCO_REGCTL_DATA 0x065C | |
247 | #define SSB_CHIPCO_PLLCTL_ADDR 0x0660 | |
248 | #define SSB_CHIPCO_PLLCTL_DATA 0x0664 | |
249 | ||
250 | ||
251 | ||
252 | /** PMU PLL registers */ | |
253 | ||
254 | /* PMU rev 0 PLL registers */ | |
255 | #define SSB_PMU0_PLLCTL0 0 | |
256 | #define SSB_PMU0_PLLCTL0_PDIV_MSK 0x00000001 | |
257 | #define SSB_PMU0_PLLCTL0_PDIV_FREQ 25000 /* kHz */ | |
258 | #define SSB_PMU0_PLLCTL1 1 | |
259 | #define SSB_PMU0_PLLCTL1_WILD_IMSK 0xF0000000 /* Wild int mask (low nibble) */ | |
260 | #define SSB_PMU0_PLLCTL1_WILD_IMSK_SHIFT 28 | |
261 | #define SSB_PMU0_PLLCTL1_WILD_FMSK 0x0FFFFF00 /* Wild frac mask */ | |
262 | #define SSB_PMU0_PLLCTL1_WILD_FMSK_SHIFT 8 | |
263 | #define SSB_PMU0_PLLCTL1_STOPMOD 0x00000040 /* Stop mod */ | |
264 | #define SSB_PMU0_PLLCTL2 2 | |
265 | #define SSB_PMU0_PLLCTL2_WILD_IMSKHI 0x0000000F /* Wild int mask (high nibble) */ | |
266 | #define SSB_PMU0_PLLCTL2_WILD_IMSKHI_SHIFT 0 | |
267 | ||
268 | /* PMU rev 1 PLL registers */ | |
269 | #define SSB_PMU1_PLLCTL0 0 | |
270 | #define SSB_PMU1_PLLCTL0_P1DIV 0x00F00000 /* P1 div */ | |
271 | #define SSB_PMU1_PLLCTL0_P1DIV_SHIFT 20 | |
272 | #define SSB_PMU1_PLLCTL0_P2DIV 0x0F000000 /* P2 div */ | |
273 | #define SSB_PMU1_PLLCTL0_P2DIV_SHIFT 24 | |
274 | #define SSB_PMU1_PLLCTL1 1 | |
275 | #define SSB_PMU1_PLLCTL1_M1DIV 0x000000FF /* M1 div */ | |
276 | #define SSB_PMU1_PLLCTL1_M1DIV_SHIFT 0 | |
277 | #define SSB_PMU1_PLLCTL1_M2DIV 0x0000FF00 /* M2 div */ | |
278 | #define SSB_PMU1_PLLCTL1_M2DIV_SHIFT 8 | |
279 | #define SSB_PMU1_PLLCTL1_M3DIV 0x00FF0000 /* M3 div */ | |
280 | #define SSB_PMU1_PLLCTL1_M3DIV_SHIFT 16 | |
281 | #define SSB_PMU1_PLLCTL1_M4DIV 0xFF000000 /* M4 div */ | |
282 | #define SSB_PMU1_PLLCTL1_M4DIV_SHIFT 24 | |
283 | #define SSB_PMU1_PLLCTL2 2 | |
284 | #define SSB_PMU1_PLLCTL2_M5DIV 0x000000FF /* M5 div */ | |
285 | #define SSB_PMU1_PLLCTL2_M5DIV_SHIFT 0 | |
286 | #define SSB_PMU1_PLLCTL2_M6DIV 0x0000FF00 /* M6 div */ | |
287 | #define SSB_PMU1_PLLCTL2_M6DIV_SHIFT 8 | |
288 | #define SSB_PMU1_PLLCTL2_NDIVMODE 0x000E0000 /* NDIV mode */ | |
289 | #define SSB_PMU1_PLLCTL2_NDIVMODE_SHIFT 17 | |
290 | #define SSB_PMU1_PLLCTL2_NDIVINT 0x1FF00000 /* NDIV int */ | |
291 | #define SSB_PMU1_PLLCTL2_NDIVINT_SHIFT 20 | |
292 | #define SSB_PMU1_PLLCTL3 3 | |
293 | #define SSB_PMU1_PLLCTL3_NDIVFRAC 0x00FFFFFF /* NDIV frac */ | |
294 | #define SSB_PMU1_PLLCTL3_NDIVFRAC_SHIFT 0 | |
295 | #define SSB_PMU1_PLLCTL4 4 | |
296 | #define SSB_PMU1_PLLCTL5 5 | |
297 | #define SSB_PMU1_PLLCTL5_CLKDRV 0xFFFFFF00 /* clk drv */ | |
298 | #define SSB_PMU1_PLLCTL5_CLKDRV_SHIFT 8 | |
299 | ||
300 | /* BCM4312 PLL resource numbers. */ | |
301 | #define SSB_PMURES_4312_SWITCHER_BURST 0 | |
302 | #define SSB_PMURES_4312_SWITCHER_PWM 1 | |
303 | #define SSB_PMURES_4312_PA_REF_LDO 2 | |
304 | #define SSB_PMURES_4312_CORE_LDO_BURST 3 | |
305 | #define SSB_PMURES_4312_CORE_LDO_PWM 4 | |
306 | #define SSB_PMURES_4312_RADIO_LDO 5 | |
307 | #define SSB_PMURES_4312_ILP_REQUEST 6 | |
308 | #define SSB_PMURES_4312_BG_FILTBYP 7 | |
309 | #define SSB_PMURES_4312_TX_FILTBYP 8 | |
310 | #define SSB_PMURES_4312_RX_FILTBYP 9 | |
311 | #define SSB_PMURES_4312_XTAL_PU 10 | |
312 | #define SSB_PMURES_4312_ALP_AVAIL 11 | |
313 | #define SSB_PMURES_4312_BB_PLL_FILTBYP 12 | |
314 | #define SSB_PMURES_4312_RF_PLL_FILTBYP 13 | |
315 | #define SSB_PMURES_4312_HT_AVAIL 14 | |
316 | ||
317 | /* BCM4325 PLL resource numbers. */ | |
318 | #define SSB_PMURES_4325_BUCK_BOOST_BURST 0 | |
319 | #define SSB_PMURES_4325_CBUCK_BURST 1 | |
320 | #define SSB_PMURES_4325_CBUCK_PWM 2 | |
321 | #define SSB_PMURES_4325_CLDO_CBUCK_BURST 3 | |
322 | #define SSB_PMURES_4325_CLDO_CBUCK_PWM 4 | |
323 | #define SSB_PMURES_4325_BUCK_BOOST_PWM 5 | |
324 | #define SSB_PMURES_4325_ILP_REQUEST 6 | |
325 | #define SSB_PMURES_4325_ABUCK_BURST 7 | |
326 | #define SSB_PMURES_4325_ABUCK_PWM 8 | |
327 | #define SSB_PMURES_4325_LNLDO1_PU 9 | |
328 | #define SSB_PMURES_4325_LNLDO2_PU 10 | |
329 | #define SSB_PMURES_4325_LNLDO3_PU 11 | |
330 | #define SSB_PMURES_4325_LNLDO4_PU 12 | |
331 | #define SSB_PMURES_4325_XTAL_PU 13 | |
332 | #define SSB_PMURES_4325_ALP_AVAIL 14 | |
333 | #define SSB_PMURES_4325_RX_PWRSW_PU 15 | |
334 | #define SSB_PMURES_4325_TX_PWRSW_PU 16 | |
335 | #define SSB_PMURES_4325_RFPLL_PWRSW_PU 17 | |
336 | #define SSB_PMURES_4325_LOGEN_PWRSW_PU 18 | |
337 | #define SSB_PMURES_4325_AFE_PWRSW_PU 19 | |
338 | #define SSB_PMURES_4325_BBPLL_PWRSW_PU 20 | |
339 | #define SSB_PMURES_4325_HT_AVAIL 21 | |
340 | ||
341 | /* BCM4328 PLL resource numbers. */ | |
342 | #define SSB_PMURES_4328_EXT_SWITCHER_PWM 0 | |
343 | #define SSB_PMURES_4328_BB_SWITCHER_PWM 1 | |
344 | #define SSB_PMURES_4328_BB_SWITCHER_BURST 2 | |
345 | #define SSB_PMURES_4328_BB_EXT_SWITCHER_BURST 3 | |
346 | #define SSB_PMURES_4328_ILP_REQUEST 4 | |
347 | #define SSB_PMURES_4328_RADIO_SWITCHER_PWM 5 | |
348 | #define SSB_PMURES_4328_RADIO_SWITCHER_BURST 6 | |
349 | #define SSB_PMURES_4328_ROM_SWITCH 7 | |
350 | #define SSB_PMURES_4328_PA_REF_LDO 8 | |
351 | #define SSB_PMURES_4328_RADIO_LDO 9 | |
352 | #define SSB_PMURES_4328_AFE_LDO 10 | |
353 | #define SSB_PMURES_4328_PLL_LDO 11 | |
354 | #define SSB_PMURES_4328_BG_FILTBYP 12 | |
355 | #define SSB_PMURES_4328_TX_FILTBYP 13 | |
356 | #define SSB_PMURES_4328_RX_FILTBYP 14 | |
357 | #define SSB_PMURES_4328_XTAL_PU 15 | |
358 | #define SSB_PMURES_4328_XTAL_EN 16 | |
359 | #define SSB_PMURES_4328_BB_PLL_FILTBYP 17 | |
360 | #define SSB_PMURES_4328_RF_PLL_FILTBYP 18 | |
361 | #define SSB_PMURES_4328_BB_PLL_PU 19 | |
362 | ||
363 | /* BCM5354 PLL resource numbers. */ | |
364 | #define SSB_PMURES_5354_EXT_SWITCHER_PWM 0 | |
365 | #define SSB_PMURES_5354_BB_SWITCHER_PWM 1 | |
366 | #define SSB_PMURES_5354_BB_SWITCHER_BURST 2 | |
367 | #define SSB_PMURES_5354_BB_EXT_SWITCHER_BURST 3 | |
368 | #define SSB_PMURES_5354_ILP_REQUEST 4 | |
369 | #define SSB_PMURES_5354_RADIO_SWITCHER_PWM 5 | |
370 | #define SSB_PMURES_5354_RADIO_SWITCHER_BURST 6 | |
371 | #define SSB_PMURES_5354_ROM_SWITCH 7 | |
372 | #define SSB_PMURES_5354_PA_REF_LDO 8 | |
373 | #define SSB_PMURES_5354_RADIO_LDO 9 | |
374 | #define SSB_PMURES_5354_AFE_LDO 10 | |
375 | #define SSB_PMURES_5354_PLL_LDO 11 | |
376 | #define SSB_PMURES_5354_BG_FILTBYP 12 | |
377 | #define SSB_PMURES_5354_TX_FILTBYP 13 | |
378 | #define SSB_PMURES_5354_RX_FILTBYP 14 | |
379 | #define SSB_PMURES_5354_XTAL_PU 15 | |
380 | #define SSB_PMURES_5354_XTAL_EN 16 | |
381 | #define SSB_PMURES_5354_BB_PLL_FILTBYP 17 | |
382 | #define SSB_PMURES_5354_RF_PLL_FILTBYP 18 | |
383 | #define SSB_PMURES_5354_BB_PLL_PU 19 | |
384 | ||
385 | ||
386 | ||
387 | /** Chip specific Chip-Status register contents. */ | |
388 | #define SSB_CHIPCO_CHST_4325_SPROM_OTP_SEL 0x00000003 | |
389 | #define SSB_CHIPCO_CHST_4325_DEFCIS_SEL 0 /* OTP is powered up, use def. CIS, no SPROM */ | |
390 | #define SSB_CHIPCO_CHST_4325_SPROM_SEL 1 /* OTP is powered up, SPROM is present */ | |
391 | #define SSB_CHIPCO_CHST_4325_OTP_SEL 2 /* OTP is powered up, no SPROM */ | |
392 | #define SSB_CHIPCO_CHST_4325_OTP_PWRDN 3 /* OTP is powered down, SPROM is present */ | |
393 | #define SSB_CHIPCO_CHST_4325_SDIO_USB_MODE 0x00000004 | |
394 | #define SSB_CHIPCO_CHST_4325_SDIO_USB_MODE_SHIFT 2 | |
395 | #define SSB_CHIPCO_CHST_4325_RCAL_VALID 0x00000008 | |
396 | #define SSB_CHIPCO_CHST_4325_RCAL_VALID_SHIFT 3 | |
397 | #define SSB_CHIPCO_CHST_4325_RCAL_VALUE 0x000001F0 | |
398 | #define SSB_CHIPCO_CHST_4325_RCAL_VALUE_SHIFT 4 | |
399 | #define SSB_CHIPCO_CHST_4325_PMUTOP_2B 0x00000200 /* 1 for 2b, 0 for to 2a */ | |
61e115a5 MB |
400 | |
401 | ||
402 | ||
403 | /** Clockcontrol masks and values **/ | |
404 | ||
405 | /* SSB_CHIPCO_CLOCK_N */ | |
406 | #define SSB_CHIPCO_CLK_N1 0x0000003F /* n1 control */ | |
407 | #define SSB_CHIPCO_CLK_N2 0x00003F00 /* n2 control */ | |
408 | #define SSB_CHIPCO_CLK_N2_SHIFT 8 | |
409 | #define SSB_CHIPCO_CLK_PLLC 0x000F0000 /* pll control */ | |
410 | #define SSB_CHIPCO_CLK_PLLC_SHIFT 16 | |
411 | ||
412 | /* SSB_CHIPCO_CLOCK_SB/PCI/UART */ | |
413 | #define SSB_CHIPCO_CLK_M1 0x0000003F /* m1 control */ | |
414 | #define SSB_CHIPCO_CLK_M2 0x00003F00 /* m2 control */ | |
415 | #define SSB_CHIPCO_CLK_M2_SHIFT 8 | |
416 | #define SSB_CHIPCO_CLK_M3 0x003F0000 /* m3 control */ | |
417 | #define SSB_CHIPCO_CLK_M3_SHIFT 16 | |
418 | #define SSB_CHIPCO_CLK_MC 0x1F000000 /* mux control */ | |
419 | #define SSB_CHIPCO_CLK_MC_SHIFT 24 | |
420 | ||
421 | /* N3M Clock control magic field values */ | |
422 | #define SSB_CHIPCO_CLK_F6_2 0x02 /* A factor of 2 in */ | |
423 | #define SSB_CHIPCO_CLK_F6_3 0x03 /* 6-bit fields like */ | |
424 | #define SSB_CHIPCO_CLK_F6_4 0x05 /* N1, M1 or M3 */ | |
425 | #define SSB_CHIPCO_CLK_F6_5 0x09 | |
426 | #define SSB_CHIPCO_CLK_F6_6 0x11 | |
427 | #define SSB_CHIPCO_CLK_F6_7 0x21 | |
428 | ||
429 | #define SSB_CHIPCO_CLK_F5_BIAS 5 /* 5-bit fields get this added */ | |
430 | ||
431 | #define SSB_CHIPCO_CLK_MC_BYPASS 0x08 | |
432 | #define SSB_CHIPCO_CLK_MC_M1 0x04 | |
433 | #define SSB_CHIPCO_CLK_MC_M1M2 0x02 | |
434 | #define SSB_CHIPCO_CLK_MC_M1M2M3 0x01 | |
435 | #define SSB_CHIPCO_CLK_MC_M1M3 0x11 | |
436 | ||
437 | /* Type 2 Clock control magic field values */ | |
438 | #define SSB_CHIPCO_CLK_T2_BIAS 2 /* n1, n2, m1 & m3 bias */ | |
439 | #define SSB_CHIPCO_CLK_T2M2_BIAS 3 /* m2 bias */ | |
440 | ||
441 | #define SSB_CHIPCO_CLK_T2MC_M1BYP 1 | |
442 | #define SSB_CHIPCO_CLK_T2MC_M2BYP 2 | |
443 | #define SSB_CHIPCO_CLK_T2MC_M3BYP 4 | |
444 | ||
445 | /* Type 6 Clock control magic field values */ | |
446 | #define SSB_CHIPCO_CLK_T6_MMASK 1 /* bits of interest in m */ | |
447 | #define SSB_CHIPCO_CLK_T6_M0 120000000 /* sb clock for m = 0 */ | |
448 | #define SSB_CHIPCO_CLK_T6_M1 100000000 /* sb clock for m = 1 */ | |
449 | #define SSB_CHIPCO_CLK_SB2MIPS_T6(sb) (2 * (sb)) | |
450 | ||
451 | /* Common clock base */ | |
452 | #define SSB_CHIPCO_CLK_BASE1 24000000 /* Half the clock freq */ | |
453 | #define SSB_CHIPCO_CLK_BASE2 12500000 /* Alternate crystal on some PLL's */ | |
454 | ||
455 | /* Clock control values for 200Mhz in 5350 */ | |
456 | #define SSB_CHIPCO_CLK_5350_N 0x0311 | |
457 | #define SSB_CHIPCO_CLK_5350_M 0x04020009 | |
458 | ||
459 | ||
460 | /** Bits in the config registers **/ | |
461 | ||
462 | #define SSB_CHIPCO_CFG_EN 0x0001 /* Enable */ | |
463 | #define SSB_CHIPCO_CFG_EXTM 0x000E /* Extif Mode */ | |
464 | #define SSB_CHIPCO_CFG_EXTM_ASYNC 0x0002 /* Async/Parallel flash */ | |
465 | #define SSB_CHIPCO_CFG_EXTM_SYNC 0x0004 /* Synchronous */ | |
466 | #define SSB_CHIPCO_CFG_EXTM_PCMCIA 0x0008 /* PCMCIA */ | |
467 | #define SSB_CHIPCO_CFG_EXTM_IDE 0x000A /* IDE */ | |
468 | #define SSB_CHIPCO_CFG_DS16 0x0010 /* Data size, 0=8bit, 1=16bit */ | |
469 | #define SSB_CHIPCO_CFG_CLKDIV 0x0060 /* Sync: Clock divisor */ | |
470 | #define SSB_CHIPCO_CFG_CLKEN 0x0080 /* Sync: Clock enable */ | |
471 | #define SSB_CHIPCO_CFG_BSTRO 0x0100 /* Sync: Size/Bytestrobe */ | |
472 | ||
473 | ||
474 | /** Flash-specific control/status values */ | |
475 | ||
476 | /* flashcontrol opcodes for ST flashes */ | |
477 | #define SSB_CHIPCO_FLASHCTL_ST_WREN 0x0006 /* Write Enable */ | |
478 | #define SSB_CHIPCO_FLASHCTL_ST_WRDIS 0x0004 /* Write Disable */ | |
479 | #define SSB_CHIPCO_FLASHCTL_ST_RDSR 0x0105 /* Read Status Register */ | |
480 | #define SSB_CHIPCO_FLASHCTL_ST_WRSR 0x0101 /* Write Status Register */ | |
481 | #define SSB_CHIPCO_FLASHCTL_ST_READ 0x0303 /* Read Data Bytes */ | |
482 | #define SSB_CHIPCO_FLASHCTL_ST_PP 0x0302 /* Page Program */ | |
483 | #define SSB_CHIPCO_FLASHCTL_ST_SE 0x02D8 /* Sector Erase */ | |
484 | #define SSB_CHIPCO_FLASHCTL_ST_BE 0x00C7 /* Bulk Erase */ | |
485 | #define SSB_CHIPCO_FLASHCTL_ST_DP 0x00B9 /* Deep Power-down */ | |
486 | #define SSB_CHIPCO_FLASHCTL_ST_RSIG 0x03AB /* Read Electronic Signature */ | |
487 | ||
488 | /* Status register bits for ST flashes */ | |
489 | #define SSB_CHIPCO_FLASHSTA_ST_WIP 0x01 /* Write In Progress */ | |
490 | #define SSB_CHIPCO_FLASHSTA_ST_WEL 0x02 /* Write Enable Latch */ | |
491 | #define SSB_CHIPCO_FLASHSTA_ST_BP 0x1C /* Block Protect */ | |
492 | #define SSB_CHIPCO_FLASHSTA_ST_BP_SHIFT 2 | |
493 | #define SSB_CHIPCO_FLASHSTA_ST_SRWD 0x80 /* Status Register Write Disable */ | |
494 | ||
495 | /* flashcontrol opcodes for Atmel flashes */ | |
496 | #define SSB_CHIPCO_FLASHCTL_AT_READ 0x07E8 | |
497 | #define SSB_CHIPCO_FLASHCTL_AT_PAGE_READ 0x07D2 | |
498 | #define SSB_CHIPCO_FLASHCTL_AT_BUF1_READ /* FIXME */ | |
499 | #define SSB_CHIPCO_FLASHCTL_AT_BUF2_READ /* FIXME */ | |
500 | #define SSB_CHIPCO_FLASHCTL_AT_STATUS 0x01D7 | |
501 | #define SSB_CHIPCO_FLASHCTL_AT_BUF1_WRITE 0x0384 | |
502 | #define SSB_CHIPCO_FLASHCTL_AT_BUF2_WRITE 0x0387 | |
503 | #define SSB_CHIPCO_FLASHCTL_AT_BUF1_ERASE_PRGM 0x0283 /* Erase program */ | |
504 | #define SSB_CHIPCO_FLASHCTL_AT_BUF2_ERASE_PRGM 0x0286 /* Erase program */ | |
505 | #define SSB_CHIPCO_FLASHCTL_AT_BUF1_PROGRAM 0x0288 | |
506 | #define SSB_CHIPCO_FLASHCTL_AT_BUF2_PROGRAM 0x0289 | |
507 | #define SSB_CHIPCO_FLASHCTL_AT_PAGE_ERASE 0x0281 | |
508 | #define SSB_CHIPCO_FLASHCTL_AT_BLOCK_ERASE 0x0250 | |
509 | #define SSB_CHIPCO_FLASHCTL_AT_BUF1_WRER_PRGM 0x0382 /* Write erase program */ | |
510 | #define SSB_CHIPCO_FLASHCTL_AT_BUF2_WRER_PRGM 0x0385 /* Write erase program */ | |
511 | #define SSB_CHIPCO_FLASHCTL_AT_BUF1_LOAD 0x0253 | |
512 | #define SSB_CHIPCO_FLASHCTL_AT_BUF2_LOAD 0x0255 | |
513 | #define SSB_CHIPCO_FLASHCTL_AT_BUF1_COMPARE 0x0260 | |
514 | #define SSB_CHIPCO_FLASHCTL_AT_BUF2_COMPARE 0x0261 | |
515 | #define SSB_CHIPCO_FLASHCTL_AT_BUF1_REPROGRAM 0x0258 | |
516 | #define SSB_CHIPCO_FLASHCTL_AT_BUF2_REPROGRAM 0x0259 | |
517 | ||
518 | /* Status register bits for Atmel flashes */ | |
519 | #define SSB_CHIPCO_FLASHSTA_AT_READY 0x80 | |
520 | #define SSB_CHIPCO_FLASHSTA_AT_MISMATCH 0x40 | |
521 | #define SSB_CHIPCO_FLASHSTA_AT_ID 0x38 | |
522 | #define SSB_CHIPCO_FLASHSTA_AT_ID_SHIFT 3 | |
523 | ||
524 | ||
525 | /** OTP **/ | |
526 | ||
527 | /* OTP regions */ | |
528 | #define SSB_CHIPCO_OTP_HW_REGION SSB_CHIPCO_OTPS_HW_PROTECT | |
529 | #define SSB_CHIPCO_OTP_SW_REGION SSB_CHIPCO_OTPS_SW_PROTECT | |
530 | #define SSB_CHIPCO_OTP_CID_REGION SSB_CHIPCO_OTPS_CID_PROTECT | |
531 | ||
532 | /* OTP regions (Byte offsets from otp size) */ | |
533 | #define SSB_CHIPCO_OTP_SWLIM_OFF (-8) | |
534 | #define SSB_CHIPCO_OTP_CIDBASE_OFF 0 | |
535 | #define SSB_CHIPCO_OTP_CIDLIM_OFF 8 | |
536 | ||
537 | /* Predefined OTP words (Word offset from otp size) */ | |
538 | #define SSB_CHIPCO_OTP_BOUNDARY_OFF (-4) | |
539 | #define SSB_CHIPCO_OTP_HWSIGN_OFF (-3) | |
540 | #define SSB_CHIPCO_OTP_SWSIGN_OFF (-2) | |
541 | #define SSB_CHIPCO_OTP_CIDSIGN_OFF (-1) | |
542 | ||
543 | #define SSB_CHIPCO_OTP_CID_OFF 0 | |
544 | #define SSB_CHIPCO_OTP_PKG_OFF 1 | |
545 | #define SSB_CHIPCO_OTP_FID_OFF 2 | |
546 | #define SSB_CHIPCO_OTP_RSV_OFF 3 | |
547 | #define SSB_CHIPCO_OTP_LIM_OFF 4 | |
548 | ||
549 | #define SSB_CHIPCO_OTP_SIGNATURE 0x578A | |
550 | #define SSB_CHIPCO_OTP_MAGIC 0x4E56 | |
551 | ||
552 | ||
553 | struct ssb_device; | |
554 | struct ssb_serial_port; | |
555 | ||
c9703146 MB |
556 | /* Data for the PMU, if available. |
557 | * Check availability with ((struct ssb_chipcommon)->capabilities & SSB_CHIPCO_CAP_PMU) | |
558 | */ | |
559 | struct ssb_chipcommon_pmu { | |
560 | u8 rev; /* PMU revision */ | |
561 | u32 crystalfreq; /* The active crystal frequency (in kHz) */ | |
562 | }; | |
563 | ||
61e115a5 MB |
564 | struct ssb_chipcommon { |
565 | struct ssb_device *dev; | |
566 | u32 capabilities; | |
567 | /* Fast Powerup Delay constant */ | |
568 | u16 fast_pwrup_delay; | |
c9703146 | 569 | struct ssb_chipcommon_pmu pmu; |
61e115a5 MB |
570 | }; |
571 | ||
42bfad4f MB |
572 | static inline bool ssb_chipco_available(struct ssb_chipcommon *cc) |
573 | { | |
574 | return (cc->dev != NULL); | |
575 | } | |
576 | ||
c9703146 MB |
577 | /* Register access */ |
578 | #define chipco_read32(cc, offset) ssb_read32((cc)->dev, offset) | |
579 | #define chipco_write32(cc, offset, val) ssb_write32((cc)->dev, offset, val) | |
580 | ||
581 | #define chipco_mask32(cc, offset, mask) \ | |
582 | chipco_write32(cc, offset, chipco_read32(cc, offset) & (mask)) | |
583 | #define chipco_set32(cc, offset, set) \ | |
584 | chipco_write32(cc, offset, chipco_read32(cc, offset) | (set)) | |
585 | #define chipco_maskset32(cc, offset, mask, set) \ | |
586 | chipco_write32(cc, offset, (chipco_read32(cc, offset) & (mask)) | (set)) | |
587 | ||
61e115a5 MB |
588 | extern void ssb_chipcommon_init(struct ssb_chipcommon *cc); |
589 | ||
8fe2b65a | 590 | extern void ssb_chipco_suspend(struct ssb_chipcommon *cc); |
61e115a5 MB |
591 | extern void ssb_chipco_resume(struct ssb_chipcommon *cc); |
592 | ||
593 | extern void ssb_chipco_get_clockcpu(struct ssb_chipcommon *cc, | |
594 | u32 *plltype, u32 *n, u32 *m); | |
595 | extern void ssb_chipco_get_clockcontrol(struct ssb_chipcommon *cc, | |
596 | u32 *plltype, u32 *n, u32 *m); | |
597 | extern void ssb_chipco_timing_init(struct ssb_chipcommon *cc, | |
598 | unsigned long ns_per_cycle); | |
599 | ||
600 | enum ssb_clkmode { | |
601 | SSB_CLKMODE_SLOW, | |
602 | SSB_CLKMODE_FAST, | |
603 | SSB_CLKMODE_DYNAMIC, | |
604 | }; | |
605 | ||
606 | extern void ssb_chipco_set_clockmode(struct ssb_chipcommon *cc, | |
607 | enum ssb_clkmode mode); | |
608 | ||
609 | extern void ssb_chipco_watchdog_timer_set(struct ssb_chipcommon *cc, | |
610 | u32 ticks); | |
611 | ||
28de57d1 AJ |
612 | void ssb_chipco_irq_mask(struct ssb_chipcommon *cc, u32 mask, u32 value); |
613 | ||
614 | u32 ssb_chipco_irq_status(struct ssb_chipcommon *cc, u32 mask); | |
615 | ||
c2bcbe65 | 616 | /* Chipcommon GPIO pin access. */ |
61e115a5 | 617 | u32 ssb_chipco_gpio_in(struct ssb_chipcommon *cc, u32 mask); |
c2bcbe65 MB |
618 | u32 ssb_chipco_gpio_out(struct ssb_chipcommon *cc, u32 mask, u32 value); |
619 | u32 ssb_chipco_gpio_outen(struct ssb_chipcommon *cc, u32 mask, u32 value); | |
620 | u32 ssb_chipco_gpio_control(struct ssb_chipcommon *cc, u32 mask, u32 value); | |
621 | u32 ssb_chipco_gpio_intmask(struct ssb_chipcommon *cc, u32 mask, u32 value); | |
622 | u32 ssb_chipco_gpio_polarity(struct ssb_chipcommon *cc, u32 mask, u32 value); | |
61e115a5 MB |
623 | |
624 | #ifdef CONFIG_SSB_SERIAL | |
625 | extern int ssb_chipco_serial_init(struct ssb_chipcommon *cc, | |
626 | struct ssb_serial_port *ports); | |
627 | #endif /* CONFIG_SSB_SERIAL */ | |
628 | ||
c9703146 MB |
629 | /* PMU support */ |
630 | extern void ssb_pmu_init(struct ssb_chipcommon *cc); | |
631 | ||
06e4da26 GS |
632 | enum ssb_pmu_ldo_volt_id { |
633 | LDO_PAREF = 0, | |
634 | LDO_VOLT1, | |
635 | LDO_VOLT2, | |
636 | LDO_VOLT3, | |
637 | }; | |
638 | ||
639 | void ssb_pmu_set_ldo_voltage(struct ssb_chipcommon *cc, | |
640 | enum ssb_pmu_ldo_volt_id id, u32 voltage); | |
641 | void ssb_pmu_set_ldo_paref(struct ssb_chipcommon *cc, bool on); | |
c9703146 | 642 | |
61e115a5 | 643 | #endif /* LINUX_SSB_CHIPCO_H_ */ |