[mirror_ubuntu-focal-kernel.git] / include / linux / ssb / ssb_driver_gige.h

#ifndef LINUX_SSB_DRIVER_GIGE_H_
#define LINUX_SSB_DRIVER_GIGE_H_

#include <linux/ssb/ssb.h>
#include <linux/bug.h>
#include <linux/pci.h>
#include <linux/spinlock.h>


#ifdef CONFIG_SSB_DRIVER_GIGE


#define SSB_GIGE_PCIIO			0x0000 /* PCI I/O Registers (1024 bytes) */
#define SSB_GIGE_RESERVED		0x0400 /* Reserved (1024 bytes) */
#define SSB_GIGE_PCICFG			0x0800 /* PCI config space (256 bytes) */
#define SSB_GIGE_SHIM_FLUSHSTAT		0x0C00 /* PCI to OCP: Flush status control (32bit) */
#define SSB_GIGE_SHIM_FLUSHRDA		0x0C04 /* PCI to OCP: Flush read address (32bit) */
#define SSB_GIGE_SHIM_FLUSHTO		0x0C08 /* PCI to OCP: Flush timeout counter (32bit) */
#define SSB_GIGE_SHIM_BARRIER		0x0C0C /* PCI to OCP: Barrier register (32bit) */
#define SSB_GIGE_SHIM_MAOCPSI		0x0C10 /* PCI to OCP: MaocpSI Control (32bit) */
#define SSB_GIGE_SHIM_SIOCPMA		0x0C14 /* PCI to OCP: SiocpMa Control (32bit) */

/* TM Status High flags */
#define SSB_GIGE_TMSHIGH_RGMII		0x00010000 /* Have an RGMII PHY-bus */
/* TM Status Low flags */
#define SSB_GIGE_TMSLOW_TXBYPASS	0x00080000 /* TX bypass (no delay) */
#define SSB_GIGE_TMSLOW_RXBYPASS	0x00100000 /* RX bypass (no delay) */
#define SSB_GIGE_TMSLOW_DLLEN		0x01000000 /* Enable DLL controls */

/* Boardflags (low) */
#define SSB_GIGE_BFL_ROBOSWITCH		0x0010


#define SSB_GIGE_MEM_RES_NAME		"SSB Broadcom 47xx GigE memory"
#define SSB_GIGE_IO_RES_NAME		"SSB Broadcom 47xx GigE I/O"

struct ssb_gige {
	struct ssb_device *dev;

	spinlock_t lock;

	/* True, if the device has an RGMII bus.
	 * False, if the device has a GMII bus. */
	bool has_rgmii;

	/* The PCI controller device. */
	struct pci_controller pci_controller;
	struct pci_ops pci_ops;
	struct resource mem_resource;
	struct resource io_resource;
};

/* Check whether a PCI device is a SSB Gigabit Ethernet core. */
extern bool pdev_is_ssb_gige_core(struct pci_dev *pdev);

/* Convert a pci_dev pointer to a ssb_gige pointer. */
static inline struct ssb_gige * pdev_to_ssb_gige(struct pci_dev *pdev)
{
	if (!pdev_is_ssb_gige_core(pdev))
		return NULL;
	return container_of(pdev->bus->ops, struct ssb_gige, pci_ops);
}

/* Returns whether the PHY is connected by an RGMII bus. */
static inline bool ssb_gige_is_rgmii(struct pci_dev *pdev)
{
	struct ssb_gige *dev = pdev_to_ssb_gige(pdev);
	return (dev ? dev->has_rgmii : 0);
}

/* Returns whether we have a Roboswitch. */
static inline bool ssb_gige_have_roboswitch(struct pci_dev *pdev)
{
	struct ssb_gige *dev = pdev_to_ssb_gige(pdev);
	if (dev)
		return !!(dev->dev->bus->sprom.boardflags_lo &
			  SSB_GIGE_BFL_ROBOSWITCH);
	return 0;
}

/* Returns whether we can only do one DMA at once. */
static inline bool ssb_gige_one_dma_at_once(struct pci_dev *pdev)
{
	struct ssb_gige *dev = pdev_to_ssb_gige(pdev);
	if (dev)
		return ((dev->dev->bus->chip_id == 0x4785) &&
			(dev->dev->bus->chip_rev < 2));
	return 0;
}

/* Returns whether we must flush posted writes. */
static inline bool ssb_gige_must_flush_posted_writes(struct pci_dev *pdev)
{
	struct ssb_gige *dev = pdev_to_ssb_gige(pdev);
	if (dev)
		return (dev->dev->bus->chip_id == 0x4785);
	return 0;
}

/* Get the device MAC address */
static inline int ssb_gige_get_macaddr(struct pci_dev *pdev, u8 *macaddr)
{
	struct ssb_gige *dev = pdev_to_ssb_gige(pdev);
	if (!dev)
		return -ENODEV;

	memcpy(macaddr, dev->dev->bus->sprom.et0mac, 6);
	return 0;
}

/* Get the device phy address */
static inline int ssb_gige_get_phyaddr(struct pci_dev *pdev)
{
	struct ssb_gige *dev = pdev_to_ssb_gige(pdev);
	if (!dev)
		return -ENODEV;

	return dev->dev->bus->sprom.et0phyaddr;
}

extern int ssb_gige_pcibios_plat_dev_init(struct ssb_device *sdev,
					  struct pci_dev *pdev);
extern int ssb_gige_map_irq(struct ssb_device *sdev,
			    const struct pci_dev *pdev);

/* The GigE driver is not a standalone module, because we don't have support
 * for unregistering the driver. So we could not unload the module anyway. */
extern int ssb_gige_init(void);
static inline void ssb_gige_exit(void)
{
	/* Currently we can not unregister the GigE driver,
	 * because we can not unregister the PCI bridge. */
	BUG();
}


#else /* CONFIG_SSB_DRIVER_GIGE */
/* Gigabit Ethernet driver disabled */


static inline int ssb_gige_pcibios_plat_dev_init(struct ssb_device *sdev,
						 struct pci_dev *pdev)
{
	return -ENOSYS;
}
static inline int ssb_gige_map_irq(struct ssb_device *sdev,
				   const struct pci_dev *pdev)
{
	return -ENOSYS;
}
static inline int ssb_gige_init(void)
{
	return 0;
}
static inline void ssb_gige_exit(void)
{
}

static inline bool pdev_is_ssb_gige_core(struct pci_dev *pdev)
{
	return 0;
}
static inline struct ssb_gige * pdev_to_ssb_gige(struct pci_dev *pdev)
{
	return NULL;
}
static inline bool ssb_gige_is_rgmii(struct pci_dev *pdev)
{
	return 0;
}
static inline bool ssb_gige_have_roboswitch(struct pci_dev *pdev)
{
	return 0;
}
static inline bool ssb_gige_one_dma_at_once(struct pci_dev *pdev)
{
	return 0;
}
static inline bool ssb_gige_must_flush_posted_writes(struct pci_dev *pdev)
{
	return 0;
}
static inline int ssb_gige_get_macaddr(struct pci_dev *pdev, u8 *macaddr)
{
	return -ENODEV;
}
static inline int ssb_gige_get_phyaddr(struct pci_dev *pdev)
{
	return -ENODEV;
}

#endif /* CONFIG_SSB_DRIVER_GIGE */
#endif /* LINUX_SSB_DRIVER_GIGE_H_ */
Commit	Line	Data
aab547ce MB	1	#ifndef LINUX_SSB_DRIVER_GIGE_H_
	2	#define LINUX_SSB_DRIVER_GIGE_H_
	3
	4	#include <linux/ssb/ssb.h>
187f1882	5	#include <linux/bug.h>
aab547ce MB	6	#include <linux/pci.h>
	7	#include <linux/spinlock.h>
	8
	9
	10	#ifdef CONFIG_SSB_DRIVER_GIGE
	11
	12
	13	#define SSB_GIGE_PCIIO 0x0000 /* PCI I/O Registers (1024 bytes) */
	14	#define SSB_GIGE_RESERVED 0x0400 /* Reserved (1024 bytes) */
	15	#define SSB_GIGE_PCICFG 0x0800 /* PCI config space (256 bytes) */
	16	#define SSB_GIGE_SHIM_FLUSHSTAT 0x0C00 /* PCI to OCP: Flush status control (32bit) */
	17	#define SSB_GIGE_SHIM_FLUSHRDA 0x0C04 /* PCI to OCP: Flush read address (32bit) */
	18	#define SSB_GIGE_SHIM_FLUSHTO 0x0C08 /* PCI to OCP: Flush timeout counter (32bit) */
	19	#define SSB_GIGE_SHIM_BARRIER 0x0C0C /* PCI to OCP: Barrier register (32bit) */
	20	#define SSB_GIGE_SHIM_MAOCPSI 0x0C10 /* PCI to OCP: MaocpSI Control (32bit) */
	21	#define SSB_GIGE_SHIM_SIOCPMA 0x0C14 /* PCI to OCP: SiocpMa Control (32bit) */
	22
	23	/* TM Status High flags */
	24	#define SSB_GIGE_TMSHIGH_RGMII 0x00010000 /* Have an RGMII PHY-bus */
	25	/* TM Status Low flags */
	26	#define SSB_GIGE_TMSLOW_TXBYPASS 0x00080000 /* TX bypass (no delay) */
	27	#define SSB_GIGE_TMSLOW_RXBYPASS 0x00100000 /* RX bypass (no delay) */
	28	#define SSB_GIGE_TMSLOW_DLLEN 0x01000000 /* Enable DLL controls */
	29
	30	/* Boardflags (low) */
	31	#define SSB_GIGE_BFL_ROBOSWITCH 0x0010
	32
	33
	34	#define SSB_GIGE_MEM_RES_NAME "SSB Broadcom 47xx GigE memory"
	35	#define SSB_GIGE_IO_RES_NAME "SSB Broadcom 47xx GigE I/O"
	36
	37	struct ssb_gige {
	38	struct ssb_device *dev;
	39
	40	spinlock_t lock;
	41
	42	/* True, if the device has an RGMII bus.
	43	* False, if the device has a GMII bus. */
	44	bool has_rgmii;
	45
	46	/* The PCI controller device. */
	47	struct pci_controller pci_controller;
	48	struct pci_ops pci_ops;
	49	struct resource mem_resource;
	50	struct resource io_resource;
	51	};
	52
	53	/* Check whether a PCI device is a SSB Gigabit Ethernet core. */
	54	extern bool pdev_is_ssb_gige_core(struct pci_dev *pdev);
	55
	56	/* Convert a pci_dev pointer to a ssb_gige pointer. */
	57	static inline struct ssb_gige * pdev_to_ssb_gige(struct pci_dev *pdev)
	58	{
	59	if (!pdev_is_ssb_gige_core(pdev))
	60	return NULL;
	61	return container_of(pdev->bus->ops, struct ssb_gige, pci_ops);
	62	}
	63
	64	/* Returns whether the PHY is connected by an RGMII bus. */
	65	static inline bool ssb_gige_is_rgmii(struct pci_dev *pdev)
	66	{
	67	struct ssb_gige *dev = pdev_to_ssb_gige(pdev);
	68	return (dev ? dev->has_rgmii : 0);
	69	}
70
71	/* Returns whether we have a Roboswitch. */
72	static inline bool ssb_gige_have_roboswitch(struct pci_dev *pdev)
73	{
74	struct ssb_gige *dev = pdev_to_ssb_gige(pdev);
75	if (dev)
76	return !!(dev->dev->bus->sprom.boardflags_lo &
77	SSB_GIGE_BFL_ROBOSWITCH);
78	return 0;
79	}
80
81	/* Returns whether we can only do one DMA at once. */
82	static inline bool ssb_gige_one_dma_at_once(struct pci_dev *pdev)
83	{
84	struct ssb_gige *dev = pdev_to_ssb_gige(pdev);
85	if (dev)
86	return ((dev->dev->bus->chip_id == 0x4785) &&
87	(dev->dev->bus->chip_rev < 2));
88	return 0;
89	}
90
91	/* Returns whether we must flush posted writes. */
92	static inline bool ssb_gige_must_flush_posted_writes(struct pci_dev *pdev)
93	{
94	struct ssb_gige *dev = pdev_to_ssb_gige(pdev);
95	if (dev)
96	return (dev->dev->bus->chip_id == 0x4785);
97	return 0;
98	}
99
aab547ce	100	/* Get the device MAC address */
180996c3	101	static inline int ssb_gige_get_macaddr(struct pci_dev pdev, u8 macaddr)
3f84622d	102	{
180996c3 HM	103	struct ssb_gige *dev = pdev_to_ssb_gige(pdev);
	104	if (!dev)
	105	return -ENODEV;
	106
	107	memcpy(macaddr, dev->dev->bus->sprom.et0mac, 6);
	108	return 0;
3f84622d	109	}
aab547ce	110
4bcef89f HM	111	/* Get the device phy address */
	112	static inline int ssb_gige_get_phyaddr(struct pci_dev *pdev)
	113	{
	114	struct ssb_gige *dev = pdev_to_ssb_gige(pdev);
	115	if (!dev)
	116	return -ENODEV;
	117
	118	return dev->dev->bus->sprom.et0phyaddr;
	119	}
	120
aab547ce MB	121	extern int ssb_gige_pcibios_plat_dev_init(struct ssb_device *sdev,
	122	struct pci_dev *pdev);
	123	extern int ssb_gige_map_irq(struct ssb_device *sdev,
	124	const struct pci_dev *pdev);
	125
	126	/* The GigE driver is not a standalone module, because we don't have support
	127	* for unregistering the driver. So we could not unload the module anyway. */
	128	extern int ssb_gige_init(void);
	129	static inline void ssb_gige_exit(void)
	130	{
	131	/* Currently we can not unregister the GigE driver,
	132	* because we can not unregister the PCI bridge. */
	133	BUG();
	134	}
	135
	136
	137	#else /* CONFIG_SSB_DRIVER_GIGE */
	138	/* Gigabit Ethernet driver disabled */
	139
	140
	141	static inline int ssb_gige_pcibios_plat_dev_init(struct ssb_device *sdev,
	142	struct pci_dev *pdev)
	143	{
	144	return -ENOSYS;
	145	}
	146	static inline int ssb_gige_map_irq(struct ssb_device *sdev,
	147	const struct pci_dev *pdev)
	148	{
	149	return -ENOSYS;
	150	}
	151	static inline int ssb_gige_init(void)
	152	{
	153	return 0;
	154	}
	155	static inline void ssb_gige_exit(void)
	156	{
	157	}
	158
	159	static inline bool pdev_is_ssb_gige_core(struct pci_dev *pdev)
	160	{
	161	return 0;
	162	}
	163	static inline struct ssb_gige * pdev_to_ssb_gige(struct pci_dev *pdev)
	164	{
	165	return NULL;
	166	}
	167	static inline bool ssb_gige_is_rgmii(struct pci_dev *pdev)
	168	{
	169	return 0;
	170	}
	171	static inline bool ssb_gige_have_roboswitch(struct pci_dev *pdev)
	172	{
	173	return 0;
	174	}
	175	static inline bool ssb_gige_one_dma_at_once(struct pci_dev *pdev)
	176	{
	177	return 0;
	178	}
	179	static inline bool ssb_gige_must_flush_posted_writes(struct pci_dev *pdev)
	180	{
	181	return 0;
	182	}
180996c3 HM	183	static inline int ssb_gige_get_macaddr(struct pci_dev pdev, u8 macaddr)
	184	{
	185	return -ENODEV;
	186	}
4bcef89f HM	187	static inline int ssb_gige_get_phyaddr(struct pci_dev *pdev)
	188	{
	189	return -ENODEV;
	190	}
aab547ce MB	191
	192	#endif /* CONFIG_SSB_DRIVER_GIGE */
	193	#endif /* LINUX_SSB_DRIVER_GIGE_H_ */