[mirror_ubuntu-kernels.git] / include / linux / stmmac.h

/* SPDX-License-Identifier: GPL-2.0-only */
/*******************************************************************************

  Header file for stmmac platform data

  Copyright (C) 2009  STMicroelectronics Ltd


  Author: Giuseppe Cavallaro <peppe.cavallaro@st.com>
*******************************************************************************/

#ifndef __STMMAC_PLATFORM_DATA
#define __STMMAC_PLATFORM_DATA

#include <linux/platform_device.h>
#include <linux/phy.h>

#define MTL_MAX_RX_QUEUES	8
#define MTL_MAX_TX_QUEUES	8
#define STMMAC_CH_MAX		8

#define STMMAC_RX_COE_NONE	0
#define STMMAC_RX_COE_TYPE1	1
#define STMMAC_RX_COE_TYPE2	2

/* Define the macros for CSR clock range parameters to be passed by
 * platform code.
 * This could also be configured at run time using CPU freq framework. */

/* MDC Clock Selection define*/
#define	STMMAC_CSR_60_100M	0x0	/* MDC = clk_scr_i/42 */
#define	STMMAC_CSR_100_150M	0x1	/* MDC = clk_scr_i/62 */
#define	STMMAC_CSR_20_35M	0x2	/* MDC = clk_scr_i/16 */
#define	STMMAC_CSR_35_60M	0x3	/* MDC = clk_scr_i/26 */
#define	STMMAC_CSR_150_250M	0x4	/* MDC = clk_scr_i/102 */
#define	STMMAC_CSR_250_300M	0x5	/* MDC = clk_scr_i/122 */

/* MTL algorithms identifiers */
#define MTL_TX_ALGORITHM_WRR	0x0
#define MTL_TX_ALGORITHM_WFQ	0x1
#define MTL_TX_ALGORITHM_DWRR	0x2
#define MTL_TX_ALGORITHM_SP	0x3
#define MTL_RX_ALGORITHM_SP	0x4
#define MTL_RX_ALGORITHM_WSP	0x5

/* RX/TX Queue Mode */
#define MTL_QUEUE_AVB		0x0
#define MTL_QUEUE_DCB		0x1

/* The MDC clock could be set higher than the IEEE 802.3
 * specified frequency limit 0f 2.5 MHz, by programming a clock divider
 * of value different than the above defined values. The resultant MDIO
 * clock frequency of 12.5 MHz is applicable for the interfacing chips
 * supporting higher MDC clocks.
 * The MDC clock selection macros need to be defined for MDC clock rate
 * of 12.5 MHz, corresponding to the following selection.
 */
#define STMMAC_CSR_I_4		0x8	/* clk_csr_i/4 */
#define STMMAC_CSR_I_6		0x9	/* clk_csr_i/6 */
#define STMMAC_CSR_I_8		0xA	/* clk_csr_i/8 */
#define STMMAC_CSR_I_10		0xB	/* clk_csr_i/10 */
#define STMMAC_CSR_I_12		0xC	/* clk_csr_i/12 */
#define STMMAC_CSR_I_14		0xD	/* clk_csr_i/14 */
#define STMMAC_CSR_I_16		0xE	/* clk_csr_i/16 */
#define STMMAC_CSR_I_18		0xF	/* clk_csr_i/18 */

/* AXI DMA Burst length supported */
#define DMA_AXI_BLEN_4		(1 << 1)
#define DMA_AXI_BLEN_8		(1 << 2)
#define DMA_AXI_BLEN_16		(1 << 3)
#define DMA_AXI_BLEN_32		(1 << 4)
#define DMA_AXI_BLEN_64		(1 << 5)
#define DMA_AXI_BLEN_128	(1 << 6)
#define DMA_AXI_BLEN_256	(1 << 7)
#define DMA_AXI_BLEN_ALL (DMA_AXI_BLEN_4 | DMA_AXI_BLEN_8 | DMA_AXI_BLEN_16 \
			| DMA_AXI_BLEN_32 | DMA_AXI_BLEN_64 \
			| DMA_AXI_BLEN_128 | DMA_AXI_BLEN_256)

/* Platfrom data for platform device structure's platform_data field */

struct stmmac_mdio_bus_data {
	unsigned int phy_mask;
	unsigned int has_xpcs;
	unsigned int xpcs_an_inband;
	int *irqs;
	int probed_phy_irq;
	bool needs_reset;
};

struct stmmac_dma_cfg {
	int pbl;
	int txpbl;
	int rxpbl;
	bool pblx8;
	int fixed_burst;
	int mixed_burst;
	bool aal;
	bool eame;
	bool multi_msi_en;
	bool dche;
};

#define AXI_BLEN	7
struct stmmac_axi {
	bool axi_lpi_en;
	bool axi_xit_frm;
	u32 axi_wr_osr_lmt;
	u32 axi_rd_osr_lmt;
	bool axi_kbbe;
	u32 axi_blen[AXI_BLEN];
	bool axi_fb;
	bool axi_mb;
	bool axi_rb;
};

#define EST_GCL		1024
struct stmmac_est {
	int enable;
	u32 btr_offset[2];
	u32 btr[2];
	u32 ctr[2];
	u32 ter;
	u32 gcl_unaligned[EST_GCL];
	u32 gcl[EST_GCL];
	u32 gcl_size;
};

struct stmmac_rxq_cfg {
	u8 mode_to_use;
	u32 chan;
	u8 pkt_route;
	bool use_prio;
	u32 prio;
};

struct stmmac_txq_cfg {
	u32 weight;
	u8 mode_to_use;
	/* Credit Base Shaper parameters */
	u32 send_slope;
	u32 idle_slope;
	u32 high_credit;
	u32 low_credit;
	bool use_prio;
	u32 prio;
	int tbs_en;
};

/* FPE link state */
enum stmmac_fpe_state {
	FPE_STATE_OFF = 0,
	FPE_STATE_CAPABLE = 1,
	FPE_STATE_ENTERING_ON = 2,
	FPE_STATE_ON = 3,
};

/* FPE link-partner hand-shaking mPacket type */
enum stmmac_mpacket_type {
	MPACKET_VERIFY = 0,
	MPACKET_RESPONSE = 1,
};

enum stmmac_fpe_task_state_t {
	__FPE_REMOVING,
	__FPE_TASK_SCHED,
};

struct stmmac_fpe_cfg {
	bool enable;				/* FPE enable */
	bool hs_enable;				/* FPE handshake enable */
	enum stmmac_fpe_state lp_fpe_state;	/* Link Partner FPE state */
	enum stmmac_fpe_state lo_fpe_state;	/* Local station FPE state */
};

struct plat_stmmacenet_data {
	int bus_id;
	int phy_addr;
	int interface;
	phy_interface_t phy_interface;
	struct stmmac_mdio_bus_data *mdio_bus_data;
	struct device_node *phy_node;
	struct device_node *phylink_node;
	struct device_node *mdio_node;
	struct stmmac_dma_cfg *dma_cfg;
	struct stmmac_est *est;
	struct stmmac_fpe_cfg *fpe_cfg;
	int clk_csr;
	int has_gmac;
	int enh_desc;
	int tx_coe;
	int rx_coe;
	int bugged_jumbo;
	int pmt;
	int force_sf_dma_mode;
	int force_thresh_dma_mode;
	int riwt_off;
	int max_speed;
	int maxmtu;
	int multicast_filter_bins;
	int unicast_filter_entries;
	int tx_fifo_size;
	int rx_fifo_size;
	u32 addr64;
	u32 rx_queues_to_use;
	u32 tx_queues_to_use;
	u8 rx_sched_algorithm;
	u8 tx_sched_algorithm;
	struct stmmac_rxq_cfg rx_queues_cfg[MTL_MAX_RX_QUEUES];
	struct stmmac_txq_cfg tx_queues_cfg[MTL_MAX_TX_QUEUES];
	void (*fix_mac_speed)(void *priv, unsigned int speed);
	int (*serdes_powerup)(struct net_device *ndev, void *priv);
	void (*serdes_powerdown)(struct net_device *ndev, void *priv);
	void (*ptp_clk_freq_config)(void *priv);
	int (*init)(struct platform_device *pdev, void *priv);
	void (*exit)(struct platform_device *pdev, void *priv);
	struct mac_device_info *(*setup)(void *priv);
	int (*clks_config)(void *priv, bool enabled);
	int (*crosststamp)(ktime_t *device, struct system_counterval_t *system,
			   void *ctx);
	void *bsp_priv;
	struct clk *stmmac_clk;
	struct clk *pclk;
	struct clk *clk_ptp_ref;
	unsigned int clk_ptp_rate;
	unsigned int clk_ref_rate;
	s32 ptp_max_adj;
	struct reset_control *stmmac_rst;
	struct stmmac_axi *axi;
	int has_gmac4;
	bool has_sun8i;
	bool tso_en;
	int rss_en;
	int mac_port_sel_speed;
	bool en_tx_lpi_clockgating;
	int has_xgmac;
	bool vlan_fail_q_en;
	u8 vlan_fail_q;
	unsigned int eee_usecs_rate;
	struct pci_dev *pdev;
	bool has_crossts;
	int int_snapshot_num;
	int ext_snapshot_num;
	bool ext_snapshot_en;
	bool multi_msi_en;
	int msi_mac_vec;
	int msi_wol_vec;
	int msi_lpi_vec;
	int msi_sfty_ce_vec;
	int msi_sfty_ue_vec;
	int msi_rx_base_vec;
	int msi_tx_base_vec;
};
#endif
Commit	Line	Data
1237a75a	1	/* SPDX-License-Identifier: GPL-2.0-only */
3c9732c0 GC	2	/*******************************************************************************
	3
	4	Header file for stmmac platform data
	5
	6	Copyright (C) 2009 STMicroelectronics Ltd
	7
3c9732c0 GC	8
	9	Author: Giuseppe Cavallaro <peppe.cavallaro@st.com>
	10	*******************************************************************************/
	11
	12	#ifndef __STMMAC_PLATFORM_DATA
	13	#define __STMMAC_PLATFORM_DATA
	14
57a503c6	15	#include <linux/platform_device.h>
0c65b2b9	16	#include <linux/phy.h>
57a503c6	17
d976a525 JP	18	#define MTL_MAX_RX_QUEUES 8
d976a525 JP	19	#define MTL_MAX_TX_QUEUES 8
8fce3331	20	#define STMMAC_CH_MAX 8
d976a525	21
55f9a4d6 DS	22	#define STMMAC_RX_COE_NONE 0
	23	#define STMMAC_RX_COE_TYPE1 1
	24	#define STMMAC_RX_COE_TYPE2 2
	25
faeae3fa DS	26	/* Define the macros for CSR clock range parameters to be passed by
	27	* platform code.
	28	* This could also be configured at run time using CPU freq framework. */
	29
	30	/* MDC Clock Selection define*/
18f05d64 GC	31	#define STMMAC_CSR_60_100M 0x0 /* MDC = clk_scr_i/42 */
	32	#define STMMAC_CSR_100_150M 0x1 /* MDC = clk_scr_i/62 */
	33	#define STMMAC_CSR_20_35M 0x2 /* MDC = clk_scr_i/16 */
	34	#define STMMAC_CSR_35_60M 0x3 /* MDC = clk_scr_i/26 */
	35	#define STMMAC_CSR_150_250M 0x4 /* MDC = clk_scr_i/102 */
	36	#define STMMAC_CSR_250_300M 0x5 /* MDC = clk_scr_i/122 */
faeae3fa	37
d976a525 JP	38	/* MTL algorithms identifiers */
	39	#define MTL_TX_ALGORITHM_WRR 0x0
	40	#define MTL_TX_ALGORITHM_WFQ 0x1
	41	#define MTL_TX_ALGORITHM_DWRR 0x2
	42	#define MTL_TX_ALGORITHM_SP 0x3
	43	#define MTL_RX_ALGORITHM_SP 0x4
	44	#define MTL_RX_ALGORITHM_WSP 0x5
	45
19d91873	46	/* RX/TX Queue Mode */
2d72d501 TR	47	#define MTL_QUEUE_AVB 0x0
2d72d501 TR	48	#define MTL_QUEUE_DCB 0x1
d976a525	49
18f05d64	50	/* The MDC clock could be set higher than the IEEE 802.3
faeae3fa DS	51	* specified frequency limit 0f 2.5 MHz, by programming a clock divider
	52	* of value different than the above defined values. The resultant MDIO
	53	* clock frequency of 12.5 MHz is applicable for the interfacing chips
	54	* supporting higher MDC clocks.
	55	* The MDC clock selection macros need to be defined for MDC clock rate
	56	* of 12.5 MHz, corresponding to the following selection.
18f05d64 GC	57	*/
	58	#define STMMAC_CSR_I_4 0x8 /* clk_csr_i/4 */
	59	#define STMMAC_CSR_I_6 0x9 /* clk_csr_i/6 */
	60	#define STMMAC_CSR_I_8 0xA /* clk_csr_i/8 */
	61	#define STMMAC_CSR_I_10 0xB /* clk_csr_i/10 */
	62	#define STMMAC_CSR_I_12 0xC /* clk_csr_i/12 */
	63	#define STMMAC_CSR_I_14 0xD /* clk_csr_i/14 */
	64	#define STMMAC_CSR_I_16 0xE /* clk_csr_i/16 */
	65	#define STMMAC_CSR_I_18 0xF /* clk_csr_i/18 */
faeae3fa	66
02582e9b	67	/* AXI DMA Burst length supported */
8327eb65 DS	68	#define DMA_AXI_BLEN_4 (1 << 1)
	69	#define DMA_AXI_BLEN_8 (1 << 2)
	70	#define DMA_AXI_BLEN_16 (1 << 3)
	71	#define DMA_AXI_BLEN_32 (1 << 4)
	72	#define DMA_AXI_BLEN_64 (1 << 5)
	73	#define DMA_AXI_BLEN_128 (1 << 6)
	74	#define DMA_AXI_BLEN_256 (1 << 7)
	75	#define DMA_AXI_BLEN_ALL (DMA_AXI_BLEN_4 \| DMA_AXI_BLEN_8 \| DMA_AXI_BLEN_16 \
	76	\| DMA_AXI_BLEN_32 \| DMA_AXI_BLEN_64 \
	77	\| DMA_AXI_BLEN_128 \| DMA_AXI_BLEN_256)
	78
36bcfe7d GC	79	/* Platfrom data for platform device structure's platform_data field */
	80
	81	struct stmmac_mdio_bus_data {
36bcfe7d	82	unsigned int phy_mask;
f213bbe8	83	unsigned int has_xpcs;
e5e5b771	84	unsigned int xpcs_an_inband;
36bcfe7d GC	85	int *irqs;
36bcfe7d GC	86	int probed_phy_irq;
1a981c05	87	bool needs_reset;
36bcfe7d	88	};
3c9732c0	89
8327eb65 DS	90	struct stmmac_dma_cfg {
8327eb65 DS	91	int pbl;
89caaa2d NC	92	int txpbl;
89caaa2d NC	93	int rxpbl;
4022d039	94	bool pblx8;
8327eb65	95	int fixed_burst;
b9cde0a8	96	int mixed_burst;
afea0365	97	bool aal;
968a2978	98	bool eame;
6ccf12ae	99	bool multi_msi_en;
96874c61	100	bool dche;
afea0365 GC	101	};
	102
	103	#define AXI_BLEN 7
	104	struct stmmac_axi {
	105	bool axi_lpi_en;
	106	bool axi_xit_frm;
	107	u32 axi_wr_osr_lmt;
	108	u32 axi_rd_osr_lmt;
	109	bool axi_kbbe;
afea0365 GC	110	u32 axi_blen[AXI_BLEN];
	111	bool axi_fb;
	112	bool axi_mb;
	113	bool axi_rb;
8327eb65 DS	114	};
8327eb65 DS	115
504723af JA	116	#define EST_GCL 1024
	117	struct stmmac_est {
	118	int enable;
	119	u32 btr_offset[2];
	120	u32 btr[2];
	121	u32 ctr[2];
	122	u32 ter;
	123	u32 gcl_unaligned[EST_GCL];
	124	u32 gcl[EST_GCL];
	125	u32 gcl_size;
	126	};
	127
d976a525 JP	128	struct stmmac_rxq_cfg {
d976a525 JP	129	u8 mode_to_use;
e73b49eb	130	u32 chan;
abe80fdc	131	u8 pkt_route;
a8f5102a JP	132	bool use_prio;
a8f5102a JP	133	u32 prio;
d976a525 JP	134	};
	135
	136	struct stmmac_txq_cfg {
e73b49eb	137	u32 weight;
19d91873 JP	138	u8 mode_to_use;
	139	/* Credit Base Shaper parameters */
	140	u32 send_slope;
	141	u32 idle_slope;
	142	u32 high_credit;
	143	u32 low_credit;
a8f5102a JP	144	bool use_prio;
a8f5102a JP	145	u32 prio;
579a25a8	146	int tbs_en;
d976a525 JP	147	};
d976a525 JP	148
5a558611 OBL	149	/* FPE link state */
	150	enum stmmac_fpe_state {
	151	FPE_STATE_OFF = 0,
	152	FPE_STATE_CAPABLE = 1,
	153	FPE_STATE_ENTERING_ON = 2,
	154	FPE_STATE_ON = 3,
	155	};
	156
	157	/* FPE link-partner hand-shaking mPacket type */
	158	enum stmmac_mpacket_type {
	159	MPACKET_VERIFY = 0,
	160	MPACKET_RESPONSE = 1,
	161	};
	162
	163	enum stmmac_fpe_task_state_t {
	164	__FPE_REMOVING,
	165	__FPE_TASK_SCHED,
	166	};
	167
	168	struct stmmac_fpe_cfg {
	169	bool enable; /* FPE enable */
	170	bool hs_enable; /* FPE handshake enable */
	171	enum stmmac_fpe_state lp_fpe_state; /* Link Partner FPE state */
	172	enum stmmac_fpe_state lo_fpe_state; /* Local station FPE state */
	173	};
	174
3c9732c0 GC	175	struct plat_stmmacenet_data {
3c9732c0 GC	176	int bus_id;
36bcfe7d GC	177	int phy_addr;
36bcfe7d GC	178	int interface;
0c65b2b9	179	phy_interface_t phy_interface;
36bcfe7d	180	struct stmmac_mdio_bus_data *mdio_bus_data;
5790cf3c	181	struct device_node *phy_node;
4838a540	182	struct device_node *phylink_node;
a7657f12	183	struct device_node *mdio_node;
8327eb65	184	struct stmmac_dma_cfg *dma_cfg;
504723af	185	struct stmmac_est *est;
5a558611	186	struct stmmac_fpe_cfg *fpe_cfg;
dfb8fb96	187	int clk_csr;
3c9732c0	188	int has_gmac;
e326e850	189	int enh_desc;
ebbb293f	190	int tx_coe;
55f9a4d6	191	int rx_coe;
ebbb293f	192	int bugged_jumbo;
543876c9	193	int pmt;
61b8013a	194	int force_sf_dma_mode;
e2a240c7	195	int force_thresh_dma_mode;
62a2ab93	196	int riwt_off;
9cbadf09	197	int max_speed;
2618abb7	198	int maxmtu;
3b57de95 VB	199	int multicast_filter_bins;
3b57de95 VB	200	int unicast_filter_entries;
e7877f52 VB	201	int tx_fifo_size;
e7877f52 VB	202	int rx_fifo_size;
f119cc98	203	u32 addr64;
e73b49eb BV	204	u32 rx_queues_to_use;
e73b49eb BV	205	u32 tx_queues_to_use;
d976a525 JP	206	u8 rx_sched_algorithm;
	207	u8 tx_sched_algorithm;
	208	struct stmmac_rxq_cfg rx_queues_cfg[MTL_MAX_RX_QUEUES];
	209	struct stmmac_txq_cfg tx_queues_cfg[MTL_MAX_TX_QUEUES];
3c9732c0	210	void (fix_mac_speed)(void priv, unsigned int speed);
b9663b7c VW	211	int (serdes_powerup)(struct net_device ndev, void *priv);
b9663b7c VW	212	void (serdes_powerdown)(struct net_device ndev, void *priv);
76da35dc	213	void (ptp_clk_freq_config)(void priv);
938dfdaa CYT	214	int (init)(struct platform_device pdev, void *priv);
938dfdaa CYT	215	void (exit)(struct platform_device pdev, void *priv);
ec33d71d	216	struct mac_device_info (setup)(void *priv);
b4d45aee	217	int (clks_config)(void priv, bool enabled);
341f67e4 TTM	218	int (crosststamp)(ktime_t device, struct system_counterval_t *system,
341f67e4 TTM	219	void *ctx);
3c9732c0	220	void *bsp_priv;
f573c0b9	221	struct clk *stmmac_clk;
	222	struct clk *pclk;
	223	struct clk *clk_ptp_ref;
	224	unsigned int clk_ptp_rate;
4ec5302f	225	unsigned int clk_ref_rate;
190f73ab	226	s32 ptp_max_adj;
f573c0b9	227	struct reset_control *stmmac_rst;
afea0365	228	struct stmmac_axi *axi;
ee2ae1ed	229	int has_gmac4;
9f93ac8d	230	bool has_sun8i;
ee2ae1ed	231	bool tso_en;
76067459	232	int rss_en;
02e57b9d	233	int mac_port_sel_speed;
b4b7b772	234	bool en_tx_lpi_clockgating;
48ae5554	235	int has_xgmac;
e0f9956a CKT	236	bool vlan_fail_q_en;
e0f9956a CKT	237	u8 vlan_fail_q;
b4c5f83a	238	unsigned int eee_usecs_rate;
20e07e2c	239	struct pci_dev *pdev;
341f67e4 TTM	240	bool has_crossts;
341f67e4 TTM	241	int int_snapshot_num;
f4da5652 TTM	242	int ext_snapshot_num;
f4da5652 TTM	243	bool ext_snapshot_en;
8532f613 OBL	244	bool multi_msi_en;
	245	int msi_mac_vec;
	246	int msi_wol_vec;
	247	int msi_lpi_vec;
	248	int msi_sfty_ce_vec;
	249	int msi_sfty_ue_vec;
	250	int msi_rx_base_vec;
	251	int msi_tx_base_vec;
3c9732c0	252	};
3c9732c0	253	#endif