[mirror_ubuntu-jammy-kernel.git] / include / linux / stmmac.h

/*******************************************************************************

  Header file for stmmac platform data

  Copyright (C) 2009  STMicroelectronics Ltd

  This program is free software; you can redistribute it and/or modify it
  under the terms and conditions of the GNU General Public License,
  version 2, as published by the Free Software Foundation.

  This program is distributed in the hope it will be useful, but WITHOUT
  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  more details.

  You should have received a copy of the GNU General Public License along with
  this program; if not, write to the Free Software Foundation, Inc.,
  51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.

  The full GNU General Public License is included in this distribution in
  the file called "COPYING".

  Author: Giuseppe Cavallaro <peppe.cavallaro@st.com>
*******************************************************************************/

#ifndef __STMMAC_PLATFORM_DATA
#define __STMMAC_PLATFORM_DATA

#include <linux/platform_device.h>

#define MTL_MAX_RX_QUEUES	8
#define MTL_MAX_TX_QUEUES	8
#define STMMAC_CH_MAX		8

#define STMMAC_RX_COE_NONE	0
#define STMMAC_RX_COE_TYPE1	1
#define STMMAC_RX_COE_TYPE2	2

/* Define the macros for CSR clock range parameters to be passed by
 * platform code.
 * This could also be configured at run time using CPU freq framework. */

/* MDC Clock Selection define*/
#define	STMMAC_CSR_60_100M	0x0	/* MDC = clk_scr_i/42 */
#define	STMMAC_CSR_100_150M	0x1	/* MDC = clk_scr_i/62 */
#define	STMMAC_CSR_20_35M	0x2	/* MDC = clk_scr_i/16 */
#define	STMMAC_CSR_35_60M	0x3	/* MDC = clk_scr_i/26 */
#define	STMMAC_CSR_150_250M	0x4	/* MDC = clk_scr_i/102 */
#define	STMMAC_CSR_250_300M	0x5	/* MDC = clk_scr_i/122 */

/* MTL algorithms identifiers */
#define MTL_TX_ALGORITHM_WRR	0x0
#define MTL_TX_ALGORITHM_WFQ	0x1
#define MTL_TX_ALGORITHM_DWRR	0x2
#define MTL_TX_ALGORITHM_SP	0x3
#define MTL_RX_ALGORITHM_SP	0x4
#define MTL_RX_ALGORITHM_WSP	0x5

/* RX/TX Queue Mode */
#define MTL_QUEUE_AVB		0x0
#define MTL_QUEUE_DCB		0x1

/* The MDC clock could be set higher than the IEEE 802.3
 * specified frequency limit 0f 2.5 MHz, by programming a clock divider
 * of value different than the above defined values. The resultant MDIO
 * clock frequency of 12.5 MHz is applicable for the interfacing chips
 * supporting higher MDC clocks.
 * The MDC clock selection macros need to be defined for MDC clock rate
 * of 12.5 MHz, corresponding to the following selection.
 */
#define STMMAC_CSR_I_4		0x8	/* clk_csr_i/4 */
#define STMMAC_CSR_I_6		0x9	/* clk_csr_i/6 */
#define STMMAC_CSR_I_8		0xA	/* clk_csr_i/8 */
#define STMMAC_CSR_I_10		0xB	/* clk_csr_i/10 */
#define STMMAC_CSR_I_12		0xC	/* clk_csr_i/12 */
#define STMMAC_CSR_I_14		0xD	/* clk_csr_i/14 */
#define STMMAC_CSR_I_16		0xE	/* clk_csr_i/16 */
#define STMMAC_CSR_I_18		0xF	/* clk_csr_i/18 */

/* AXI DMA Burst length supported */
#define DMA_AXI_BLEN_4		(1 << 1)
#define DMA_AXI_BLEN_8		(1 << 2)
#define DMA_AXI_BLEN_16		(1 << 3)
#define DMA_AXI_BLEN_32		(1 << 4)
#define DMA_AXI_BLEN_64		(1 << 5)
#define DMA_AXI_BLEN_128	(1 << 6)
#define DMA_AXI_BLEN_256	(1 << 7)
#define DMA_AXI_BLEN_ALL (DMA_AXI_BLEN_4 | DMA_AXI_BLEN_8 | DMA_AXI_BLEN_16 \
			| DMA_AXI_BLEN_32 | DMA_AXI_BLEN_64 \
			| DMA_AXI_BLEN_128 | DMA_AXI_BLEN_256)

/* Platfrom data for platform device structure's platform_data field */

struct stmmac_mdio_bus_data {
	int (*phy_reset)(void *priv);
	unsigned int phy_mask;
	int *irqs;
	int probed_phy_irq;
#ifdef CONFIG_OF
	int reset_gpio, active_low;
	u32 delays[3];
#endif
};

struct stmmac_dma_cfg {
	int pbl;
	int txpbl;
	int rxpbl;
	bool pblx8;
	int fixed_burst;
	int mixed_burst;
	bool aal;
};

#define AXI_BLEN	7
struct stmmac_axi {
	bool axi_lpi_en;
	bool axi_xit_frm;
	u32 axi_wr_osr_lmt;
	u32 axi_rd_osr_lmt;
	bool axi_kbbe;
	u32 axi_blen[AXI_BLEN];
	bool axi_fb;
	bool axi_mb;
	bool axi_rb;
};

struct stmmac_rxq_cfg {
	u8 mode_to_use;
	u32 chan;
	u8 pkt_route;
	bool use_prio;
	u32 prio;
};

struct stmmac_txq_cfg {
	u32 weight;
	u8 mode_to_use;
	/* Credit Base Shaper parameters */
	u32 send_slope;
	u32 idle_slope;
	u32 high_credit;
	u32 low_credit;
	bool use_prio;
	u32 prio;
};

struct plat_stmmacenet_data {
	int bus_id;
	int phy_addr;
	int interface;
	struct stmmac_mdio_bus_data *mdio_bus_data;
	struct device_node *phy_node;
	struct device_node *mdio_node;
	struct stmmac_dma_cfg *dma_cfg;
	int clk_csr;
	int has_gmac;
	int enh_desc;
	int tx_coe;
	int rx_coe;
	int bugged_jumbo;
	int pmt;
	int force_sf_dma_mode;
	int force_thresh_dma_mode;
	int riwt_off;
	int max_speed;
	int maxmtu;
	int multicast_filter_bins;
	int unicast_filter_entries;
	int tx_fifo_size;
	int rx_fifo_size;
	u32 rx_queues_to_use;
	u32 tx_queues_to_use;
	u8 rx_sched_algorithm;
	u8 tx_sched_algorithm;
	struct stmmac_rxq_cfg rx_queues_cfg[MTL_MAX_RX_QUEUES];
	struct stmmac_txq_cfg tx_queues_cfg[MTL_MAX_TX_QUEUES];
	void (*fix_mac_speed)(void *priv, unsigned int speed);
	int (*init)(struct platform_device *pdev, void *priv);
	void (*exit)(struct platform_device *pdev, void *priv);
	struct mac_device_info *(*setup)(void *priv);
	void *bsp_priv;
	struct clk *stmmac_clk;
	struct clk *pclk;
	struct clk *clk_ptp_ref;
	unsigned int clk_ptp_rate;
	unsigned int clk_ref_rate;
	struct reset_control *stmmac_rst;
	struct stmmac_axi *axi;
	int has_gmac4;
	bool has_sun8i;
	bool tso_en;
	int mac_port_sel_speed;
	bool en_tx_lpi_clockgating;
	int has_xgmac;
};
#endif
Commit	Line	Data
3c9732c0 GC	1	/*******************************************************************************
	2
	3	Header file for stmmac platform data
	4
	5	Copyright (C) 2009 STMicroelectronics Ltd
	6
	7	This program is free software; you can redistribute it and/or modify it
	8	under the terms and conditions of the GNU General Public License,
	9	version 2, as published by the Free Software Foundation.
	10
	11	This program is distributed in the hope it will be useful, but WITHOUT
	12	ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
	13	FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
	14	more details.
	15
	16	You should have received a copy of the GNU General Public License along with
	17	this program; if not, write to the Free Software Foundation, Inc.,
	18	51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
	19
	20	The full GNU General Public License is included in this distribution in
	21	the file called "COPYING".
	22
	23	Author: Giuseppe Cavallaro <peppe.cavallaro@st.com>
	24	*******************************************************************************/
	25
	26	#ifndef __STMMAC_PLATFORM_DATA
	27	#define __STMMAC_PLATFORM_DATA
	28
57a503c6 VK	29	#include <linux/platform_device.h>
57a503c6 VK	30
d976a525 JP	31	#define MTL_MAX_RX_QUEUES 8
d976a525 JP	32	#define MTL_MAX_TX_QUEUES 8
8fce3331	33	#define STMMAC_CH_MAX 8
d976a525	34
55f9a4d6 DS	35	#define STMMAC_RX_COE_NONE 0
	36	#define STMMAC_RX_COE_TYPE1 1
	37	#define STMMAC_RX_COE_TYPE2 2
	38
faeae3fa DS	39	/* Define the macros for CSR clock range parameters to be passed by
	40	* platform code.
	41	* This could also be configured at run time using CPU freq framework. */
	42
	43	/* MDC Clock Selection define*/
18f05d64 GC	44	#define STMMAC_CSR_60_100M 0x0 /* MDC = clk_scr_i/42 */
	45	#define STMMAC_CSR_100_150M 0x1 /* MDC = clk_scr_i/62 */
	46	#define STMMAC_CSR_20_35M 0x2 /* MDC = clk_scr_i/16 */
	47	#define STMMAC_CSR_35_60M 0x3 /* MDC = clk_scr_i/26 */
	48	#define STMMAC_CSR_150_250M 0x4 /* MDC = clk_scr_i/102 */
	49	#define STMMAC_CSR_250_300M 0x5 /* MDC = clk_scr_i/122 */
faeae3fa	50
d976a525 JP	51	/* MTL algorithms identifiers */
	52	#define MTL_TX_ALGORITHM_WRR 0x0
	53	#define MTL_TX_ALGORITHM_WFQ 0x1
	54	#define MTL_TX_ALGORITHM_DWRR 0x2
	55	#define MTL_TX_ALGORITHM_SP 0x3
	56	#define MTL_RX_ALGORITHM_SP 0x4
	57	#define MTL_RX_ALGORITHM_WSP 0x5
	58
19d91873	59	/* RX/TX Queue Mode */
2d72d501 TR	60	#define MTL_QUEUE_AVB 0x0
2d72d501 TR	61	#define MTL_QUEUE_DCB 0x1
d976a525	62
18f05d64	63	/* The MDC clock could be set higher than the IEEE 802.3
faeae3fa DS	64	* specified frequency limit 0f 2.5 MHz, by programming a clock divider
	65	* of value different than the above defined values. The resultant MDIO
	66	* clock frequency of 12.5 MHz is applicable for the interfacing chips
	67	* supporting higher MDC clocks.
	68	* The MDC clock selection macros need to be defined for MDC clock rate
	69	* of 12.5 MHz, corresponding to the following selection.
18f05d64 GC	70	*/
	71	#define STMMAC_CSR_I_4 0x8 /* clk_csr_i/4 */
	72	#define STMMAC_CSR_I_6 0x9 /* clk_csr_i/6 */
	73	#define STMMAC_CSR_I_8 0xA /* clk_csr_i/8 */
	74	#define STMMAC_CSR_I_10 0xB /* clk_csr_i/10 */
	75	#define STMMAC_CSR_I_12 0xC /* clk_csr_i/12 */
	76	#define STMMAC_CSR_I_14 0xD /* clk_csr_i/14 */
	77	#define STMMAC_CSR_I_16 0xE /* clk_csr_i/16 */
	78	#define STMMAC_CSR_I_18 0xF /* clk_csr_i/18 */
faeae3fa	79
02582e9b	80	/* AXI DMA Burst length supported */
8327eb65 DS	81	#define DMA_AXI_BLEN_4 (1 << 1)
	82	#define DMA_AXI_BLEN_8 (1 << 2)
	83	#define DMA_AXI_BLEN_16 (1 << 3)
	84	#define DMA_AXI_BLEN_32 (1 << 4)
	85	#define DMA_AXI_BLEN_64 (1 << 5)
	86	#define DMA_AXI_BLEN_128 (1 << 6)
	87	#define DMA_AXI_BLEN_256 (1 << 7)
	88	#define DMA_AXI_BLEN_ALL (DMA_AXI_BLEN_4 \| DMA_AXI_BLEN_8 \| DMA_AXI_BLEN_16 \
	89	\| DMA_AXI_BLEN_32 \| DMA_AXI_BLEN_64 \
	90	\| DMA_AXI_BLEN_128 \| DMA_AXI_BLEN_256)
	91
36bcfe7d GC	92	/* Platfrom data for platform device structure's platform_data field */
	93
	94	struct stmmac_mdio_bus_data {
36bcfe7d GC	95	int (phy_reset)(void priv);
	96	unsigned int phy_mask;
	97	int *irqs;
	98	int probed_phy_irq;
0e076471 SK	99	#ifdef CONFIG_OF
	100	int reset_gpio, active_low;
	101	u32 delays[3];
	102	#endif
36bcfe7d	103	};
3c9732c0	104
8327eb65 DS	105	struct stmmac_dma_cfg {
8327eb65 DS	106	int pbl;
89caaa2d NC	107	int txpbl;
89caaa2d NC	108	int rxpbl;
4022d039	109	bool pblx8;
8327eb65	110	int fixed_burst;
b9cde0a8	111	int mixed_burst;
afea0365 GC	112	bool aal;
	113	};
	114
	115	#define AXI_BLEN 7
	116	struct stmmac_axi {
	117	bool axi_lpi_en;
	118	bool axi_xit_frm;
	119	u32 axi_wr_osr_lmt;
	120	u32 axi_rd_osr_lmt;
	121	bool axi_kbbe;
afea0365 GC	122	u32 axi_blen[AXI_BLEN];
	123	bool axi_fb;
	124	bool axi_mb;
	125	bool axi_rb;
8327eb65 DS	126	};
8327eb65 DS	127
d976a525 JP	128	struct stmmac_rxq_cfg {
d976a525 JP	129	u8 mode_to_use;
e73b49eb	130	u32 chan;
abe80fdc	131	u8 pkt_route;
a8f5102a JP	132	bool use_prio;
a8f5102a JP	133	u32 prio;
d976a525 JP	134	};
	135
	136	struct stmmac_txq_cfg {
e73b49eb	137	u32 weight;
19d91873 JP	138	u8 mode_to_use;
	139	/* Credit Base Shaper parameters */
	140	u32 send_slope;
	141	u32 idle_slope;
	142	u32 high_credit;
	143	u32 low_credit;
a8f5102a JP	144	bool use_prio;
a8f5102a JP	145	u32 prio;
d976a525 JP	146	};
d976a525 JP	147
3c9732c0 GC	148	struct plat_stmmacenet_data {
3c9732c0 GC	149	int bus_id;
36bcfe7d GC	150	int phy_addr;
	151	int interface;
	152	struct stmmac_mdio_bus_data *mdio_bus_data;
5790cf3c	153	struct device_node *phy_node;
a7657f12	154	struct device_node *mdio_node;
8327eb65	155	struct stmmac_dma_cfg *dma_cfg;
dfb8fb96	156	int clk_csr;
3c9732c0	157	int has_gmac;
e326e850	158	int enh_desc;
ebbb293f	159	int tx_coe;
55f9a4d6	160	int rx_coe;
ebbb293f	161	int bugged_jumbo;
543876c9	162	int pmt;
61b8013a	163	int force_sf_dma_mode;
e2a240c7	164	int force_thresh_dma_mode;
62a2ab93	165	int riwt_off;
9cbadf09	166	int max_speed;
2618abb7	167	int maxmtu;
3b57de95 VB	168	int multicast_filter_bins;
3b57de95 VB	169	int unicast_filter_entries;
e7877f52 VB	170	int tx_fifo_size;
e7877f52 VB	171	int rx_fifo_size;
e73b49eb BV	172	u32 rx_queues_to_use;
e73b49eb BV	173	u32 tx_queues_to_use;
d976a525 JP	174	u8 rx_sched_algorithm;
	175	u8 tx_sched_algorithm;
	176	struct stmmac_rxq_cfg rx_queues_cfg[MTL_MAX_RX_QUEUES];
	177	struct stmmac_txq_cfg tx_queues_cfg[MTL_MAX_TX_QUEUES];
3c9732c0	178	void (fix_mac_speed)(void priv, unsigned int speed);
938dfdaa CYT	179	int (init)(struct platform_device pdev, void *priv);
938dfdaa CYT	180	void (exit)(struct platform_device pdev, void *priv);
ec33d71d	181	struct mac_device_info (setup)(void *priv);
3c9732c0	182	void *bsp_priv;
f573c0b9	183	struct clk *stmmac_clk;
	184	struct clk *pclk;
	185	struct clk *clk_ptp_ref;
	186	unsigned int clk_ptp_rate;
4ec5302f	187	unsigned int clk_ref_rate;
f573c0b9	188	struct reset_control *stmmac_rst;
afea0365	189	struct stmmac_axi *axi;
ee2ae1ed	190	int has_gmac4;
9f93ac8d	191	bool has_sun8i;
ee2ae1ed	192	bool tso_en;
02e57b9d	193	int mac_port_sel_speed;
b4b7b772	194	bool en_tx_lpi_clockgating;
48ae5554	195	int has_xgmac;
3c9732c0	196	};
3c9732c0	197	#endif