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1237a75a | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
3c9732c0 GC |
2 | /******************************************************************************* |
3 | ||
4 | Header file for stmmac platform data | |
5 | ||
6 | Copyright (C) 2009 STMicroelectronics Ltd | |
7 | ||
3c9732c0 GC |
8 | |
9 | Author: Giuseppe Cavallaro <peppe.cavallaro@st.com> | |
10 | *******************************************************************************/ | |
11 | ||
12 | #ifndef __STMMAC_PLATFORM_DATA | |
13 | #define __STMMAC_PLATFORM_DATA | |
14 | ||
57a503c6 | 15 | #include <linux/platform_device.h> |
0c65b2b9 | 16 | #include <linux/phy.h> |
57a503c6 | 17 | |
d976a525 JP |
18 | #define MTL_MAX_RX_QUEUES 8 |
19 | #define MTL_MAX_TX_QUEUES 8 | |
8fce3331 | 20 | #define STMMAC_CH_MAX 8 |
d976a525 | 21 | |
55f9a4d6 DS |
22 | #define STMMAC_RX_COE_NONE 0 |
23 | #define STMMAC_RX_COE_TYPE1 1 | |
24 | #define STMMAC_RX_COE_TYPE2 2 | |
25 | ||
faeae3fa DS |
26 | /* Define the macros for CSR clock range parameters to be passed by |
27 | * platform code. | |
28 | * This could also be configured at run time using CPU freq framework. */ | |
29 | ||
30 | /* MDC Clock Selection define*/ | |
18f05d64 GC |
31 | #define STMMAC_CSR_60_100M 0x0 /* MDC = clk_scr_i/42 */ |
32 | #define STMMAC_CSR_100_150M 0x1 /* MDC = clk_scr_i/62 */ | |
33 | #define STMMAC_CSR_20_35M 0x2 /* MDC = clk_scr_i/16 */ | |
34 | #define STMMAC_CSR_35_60M 0x3 /* MDC = clk_scr_i/26 */ | |
35 | #define STMMAC_CSR_150_250M 0x4 /* MDC = clk_scr_i/102 */ | |
36 | #define STMMAC_CSR_250_300M 0x5 /* MDC = clk_scr_i/122 */ | |
faeae3fa | 37 | |
d976a525 JP |
38 | /* MTL algorithms identifiers */ |
39 | #define MTL_TX_ALGORITHM_WRR 0x0 | |
40 | #define MTL_TX_ALGORITHM_WFQ 0x1 | |
41 | #define MTL_TX_ALGORITHM_DWRR 0x2 | |
42 | #define MTL_TX_ALGORITHM_SP 0x3 | |
43 | #define MTL_RX_ALGORITHM_SP 0x4 | |
44 | #define MTL_RX_ALGORITHM_WSP 0x5 | |
45 | ||
19d91873 | 46 | /* RX/TX Queue Mode */ |
2d72d501 TR |
47 | #define MTL_QUEUE_AVB 0x0 |
48 | #define MTL_QUEUE_DCB 0x1 | |
d976a525 | 49 | |
18f05d64 | 50 | /* The MDC clock could be set higher than the IEEE 802.3 |
faeae3fa DS |
51 | * specified frequency limit 0f 2.5 MHz, by programming a clock divider |
52 | * of value different than the above defined values. The resultant MDIO | |
53 | * clock frequency of 12.5 MHz is applicable for the interfacing chips | |
54 | * supporting higher MDC clocks. | |
55 | * The MDC clock selection macros need to be defined for MDC clock rate | |
56 | * of 12.5 MHz, corresponding to the following selection. | |
18f05d64 GC |
57 | */ |
58 | #define STMMAC_CSR_I_4 0x8 /* clk_csr_i/4 */ | |
59 | #define STMMAC_CSR_I_6 0x9 /* clk_csr_i/6 */ | |
60 | #define STMMAC_CSR_I_8 0xA /* clk_csr_i/8 */ | |
61 | #define STMMAC_CSR_I_10 0xB /* clk_csr_i/10 */ | |
62 | #define STMMAC_CSR_I_12 0xC /* clk_csr_i/12 */ | |
63 | #define STMMAC_CSR_I_14 0xD /* clk_csr_i/14 */ | |
64 | #define STMMAC_CSR_I_16 0xE /* clk_csr_i/16 */ | |
65 | #define STMMAC_CSR_I_18 0xF /* clk_csr_i/18 */ | |
faeae3fa | 66 | |
02582e9b | 67 | /* AXI DMA Burst length supported */ |
8327eb65 DS |
68 | #define DMA_AXI_BLEN_4 (1 << 1) |
69 | #define DMA_AXI_BLEN_8 (1 << 2) | |
70 | #define DMA_AXI_BLEN_16 (1 << 3) | |
71 | #define DMA_AXI_BLEN_32 (1 << 4) | |
72 | #define DMA_AXI_BLEN_64 (1 << 5) | |
73 | #define DMA_AXI_BLEN_128 (1 << 6) | |
74 | #define DMA_AXI_BLEN_256 (1 << 7) | |
75 | #define DMA_AXI_BLEN_ALL (DMA_AXI_BLEN_4 | DMA_AXI_BLEN_8 | DMA_AXI_BLEN_16 \ | |
76 | | DMA_AXI_BLEN_32 | DMA_AXI_BLEN_64 \ | |
77 | | DMA_AXI_BLEN_128 | DMA_AXI_BLEN_256) | |
78 | ||
36bcfe7d GC |
79 | /* Platfrom data for platform device structure's platform_data field */ |
80 | ||
81 | struct stmmac_mdio_bus_data { | |
36bcfe7d | 82 | unsigned int phy_mask; |
f213bbe8 | 83 | unsigned int has_xpcs; |
36bcfe7d GC |
84 | int *irqs; |
85 | int probed_phy_irq; | |
1a981c05 | 86 | bool needs_reset; |
36bcfe7d | 87 | }; |
3c9732c0 | 88 | |
8327eb65 DS |
89 | struct stmmac_dma_cfg { |
90 | int pbl; | |
89caaa2d NC |
91 | int txpbl; |
92 | int rxpbl; | |
4022d039 | 93 | bool pblx8; |
8327eb65 | 94 | int fixed_burst; |
b9cde0a8 | 95 | int mixed_burst; |
afea0365 | 96 | bool aal; |
968a2978 | 97 | bool eame; |
afea0365 GC |
98 | }; |
99 | ||
100 | #define AXI_BLEN 7 | |
101 | struct stmmac_axi { | |
102 | bool axi_lpi_en; | |
103 | bool axi_xit_frm; | |
104 | u32 axi_wr_osr_lmt; | |
105 | u32 axi_rd_osr_lmt; | |
106 | bool axi_kbbe; | |
afea0365 GC |
107 | u32 axi_blen[AXI_BLEN]; |
108 | bool axi_fb; | |
109 | bool axi_mb; | |
110 | bool axi_rb; | |
8327eb65 DS |
111 | }; |
112 | ||
504723af JA |
113 | #define EST_GCL 1024 |
114 | struct stmmac_est { | |
115 | int enable; | |
116 | u32 btr_offset[2]; | |
117 | u32 btr[2]; | |
118 | u32 ctr[2]; | |
119 | u32 ter; | |
120 | u32 gcl_unaligned[EST_GCL]; | |
121 | u32 gcl[EST_GCL]; | |
122 | u32 gcl_size; | |
123 | }; | |
124 | ||
d976a525 JP |
125 | struct stmmac_rxq_cfg { |
126 | u8 mode_to_use; | |
e73b49eb | 127 | u32 chan; |
abe80fdc | 128 | u8 pkt_route; |
a8f5102a JP |
129 | bool use_prio; |
130 | u32 prio; | |
d976a525 JP |
131 | }; |
132 | ||
133 | struct stmmac_txq_cfg { | |
e73b49eb | 134 | u32 weight; |
19d91873 JP |
135 | u8 mode_to_use; |
136 | /* Credit Base Shaper parameters */ | |
137 | u32 send_slope; | |
138 | u32 idle_slope; | |
139 | u32 high_credit; | |
140 | u32 low_credit; | |
a8f5102a JP |
141 | bool use_prio; |
142 | u32 prio; | |
579a25a8 | 143 | int tbs_en; |
d976a525 JP |
144 | }; |
145 | ||
3c9732c0 GC |
146 | struct plat_stmmacenet_data { |
147 | int bus_id; | |
36bcfe7d GC |
148 | int phy_addr; |
149 | int interface; | |
0c65b2b9 | 150 | phy_interface_t phy_interface; |
36bcfe7d | 151 | struct stmmac_mdio_bus_data *mdio_bus_data; |
5790cf3c | 152 | struct device_node *phy_node; |
4838a540 | 153 | struct device_node *phylink_node; |
a7657f12 | 154 | struct device_node *mdio_node; |
8327eb65 | 155 | struct stmmac_dma_cfg *dma_cfg; |
504723af | 156 | struct stmmac_est *est; |
dfb8fb96 | 157 | int clk_csr; |
3c9732c0 | 158 | int has_gmac; |
e326e850 | 159 | int enh_desc; |
ebbb293f | 160 | int tx_coe; |
55f9a4d6 | 161 | int rx_coe; |
ebbb293f | 162 | int bugged_jumbo; |
543876c9 | 163 | int pmt; |
61b8013a | 164 | int force_sf_dma_mode; |
e2a240c7 | 165 | int force_thresh_dma_mode; |
62a2ab93 | 166 | int riwt_off; |
9cbadf09 | 167 | int max_speed; |
2618abb7 | 168 | int maxmtu; |
3b57de95 VB |
169 | int multicast_filter_bins; |
170 | int unicast_filter_entries; | |
e7877f52 VB |
171 | int tx_fifo_size; |
172 | int rx_fifo_size; | |
e73b49eb BV |
173 | u32 rx_queues_to_use; |
174 | u32 tx_queues_to_use; | |
d976a525 JP |
175 | u8 rx_sched_algorithm; |
176 | u8 tx_sched_algorithm; | |
177 | struct stmmac_rxq_cfg rx_queues_cfg[MTL_MAX_RX_QUEUES]; | |
178 | struct stmmac_txq_cfg tx_queues_cfg[MTL_MAX_TX_QUEUES]; | |
3c9732c0 | 179 | void (*fix_mac_speed)(void *priv, unsigned int speed); |
b9663b7c VW |
180 | int (*serdes_powerup)(struct net_device *ndev, void *priv); |
181 | void (*serdes_powerdown)(struct net_device *ndev, void *priv); | |
938dfdaa CYT |
182 | int (*init)(struct platform_device *pdev, void *priv); |
183 | void (*exit)(struct platform_device *pdev, void *priv); | |
ec33d71d | 184 | struct mac_device_info *(*setup)(void *priv); |
3c9732c0 | 185 | void *bsp_priv; |
f573c0b9 | 186 | struct clk *stmmac_clk; |
187 | struct clk *pclk; | |
188 | struct clk *clk_ptp_ref; | |
189 | unsigned int clk_ptp_rate; | |
4ec5302f | 190 | unsigned int clk_ref_rate; |
190f73ab | 191 | s32 ptp_max_adj; |
f573c0b9 | 192 | struct reset_control *stmmac_rst; |
afea0365 | 193 | struct stmmac_axi *axi; |
ee2ae1ed | 194 | int has_gmac4; |
9f93ac8d | 195 | bool has_sun8i; |
ee2ae1ed | 196 | bool tso_en; |
76067459 | 197 | int rss_en; |
02e57b9d | 198 | int mac_port_sel_speed; |
b4b7b772 | 199 | bool en_tx_lpi_clockgating; |
48ae5554 | 200 | int has_xgmac; |
3c9732c0 | 201 | }; |
3c9732c0 | 202 | #endif |