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3c9732c0 GC |
1 | /******************************************************************************* |
2 | ||
3 | Header file for stmmac platform data | |
4 | ||
5 | Copyright (C) 2009 STMicroelectronics Ltd | |
6 | ||
7 | This program is free software; you can redistribute it and/or modify it | |
8 | under the terms and conditions of the GNU General Public License, | |
9 | version 2, as published by the Free Software Foundation. | |
10 | ||
11 | This program is distributed in the hope it will be useful, but WITHOUT | |
12 | ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
13 | FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
14 | more details. | |
15 | ||
16 | You should have received a copy of the GNU General Public License along with | |
17 | this program; if not, write to the Free Software Foundation, Inc., | |
18 | 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. | |
19 | ||
20 | The full GNU General Public License is included in this distribution in | |
21 | the file called "COPYING". | |
22 | ||
23 | Author: Giuseppe Cavallaro <peppe.cavallaro@st.com> | |
24 | *******************************************************************************/ | |
25 | ||
26 | #ifndef __STMMAC_PLATFORM_DATA | |
27 | #define __STMMAC_PLATFORM_DATA | |
28 | ||
57a503c6 VK |
29 | #include <linux/platform_device.h> |
30 | ||
d976a525 JP |
31 | #define MTL_MAX_RX_QUEUES 8 |
32 | #define MTL_MAX_TX_QUEUES 8 | |
33 | ||
55f9a4d6 DS |
34 | #define STMMAC_RX_COE_NONE 0 |
35 | #define STMMAC_RX_COE_TYPE1 1 | |
36 | #define STMMAC_RX_COE_TYPE2 2 | |
37 | ||
faeae3fa DS |
38 | /* Define the macros for CSR clock range parameters to be passed by |
39 | * platform code. | |
40 | * This could also be configured at run time using CPU freq framework. */ | |
41 | ||
42 | /* MDC Clock Selection define*/ | |
18f05d64 GC |
43 | #define STMMAC_CSR_60_100M 0x0 /* MDC = clk_scr_i/42 */ |
44 | #define STMMAC_CSR_100_150M 0x1 /* MDC = clk_scr_i/62 */ | |
45 | #define STMMAC_CSR_20_35M 0x2 /* MDC = clk_scr_i/16 */ | |
46 | #define STMMAC_CSR_35_60M 0x3 /* MDC = clk_scr_i/26 */ | |
47 | #define STMMAC_CSR_150_250M 0x4 /* MDC = clk_scr_i/102 */ | |
48 | #define STMMAC_CSR_250_300M 0x5 /* MDC = clk_scr_i/122 */ | |
faeae3fa | 49 | |
d976a525 JP |
50 | /* MTL algorithms identifiers */ |
51 | #define MTL_TX_ALGORITHM_WRR 0x0 | |
52 | #define MTL_TX_ALGORITHM_WFQ 0x1 | |
53 | #define MTL_TX_ALGORITHM_DWRR 0x2 | |
54 | #define MTL_TX_ALGORITHM_SP 0x3 | |
55 | #define MTL_RX_ALGORITHM_SP 0x4 | |
56 | #define MTL_RX_ALGORITHM_WSP 0x5 | |
57 | ||
58 | /* RX Queue Mode */ | |
59 | #define MTL_RX_DCB 0x0 | |
60 | #define MTL_RX_AVB 0x1 | |
61 | ||
18f05d64 | 62 | /* The MDC clock could be set higher than the IEEE 802.3 |
faeae3fa DS |
63 | * specified frequency limit 0f 2.5 MHz, by programming a clock divider |
64 | * of value different than the above defined values. The resultant MDIO | |
65 | * clock frequency of 12.5 MHz is applicable for the interfacing chips | |
66 | * supporting higher MDC clocks. | |
67 | * The MDC clock selection macros need to be defined for MDC clock rate | |
68 | * of 12.5 MHz, corresponding to the following selection. | |
18f05d64 GC |
69 | */ |
70 | #define STMMAC_CSR_I_4 0x8 /* clk_csr_i/4 */ | |
71 | #define STMMAC_CSR_I_6 0x9 /* clk_csr_i/6 */ | |
72 | #define STMMAC_CSR_I_8 0xA /* clk_csr_i/8 */ | |
73 | #define STMMAC_CSR_I_10 0xB /* clk_csr_i/10 */ | |
74 | #define STMMAC_CSR_I_12 0xC /* clk_csr_i/12 */ | |
75 | #define STMMAC_CSR_I_14 0xD /* clk_csr_i/14 */ | |
76 | #define STMMAC_CSR_I_16 0xE /* clk_csr_i/16 */ | |
77 | #define STMMAC_CSR_I_18 0xF /* clk_csr_i/18 */ | |
faeae3fa | 78 | |
02582e9b | 79 | /* AXI DMA Burst length supported */ |
8327eb65 DS |
80 | #define DMA_AXI_BLEN_4 (1 << 1) |
81 | #define DMA_AXI_BLEN_8 (1 << 2) | |
82 | #define DMA_AXI_BLEN_16 (1 << 3) | |
83 | #define DMA_AXI_BLEN_32 (1 << 4) | |
84 | #define DMA_AXI_BLEN_64 (1 << 5) | |
85 | #define DMA_AXI_BLEN_128 (1 << 6) | |
86 | #define DMA_AXI_BLEN_256 (1 << 7) | |
87 | #define DMA_AXI_BLEN_ALL (DMA_AXI_BLEN_4 | DMA_AXI_BLEN_8 | DMA_AXI_BLEN_16 \ | |
88 | | DMA_AXI_BLEN_32 | DMA_AXI_BLEN_64 \ | |
89 | | DMA_AXI_BLEN_128 | DMA_AXI_BLEN_256) | |
90 | ||
36bcfe7d GC |
91 | /* Platfrom data for platform device structure's platform_data field */ |
92 | ||
93 | struct stmmac_mdio_bus_data { | |
36bcfe7d GC |
94 | int (*phy_reset)(void *priv); |
95 | unsigned int phy_mask; | |
96 | int *irqs; | |
97 | int probed_phy_irq; | |
0e076471 SK |
98 | #ifdef CONFIG_OF |
99 | int reset_gpio, active_low; | |
100 | u32 delays[3]; | |
101 | #endif | |
36bcfe7d | 102 | }; |
3c9732c0 | 103 | |
8327eb65 DS |
104 | struct stmmac_dma_cfg { |
105 | int pbl; | |
89caaa2d NC |
106 | int txpbl; |
107 | int rxpbl; | |
4022d039 | 108 | bool pblx8; |
8327eb65 | 109 | int fixed_burst; |
b9cde0a8 | 110 | int mixed_burst; |
afea0365 GC |
111 | bool aal; |
112 | }; | |
113 | ||
114 | #define AXI_BLEN 7 | |
115 | struct stmmac_axi { | |
116 | bool axi_lpi_en; | |
117 | bool axi_xit_frm; | |
118 | u32 axi_wr_osr_lmt; | |
119 | u32 axi_rd_osr_lmt; | |
120 | bool axi_kbbe; | |
afea0365 GC |
121 | u32 axi_blen[AXI_BLEN]; |
122 | bool axi_fb; | |
123 | bool axi_mb; | |
124 | bool axi_rb; | |
8327eb65 DS |
125 | }; |
126 | ||
d976a525 JP |
127 | struct stmmac_rxq_cfg { |
128 | u8 mode_to_use; | |
129 | u8 chan; | |
130 | }; | |
131 | ||
132 | struct stmmac_txq_cfg { | |
133 | u8 weight; | |
134 | }; | |
135 | ||
3c9732c0 GC |
136 | struct plat_stmmacenet_data { |
137 | int bus_id; | |
36bcfe7d GC |
138 | int phy_addr; |
139 | int interface; | |
140 | struct stmmac_mdio_bus_data *mdio_bus_data; | |
5790cf3c | 141 | struct device_node *phy_node; |
a7657f12 | 142 | struct device_node *mdio_node; |
8327eb65 | 143 | struct stmmac_dma_cfg *dma_cfg; |
dfb8fb96 | 144 | int clk_csr; |
3c9732c0 | 145 | int has_gmac; |
e326e850 | 146 | int enh_desc; |
ebbb293f | 147 | int tx_coe; |
55f9a4d6 | 148 | int rx_coe; |
ebbb293f | 149 | int bugged_jumbo; |
543876c9 | 150 | int pmt; |
61b8013a | 151 | int force_sf_dma_mode; |
e2a240c7 | 152 | int force_thresh_dma_mode; |
62a2ab93 | 153 | int riwt_off; |
9cbadf09 | 154 | int max_speed; |
2618abb7 | 155 | int maxmtu; |
3b57de95 VB |
156 | int multicast_filter_bins; |
157 | int unicast_filter_entries; | |
e7877f52 VB |
158 | int tx_fifo_size; |
159 | int rx_fifo_size; | |
d976a525 JP |
160 | u8 rx_queues_to_use; |
161 | u8 tx_queues_to_use; | |
162 | u8 rx_sched_algorithm; | |
163 | u8 tx_sched_algorithm; | |
164 | struct stmmac_rxq_cfg rx_queues_cfg[MTL_MAX_RX_QUEUES]; | |
165 | struct stmmac_txq_cfg tx_queues_cfg[MTL_MAX_TX_QUEUES]; | |
3c9732c0 | 166 | void (*fix_mac_speed)(void *priv, unsigned int speed); |
938dfdaa CYT |
167 | int (*init)(struct platform_device *pdev, void *priv); |
168 | void (*exit)(struct platform_device *pdev, void *priv); | |
3c9732c0 | 169 | void *bsp_priv; |
f573c0b9 | 170 | struct clk *stmmac_clk; |
171 | struct clk *pclk; | |
172 | struct clk *clk_ptp_ref; | |
173 | unsigned int clk_ptp_rate; | |
174 | struct reset_control *stmmac_rst; | |
afea0365 | 175 | struct stmmac_axi *axi; |
ee2ae1ed AT |
176 | int has_gmac4; |
177 | bool tso_en; | |
02e57b9d | 178 | int mac_port_sel_speed; |
b4b7b772 | 179 | bool en_tx_lpi_clockgating; |
3c9732c0 | 180 | }; |
3c9732c0 | 181 | #endif |