projects / mirror_ubuntu-artful-kernel.git / blame
| Commit | Line | Data |
|---|---|---|
| 1da177e4 LT |
1 | /* |
| 2 | * SyncLink Multiprotocol Serial Adapter Driver | |
| 3 | * | |
| cb10dc9a | 4 | * $Id: synclink.h,v 3.14 2006/07/17 20:15:43 paulkf Exp $ |
| 1da177e4 LT |
5 | * |
| 6 | * Copyright (C) 1998-2000 by Microgate Corporation | |
| 7 | * | |
| 8 | * Redistribution of this file is permitted under | |
| 9 | * the terms of the GNU Public License (GPL) | |
| 10 | */ | |
| 11 | ||
| 12 | #ifndef _SYNCLINK_H_ | |
| 13 | #define _SYNCLINK_H_ | |
| 14 | #define SYNCLINK_H_VERSION 3.6 | |
| 15 | ||
| 1da177e4 LT |
16 | #define BIT0 0x0001 |
| 17 | #define BIT1 0x0002 | |
| 18 | #define BIT2 0x0004 | |
| 19 | #define BIT3 0x0008 | |
| 20 | #define BIT4 0x0010 | |
| 21 | #define BIT5 0x0020 | |
| 22 | #define BIT6 0x0040 | |
| 23 | #define BIT7 0x0080 | |
| 24 | #define BIT8 0x0100 | |
| 25 | #define BIT9 0x0200 | |
| 26 | #define BIT10 0x0400 | |
| 27 | #define BIT11 0x0800 | |
| 28 | #define BIT12 0x1000 | |
| 29 | #define BIT13 0x2000 | |
| 30 | #define BIT14 0x4000 | |
| 31 | #define BIT15 0x8000 | |
| 32 | #define BIT16 0x00010000 | |
| 33 | #define BIT17 0x00020000 | |
| 34 | #define BIT18 0x00040000 | |
| 35 | #define BIT19 0x00080000 | |
| 36 | #define BIT20 0x00100000 | |
| 37 | #define BIT21 0x00200000 | |
| 38 | #define BIT22 0x00400000 | |
| 39 | #define BIT23 0x00800000 | |
| 40 | #define BIT24 0x01000000 | |
| 41 | #define BIT25 0x02000000 | |
| 42 | #define BIT26 0x04000000 | |
| 43 | #define BIT27 0x08000000 | |
| 44 | #define BIT28 0x10000000 | |
| 45 | #define BIT29 0x20000000 | |
| 46 | #define BIT30 0x40000000 | |
| 47 | #define BIT31 0x80000000 | |
| 48 | ||
| 49 | ||
| 50 | #define HDLC_MAX_FRAME_SIZE 65535 | |
| 51 | #define MAX_ASYNC_TRANSMIT 4096 | |
| 52 | #define MAX_ASYNC_BUFFER_SIZE 4096 | |
| 53 | ||
| 54 | #define ASYNC_PARITY_NONE 0 | |
| 55 | #define ASYNC_PARITY_EVEN 1 | |
| 56 | #define ASYNC_PARITY_ODD 2 | |
| 57 | #define ASYNC_PARITY_SPACE 3 | |
| 58 | ||
| 59 | #define HDLC_FLAG_UNDERRUN_ABORT7 0x0000 | |
| 60 | #define HDLC_FLAG_UNDERRUN_ABORT15 0x0001 | |
| 61 | #define HDLC_FLAG_UNDERRUN_FLAG 0x0002 | |
| 62 | #define HDLC_FLAG_UNDERRUN_CRC 0x0004 | |
| 63 | #define HDLC_FLAG_SHARE_ZERO 0x0010 | |
| 64 | #define HDLC_FLAG_AUTO_CTS 0x0020 | |
| 65 | #define HDLC_FLAG_AUTO_DCD 0x0040 | |
| 66 | #define HDLC_FLAG_AUTO_RTS 0x0080 | |
| 67 | #define HDLC_FLAG_RXC_DPLL 0x0100 | |
| 68 | #define HDLC_FLAG_RXC_BRG 0x0200 | |
| 69 | #define HDLC_FLAG_RXC_TXCPIN 0x8000 | |
| 70 | #define HDLC_FLAG_RXC_RXCPIN 0x0000 | |
| 71 | #define HDLC_FLAG_TXC_DPLL 0x0400 | |
| 72 | #define HDLC_FLAG_TXC_BRG 0x0800 | |
| 73 | #define HDLC_FLAG_TXC_TXCPIN 0x0000 | |
| 74 | #define HDLC_FLAG_TXC_RXCPIN 0x0008 | |
| 75 | #define HDLC_FLAG_DPLL_DIV8 0x1000 | |
| 76 | #define HDLC_FLAG_DPLL_DIV16 0x2000 | |
| 77 | #define HDLC_FLAG_DPLL_DIV32 0x0000 | |
| 78 | #define HDLC_FLAG_HDLC_LOOPMODE 0x4000 | |
| 79 | ||
| 80 | #define HDLC_CRC_NONE 0 | |
| 81 | #define HDLC_CRC_16_CCITT 1 | |
| 82 | #define HDLC_CRC_32_CCITT 2 | |
| 83 | #define HDLC_CRC_MASK 0x00ff | |
| 84 | #define HDLC_CRC_RETURN_EX 0x8000 | |
| 85 | ||
| 86 | #define RX_OK 0 | |
| 87 | #define RX_CRC_ERROR 1 | |
| 88 | ||
| 89 | #define HDLC_TXIDLE_FLAGS 0 | |
| 90 | #define HDLC_TXIDLE_ALT_ZEROS_ONES 1 | |
| 91 | #define HDLC_TXIDLE_ZEROS 2 | |
| 92 | #define HDLC_TXIDLE_ONES 3 | |
| 93 | #define HDLC_TXIDLE_ALT_MARK_SPACE 4 | |
| 94 | #define HDLC_TXIDLE_SPACE 5 | |
| 95 | #define HDLC_TXIDLE_MARK 6 | |
| 643f3319 PF |
96 | #define HDLC_TXIDLE_CUSTOM_8 0x10000000 |
| 97 | #define HDLC_TXIDLE_CUSTOM_16 0x20000000 | |
| 1da177e4 LT |
98 | |
| 99 | #define HDLC_ENCODING_NRZ 0 | |
| 100 | #define HDLC_ENCODING_NRZB 1 | |
| 101 | #define HDLC_ENCODING_NRZI_MARK 2 | |
| 102 | #define HDLC_ENCODING_NRZI_SPACE 3 | |
| 103 | #define HDLC_ENCODING_NRZI HDLC_ENCODING_NRZI_SPACE | |
| 104 | #define HDLC_ENCODING_BIPHASE_MARK 4 | |
| 105 | #define HDLC_ENCODING_BIPHASE_SPACE 5 | |
| 106 | #define HDLC_ENCODING_BIPHASE_LEVEL 6 | |
| 107 | #define HDLC_ENCODING_DIFF_BIPHASE_LEVEL 7 | |
| 108 | ||
| 109 | #define HDLC_PREAMBLE_LENGTH_8BITS 0 | |
| 110 | #define HDLC_PREAMBLE_LENGTH_16BITS 1 | |
| 111 | #define HDLC_PREAMBLE_LENGTH_32BITS 2 | |
| 112 | #define HDLC_PREAMBLE_LENGTH_64BITS 3 | |
| 113 | ||
| 114 | #define HDLC_PREAMBLE_PATTERN_NONE 0 | |
| 115 | #define HDLC_PREAMBLE_PATTERN_ZEROS 1 | |
| 116 | #define HDLC_PREAMBLE_PATTERN_FLAGS 2 | |
| 117 | #define HDLC_PREAMBLE_PATTERN_10 3 | |
| 118 | #define HDLC_PREAMBLE_PATTERN_01 4 | |
| 119 | #define HDLC_PREAMBLE_PATTERN_ONES 5 | |
| 120 | ||
| 121 | #define MGSL_MODE_ASYNC 1 | |
| 122 | #define MGSL_MODE_HDLC 2 | |
| cb10dc9a PF |
123 | #define MGSL_MODE_MONOSYNC 3 |
| 124 | #define MGSL_MODE_BISYNC 4 | |
| 1da177e4 LT |
125 | #define MGSL_MODE_RAW 6 |
| 126 | ||
| 127 | #define MGSL_BUS_TYPE_ISA 1 | |
| 128 | #define MGSL_BUS_TYPE_EISA 2 | |
| 129 | #define MGSL_BUS_TYPE_PCI 5 | |
| 130 | ||
| 705b6c7b | 131 | #define MGSL_INTERFACE_MASK 0xf |
| 1da177e4 LT |
132 | #define MGSL_INTERFACE_DISABLE 0 |
| 133 | #define MGSL_INTERFACE_RS232 1 | |
| 134 | #define MGSL_INTERFACE_V35 2 | |
| 135 | #define MGSL_INTERFACE_RS422 3 | |
| 705b6c7b PF |
136 | #define MGSL_INTERFACE_RTS_EN 0x10 |
| 137 | #define MGSL_INTERFACE_LL 0x20 | |
| 138 | #define MGSL_INTERFACE_RL 0x40 | |
| e5590717 | 139 | #define MGSL_INTERFACE_MSB_FIRST 0x80 |
| 1da177e4 LT |
140 | |
| 141 | typedef struct _MGSL_PARAMS | |
| 142 | { | |
| 143 | /* Common */ | |
| 144 | ||
| 145 | unsigned long mode; /* Asynchronous or HDLC */ | |
| 146 | unsigned char loopback; /* internal loopback mode */ | |
| 147 | ||
| 148 | /* HDLC Only */ | |
| 149 | ||
| 150 | unsigned short flags; | |
| 151 | unsigned char encoding; /* NRZ, NRZI, etc. */ | |
| 152 | unsigned long clock_speed; /* external clock speed in bits per second */ | |
| 153 | unsigned char addr_filter; /* receive HDLC address filter, 0xFF = disable */ | |
| 154 | unsigned short crc_type; /* None, CRC16-CCITT, or CRC32-CCITT */ | |
| 155 | unsigned char preamble_length; | |
| 156 | unsigned char preamble; | |
| 157 | ||
| 158 | /* Async Only */ | |
| 159 | ||
| 160 | unsigned long data_rate; /* bits per second */ | |
| 161 | unsigned char data_bits; /* 7 or 8 data bits */ | |
| 162 | unsigned char stop_bits; /* 1 or 2 stop bits */ | |
| 163 | unsigned char parity; /* none, even, or odd */ | |
| 164 | ||
| 165 | } MGSL_PARAMS, *PMGSL_PARAMS; | |
| 166 | ||
| 167 | #define MICROGATE_VENDOR_ID 0x13c0 | |
| 168 | #define SYNCLINK_DEVICE_ID 0x0010 | |
| 169 | #define MGSCC_DEVICE_ID 0x0020 | |
| 170 | #define SYNCLINK_SCA_DEVICE_ID 0x0030 | |
| 705b6c7b PF |
171 | #define SYNCLINK_GT_DEVICE_ID 0x0070 |
| 172 | #define SYNCLINK_GT4_DEVICE_ID 0x0080 | |
| 173 | #define SYNCLINK_AC_DEVICE_ID 0x0090 | |
| 6f84be84 | 174 | #define SYNCLINK_GT2_DEVICE_ID 0x00A0 |
| 1da177e4 LT |
175 | #define MGSL_MAX_SERIAL_NUMBER 30 |
| 176 | ||
| 177 | /* | |
| 178 | ** device diagnostics status | |
| 179 | */ | |
| 180 | ||
| 181 | #define DiagStatus_OK 0 | |
| 182 | #define DiagStatus_AddressFailure 1 | |
| 183 | #define DiagStatus_AddressConflict 2 | |
| 184 | #define DiagStatus_IrqFailure 3 | |
| 185 | #define DiagStatus_IrqConflict 4 | |
| 186 | #define DiagStatus_DmaFailure 5 | |
| 187 | #define DiagStatus_DmaConflict 6 | |
| 188 | #define DiagStatus_PciAdapterNotFound 7 | |
| 189 | #define DiagStatus_CantAssignPciResources 8 | |
| 190 | #define DiagStatus_CantAssignPciMemAddr 9 | |
| 191 | #define DiagStatus_CantAssignPciIoAddr 10 | |
| 192 | #define DiagStatus_CantAssignPciIrq 11 | |
| 193 | #define DiagStatus_MemoryError 12 | |
| 194 | ||
| 195 | #define SerialSignal_DCD 0x01 /* Data Carrier Detect */ | |
| 196 | #define SerialSignal_TXD 0x02 /* Transmit Data */ | |
| 197 | #define SerialSignal_RI 0x04 /* Ring Indicator */ | |
| 198 | #define SerialSignal_RXD 0x08 /* Receive Data */ | |
| 199 | #define SerialSignal_CTS 0x10 /* Clear to Send */ | |
| 200 | #define SerialSignal_RTS 0x20 /* Request to Send */ | |
| 201 | #define SerialSignal_DSR 0x40 /* Data Set Ready */ | |
| 202 | #define SerialSignal_DTR 0x80 /* Data Terminal Ready */ | |
| 203 | ||
| 204 | ||
| 205 | /* | |
| 206 | * Counters of the input lines (CTS, DSR, RI, CD) interrupts | |
| 207 | */ | |
| 208 | struct mgsl_icount { | |
| 209 | __u32 cts, dsr, rng, dcd, tx, rx; | |
| 210 | __u32 frame, parity, overrun, brk; | |
| 211 | __u32 buf_overrun; | |
| 212 | __u32 txok; | |
| 213 | __u32 txunder; | |
| 214 | __u32 txabort; | |
| 215 | __u32 txtimeout; | |
| 216 | __u32 rxshort; | |
| 217 | __u32 rxlong; | |
| 218 | __u32 rxabort; | |
| 219 | __u32 rxover; | |
| 220 | __u32 rxcrc; | |
| 221 | __u32 rxok; | |
| 222 | __u32 exithunt; | |
| 223 | __u32 rxidle; | |
| 224 | }; | |
| 225 | ||
| 0080b7aa PF |
226 | struct gpio_desc { |
| 227 | __u32 state; | |
| 228 | __u32 smask; | |
| 229 | __u32 dir; | |
| 230 | __u32 dmask; | |
| 231 | }; | |
| 1da177e4 LT |
232 | |
| 233 | #define DEBUG_LEVEL_DATA 1 | |
| 234 | #define DEBUG_LEVEL_ERROR 2 | |
| 235 | #define DEBUG_LEVEL_INFO 3 | |
| 236 | #define DEBUG_LEVEL_BH 4 | |
| 237 | #define DEBUG_LEVEL_ISR 5 | |
| 238 | ||
| 239 | /* | |
| 240 | ** Event bit flags for use with MgslWaitEvent | |
| 241 | */ | |
| 242 | ||
| 243 | #define MgslEvent_DsrActive 0x0001 | |
| 244 | #define MgslEvent_DsrInactive 0x0002 | |
| 245 | #define MgslEvent_Dsr 0x0003 | |
| 246 | #define MgslEvent_CtsActive 0x0004 | |
| 247 | #define MgslEvent_CtsInactive 0x0008 | |
| 248 | #define MgslEvent_Cts 0x000c | |
| 249 | #define MgslEvent_DcdActive 0x0010 | |
| 250 | #define MgslEvent_DcdInactive 0x0020 | |
| 251 | #define MgslEvent_Dcd 0x0030 | |
| 252 | #define MgslEvent_RiActive 0x0040 | |
| 253 | #define MgslEvent_RiInactive 0x0080 | |
| 254 | #define MgslEvent_Ri 0x00c0 | |
| 255 | #define MgslEvent_ExitHuntMode 0x0100 | |
| 256 | #define MgslEvent_IdleReceived 0x0200 | |
| 257 | ||
| 258 | /* Private IOCTL codes: | |
| 259 | * | |
| 260 | * MGSL_IOCSPARAMS set MGSL_PARAMS structure values | |
| 261 | * MGSL_IOCGPARAMS get current MGSL_PARAMS structure values | |
| 262 | * MGSL_IOCSTXIDLE set current transmit idle mode | |
| 263 | * MGSL_IOCGTXIDLE get current transmit idle mode | |
| 264 | * MGSL_IOCTXENABLE enable or disable transmitter | |
| 265 | * MGSL_IOCRXENABLE enable or disable receiver | |
| 266 | * MGSL_IOCTXABORT abort transmitting frame (HDLC) | |
| 267 | * MGSL_IOCGSTATS return current statistics | |
| 268 | * MGSL_IOCWAITEVENT wait for specified event to occur | |
| 269 | * MGSL_LOOPTXDONE transmit in HDLC LoopMode done | |
| 270 | * MGSL_IOCSIF set the serial interface type | |
| 271 | * MGSL_IOCGIF get the serial interface type | |
| 272 | */ | |
| 273 | #define MGSL_MAGIC_IOC 'm' | |
| 274 | #define MGSL_IOCSPARAMS _IOW(MGSL_MAGIC_IOC,0,struct _MGSL_PARAMS) | |
| 275 | #define MGSL_IOCGPARAMS _IOR(MGSL_MAGIC_IOC,1,struct _MGSL_PARAMS) | |
| 276 | #define MGSL_IOCSTXIDLE _IO(MGSL_MAGIC_IOC,2) | |
| 277 | #define MGSL_IOCGTXIDLE _IO(MGSL_MAGIC_IOC,3) | |
| 278 | #define MGSL_IOCTXENABLE _IO(MGSL_MAGIC_IOC,4) | |
| 279 | #define MGSL_IOCRXENABLE _IO(MGSL_MAGIC_IOC,5) | |
| 280 | #define MGSL_IOCTXABORT _IO(MGSL_MAGIC_IOC,6) | |
| 281 | #define MGSL_IOCGSTATS _IO(MGSL_MAGIC_IOC,7) | |
| 282 | #define MGSL_IOCWAITEVENT _IOWR(MGSL_MAGIC_IOC,8,int) | |
| 283 | #define MGSL_IOCCLRMODCOUNT _IO(MGSL_MAGIC_IOC,15) | |
| 284 | #define MGSL_IOCLOOPTXDONE _IO(MGSL_MAGIC_IOC,9) | |
| 285 | #define MGSL_IOCSIF _IO(MGSL_MAGIC_IOC,10) | |
| 286 | #define MGSL_IOCGIF _IO(MGSL_MAGIC_IOC,11) | |
| 0080b7aa PF |
287 | #define MGSL_IOCSGPIO _IOW(MGSL_MAGIC_IOC,16,struct gpio_desc) |
| 288 | #define MGSL_IOCGGPIO _IOR(MGSL_MAGIC_IOC,17,struct gpio_desc) | |
| 289 | #define MGSL_IOCWAITGPIO _IOWR(MGSL_MAGIC_IOC,18,struct gpio_desc) | |
| 1da177e4 | 290 | |
| 2acdb169 PF |
291 | #ifdef __KERNEL__ |
| 292 | /* provide 32 bit ioctl compatibility on 64 bit systems */ | |
| 293 | #ifdef CONFIG_COMPAT | |
| 294 | #include <linux/compat.h> | |
| 295 | struct MGSL_PARAMS32 { | |
| 296 | compat_ulong_t mode; | |
| 297 | unsigned char loopback; | |
| 298 | unsigned short flags; | |
| 299 | unsigned char encoding; | |
| 300 | compat_ulong_t clock_speed; | |
| 301 | unsigned char addr_filter; | |
| 302 | unsigned short crc_type; | |
| 303 | unsigned char preamble_length; | |
| 304 | unsigned char preamble; | |
| 305 | compat_ulong_t data_rate; | |
| 306 | unsigned char data_bits; | |
| 307 | unsigned char stop_bits; | |
| 308 | unsigned char parity; | |
| 309 | }; | |
| 310 | #define MGSL_IOCSPARAMS32 _IOW(MGSL_MAGIC_IOC,0,struct MGSL_PARAMS32) | |
| 311 | #define MGSL_IOCGPARAMS32 _IOR(MGSL_MAGIC_IOC,1,struct MGSL_PARAMS32) | |
| 312 | #endif | |
| 313 | #endif | |
| 314 | ||
| 1da177e4 | 315 | #endif /* _SYNCLINK_H_ */ |