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CommitLineData
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1/*
2 * QEMU CPU model
3 *
4 * Copyright (c) 2012 SUSE LINUX Products GmbH
5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License
8 * as published by the Free Software Foundation; either version 2
9 * of the License, or (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, see
18 * <http://www.gnu.org/licenses/gpl-2.0.html>
19 */
20#ifndef QEMU_CPU_H
21#define QEMU_CPU_H
22
fcd7d003 23#include <signal.h>
6f03bef0 24#include <setjmp.h>
961f8395 25#include "hw/qdev-core.h"
c658b94f 26#include "exec/hwaddr.h"
bdc44640 27#include "qemu/queue.h"
1de7afc9 28#include "qemu/thread.h"
4917cf44 29#include "qemu/tls.h"
a23bbfda 30#include "qemu/typedefs.h"
dd83b06a 31
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QN
32typedef int (*WriteCoreDumpFunction)(const void *buf, size_t size,
33 void *opaque);
c72bf468 34
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35/**
36 * vaddr:
37 * Type wide enough to contain any #target_ulong virtual address.
38 */
39typedef uint64_t vaddr;
40#define VADDR_PRId PRId64
41#define VADDR_PRIu PRIu64
42#define VADDR_PRIo PRIo64
43#define VADDR_PRIx PRIx64
44#define VADDR_PRIX PRIX64
45#define VADDR_MAX UINT64_MAX
46
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47/**
48 * SECTION:cpu
49 * @section_id: QEMU-cpu
50 * @title: CPU Class
51 * @short_description: Base class for all CPUs
52 */
53
54#define TYPE_CPU "cpu"
55
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56/* Since this macro is used a lot in hot code paths and in conjunction with
57 * FooCPU *foo_env_get_cpu(), we deviate from usual QOM practice by using
58 * an unchecked cast.
59 */
60#define CPU(obj) ((CPUState *)(obj))
61
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62#define CPU_CLASS(class) OBJECT_CLASS_CHECK(CPUClass, (class), TYPE_CPU)
63#define CPU_GET_CLASS(obj) OBJECT_GET_CLASS(CPUClass, (obj), TYPE_CPU)
64
65typedef struct CPUState CPUState;
66
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67typedef void (*CPUUnassignedAccess)(CPUState *cpu, hwaddr addr,
68 bool is_write, bool is_exec, int opaque,
69 unsigned size);
70
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71struct TranslationBlock;
72
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73/**
74 * CPUClass:
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75 * @class_by_name: Callback to map -cpu command line model name to an
76 * instantiatable CPU type.
94a444b2 77 * @parse_features: Callback to parse command line arguments.
f5df5baf 78 * @reset: Callback to reset the #CPUState to its initial state.
91b1df8c 79 * @reset_dump_flags: #CPUDumpFlags to use for reset logging.
8c2e1b00 80 * @has_work: Callback for checking if there is work to do.
97a8ea5a 81 * @do_interrupt: Callback for interrupt handling.
c658b94f 82 * @do_unassigned_access: Callback for unassigned access handling.
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83 * @do_unaligned_access: Callback for unaligned access handling, if
84 * the target defines #ALIGNED_ONLY.
f3659eee 85 * @memory_rw_debug: Callback for GDB memory access.
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86 * @dump_state: Callback for dumping state.
87 * @dump_statistics: Callback for dumping statistics.
997395d3 88 * @get_arch_id: Callback for getting architecture-dependent CPU ID.
444d5590 89 * @get_paging_enabled: Callback for inquiring whether paging is enabled.
a23bbfda 90 * @get_memory_mapping: Callback for obtaining the memory mappings.
f45748f1 91 * @set_pc: Callback for setting the Program Counter register.
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92 * @synchronize_from_tb: Callback for synchronizing state from a TCG
93 * #TranslationBlock.
7510454e 94 * @handle_mmu_fault: Callback for handling an MMU fault.
00b941e5 95 * @get_phys_page_debug: Callback for obtaining a physical address.
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96 * @gdb_read_register: Callback for letting GDB read a register.
97 * @gdb_write_register: Callback for letting GDB write a register.
86025ee4 98 * @debug_excp_handler: Callback for handling debug exceptions.
b170fce3 99 * @vmsd: State description for migration.
a0e372f0 100 * @gdb_num_core_regs: Number of core registers accessible to GDB.
5b24c641 101 * @gdb_core_xml_file: File name for core registers GDB XML description.
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102 *
103 * Represents a CPU family or model.
104 */
105typedef struct CPUClass {
106 /*< private >*/
961f8395 107 DeviceClass parent_class;
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108 /*< public >*/
109
2b8c2754 110 ObjectClass *(*class_by_name)(const char *cpu_model);
94a444b2 111 void (*parse_features)(CPUState *cpu, char *str, Error **errp);
2b8c2754 112
dd83b06a 113 void (*reset)(CPUState *cpu);
91b1df8c 114 int reset_dump_flags;
8c2e1b00 115 bool (*has_work)(CPUState *cpu);
97a8ea5a 116 void (*do_interrupt)(CPUState *cpu);
c658b94f 117 CPUUnassignedAccess do_unassigned_access;
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118 void (*do_unaligned_access)(CPUState *cpu, vaddr addr,
119 int is_write, int is_user, uintptr_t retaddr);
bf7663c4 120 bool (*virtio_is_big_endian)(CPUState *cpu);
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121 int (*memory_rw_debug)(CPUState *cpu, vaddr addr,
122 uint8_t *buf, int len, bool is_write);
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123 void (*dump_state)(CPUState *cpu, FILE *f, fprintf_function cpu_fprintf,
124 int flags);
125 void (*dump_statistics)(CPUState *cpu, FILE *f,
126 fprintf_function cpu_fprintf, int flags);
997395d3 127 int64_t (*get_arch_id)(CPUState *cpu);
444d5590 128 bool (*get_paging_enabled)(const CPUState *cpu);
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129 void (*get_memory_mapping)(CPUState *cpu, MemoryMappingList *list,
130 Error **errp);
f45748f1 131 void (*set_pc)(CPUState *cpu, vaddr value);
bdf7ae5b 132 void (*synchronize_from_tb)(CPUState *cpu, struct TranslationBlock *tb);
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133 int (*handle_mmu_fault)(CPUState *cpu, vaddr address, int rw,
134 int mmu_index);
00b941e5 135 hwaddr (*get_phys_page_debug)(CPUState *cpu, vaddr addr);
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136 int (*gdb_read_register)(CPUState *cpu, uint8_t *buf, int reg);
137 int (*gdb_write_register)(CPUState *cpu, uint8_t *buf, int reg);
86025ee4 138 void (*debug_excp_handler)(CPUState *cpu);
b170fce3 139
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140 int (*write_elf64_note)(WriteCoreDumpFunction f, CPUState *cpu,
141 int cpuid, void *opaque);
142 int (*write_elf64_qemunote)(WriteCoreDumpFunction f, CPUState *cpu,
143 void *opaque);
144 int (*write_elf32_note)(WriteCoreDumpFunction f, CPUState *cpu,
145 int cpuid, void *opaque);
146 int (*write_elf32_qemunote)(WriteCoreDumpFunction f, CPUState *cpu,
147 void *opaque);
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148
149 const struct VMStateDescription *vmsd;
150 int gdb_num_core_regs;
5b24c641 151 const char *gdb_core_xml_file;
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152} CPUClass;
153
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154#ifdef HOST_WORDS_BIGENDIAN
155typedef struct icount_decr_u16 {
156 uint16_t high;
157 uint16_t low;
158} icount_decr_u16;
159#else
160typedef struct icount_decr_u16 {
161 uint16_t low;
162 uint16_t high;
163} icount_decr_u16;
164#endif
165
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166typedef struct CPUBreakpoint {
167 vaddr pc;
168 int flags; /* BP_* */
169 QTAILQ_ENTRY(CPUBreakpoint) entry;
170} CPUBreakpoint;
171
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172typedef struct CPUWatchpoint {
173 vaddr vaddr;
05068c0d 174 vaddr len;
08225676 175 vaddr hitaddr;
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176 int flags; /* BP_* */
177 QTAILQ_ENTRY(CPUWatchpoint) entry;
178} CPUWatchpoint;
179
a60f24b5 180struct KVMState;
f7575c96 181struct kvm_run;
a60f24b5 182
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183#define TB_JMP_CACHE_BITS 12
184#define TB_JMP_CACHE_SIZE (1 << TB_JMP_CACHE_BITS)
185
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186/**
187 * CPUState:
55e5c285 188 * @cpu_index: CPU index (informative).
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189 * @nr_cores: Number of cores within this CPU package.
190 * @nr_threads: Number of threads within this CPU.
1b1ed8dc 191 * @numa_node: NUMA node this CPU is belonging to.
0d34282f 192 * @host_tid: Host thread ID.
0315c31c 193 * @running: #true if CPU is currently running (usermode).
61a46217 194 * @created: Indicates whether the CPU thread has been successfully created.
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195 * @interrupt_request: Indicates a pending interrupt request.
196 * @halted: Nonzero if the CPU is in suspended state.
4fdeee7c 197 * @stop: Indicates a pending stop request.
f324e766 198 * @stopped: Indicates the CPU has been artificially stopped.
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199 * @tcg_exit_req: Set to force TCG to stop executing linked TBs for this
200 * CPU and return to its top level loop.
ed2803da 201 * @singlestep_enabled: Flags for single-stepping.
efee7340 202 * @icount_extra: Instructions until next timer event.
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203 * @icount_decr: Number of cycles left, with interrupt flag in high bit.
204 * This allows a single read-compare-cbranch-write sequence to test
205 * for both decrementer underflow and exceptions.
99df7dce 206 * @can_do_io: Nonzero if memory-mapped IO is safe.
c05efcb1 207 * @env_ptr: Pointer to subclass-specific CPUArchState field.
d77953b9 208 * @current_tb: Currently executing TB.
eac8b355 209 * @gdb_regs: Additional GDB registers.
a0e372f0 210 * @gdb_num_regs: Number of total registers accessible to GDB.
35143f01 211 * @gdb_num_g_regs: Number of registers in GDB 'g' packets.
182735ef 212 * @next_cpu: Next CPU sharing TB cache.
0429a971 213 * @opaque: User data.
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214 * @mem_io_pc: Host Program Counter at which the memory was accessed.
215 * @mem_io_vaddr: Target virtual address at which the memory was accessed.
8737c51c 216 * @kvm_fd: vCPU file descriptor for KVM.
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217 *
218 * State of one CPU core or thread.
219 */
220struct CPUState {
221 /*< private >*/
961f8395 222 DeviceState parent_obj;
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223 /*< public >*/
224
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225 int nr_cores;
226 int nr_threads;
1b1ed8dc 227 int numa_node;
ce3960eb 228
814e612e 229 struct QemuThread *thread;
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230#ifdef _WIN32
231 HANDLE hThread;
232#endif
9f09e18a 233 int thread_id;
0d34282f 234 uint32_t host_tid;
0315c31c 235 bool running;
f5c121b8 236 struct QemuCond *halt_cond;
c64ca814 237 struct qemu_work_item *queued_work_first, *queued_work_last;
216fc9a4 238 bool thread_kicked;
61a46217 239 bool created;
4fdeee7c 240 bool stop;
f324e766 241 bool stopped;
fcd7d003 242 volatile sig_atomic_t exit_request;
259186a7 243 uint32_t interrupt_request;
ed2803da 244 int singlestep_enabled;
efee7340 245 int64_t icount_extra;
6f03bef0 246 sigjmp_buf jmp_env;
bcba2a72 247
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248 AddressSpace *as;
249 MemoryListener *tcg_as_listener;
250
c05efcb1 251 void *env_ptr; /* CPUArchState */
d77953b9 252 struct TranslationBlock *current_tb;
8cd70437 253 struct TranslationBlock *tb_jmp_cache[TB_JMP_CACHE_SIZE];
eac8b355 254 struct GDBRegisterState *gdb_regs;
a0e372f0 255 int gdb_num_regs;
35143f01 256 int gdb_num_g_regs;
bdc44640 257 QTAILQ_ENTRY(CPUState) node;
d77953b9 258
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259 /* ice debug support */
260 QTAILQ_HEAD(breakpoints_head, CPUBreakpoint) breakpoints;
261
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262 QTAILQ_HEAD(watchpoints_head, CPUWatchpoint) watchpoints;
263 CPUWatchpoint *watchpoint_hit;
264
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265 void *opaque;
266
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267 /* In order to avoid passing too many arguments to the MMIO helpers,
268 * we store some rarely used information in the CPU context.
269 */
270 uintptr_t mem_io_pc;
271 vaddr mem_io_vaddr;
272
8737c51c 273 int kvm_fd;
20d695a9 274 bool kvm_vcpu_dirty;
a60f24b5 275 struct KVMState *kvm_state;
f7575c96 276 struct kvm_run *kvm_run;
8737c51c 277
f5df5baf 278 /* TODO Move common fields from CPUArchState here. */
55e5c285 279 int cpu_index; /* used by alpha TCG */
259186a7 280 uint32_t halted; /* used by alpha, cris, ppc TCG */
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281 union {
282 uint32_t u32;
283 icount_decr_u16 u16;
284 } icount_decr;
99df7dce 285 uint32_t can_do_io;
27103424 286 int32_t exception_index; /* used by m68k TCG */
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287
288 /* Note that this is accessed at the start of every TB via a negative
289 offset from AREG0. Leave this field at the end so as to make the
290 (absolute value) offset as small as possible. This reduces code
291 size, especially for hosts without large memory offsets. */
292 volatile sig_atomic_t tcg_exit_req;
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293};
294
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295QTAILQ_HEAD(CPUTailQ, CPUState);
296extern struct CPUTailQ cpus;
297#define CPU_NEXT(cpu) QTAILQ_NEXT(cpu, node)
298#define CPU_FOREACH(cpu) QTAILQ_FOREACH(cpu, &cpus, node)
299#define CPU_FOREACH_SAFE(cpu, next_cpu) \
300 QTAILQ_FOREACH_SAFE(cpu, &cpus, node, next_cpu)
301#define first_cpu QTAILQ_FIRST(&cpus)
182735ef 302
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303DECLARE_TLS(CPUState *, current_cpu);
304#define current_cpu tls_var(current_cpu)
305
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306/**
307 * cpu_paging_enabled:
308 * @cpu: The CPU whose state is to be inspected.
309 *
310 * Returns: %true if paging is enabled, %false otherwise.
311 */
312bool cpu_paging_enabled(const CPUState *cpu);
313
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314/**
315 * cpu_get_memory_mapping:
316 * @cpu: The CPU whose memory mappings are to be obtained.
317 * @list: Where to write the memory mappings to.
318 * @errp: Pointer for reporting an #Error.
319 */
320void cpu_get_memory_mapping(CPUState *cpu, MemoryMappingList *list,
321 Error **errp);
322
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323/**
324 * cpu_write_elf64_note:
325 * @f: pointer to a function that writes memory to a file
326 * @cpu: The CPU whose memory is to be dumped
327 * @cpuid: ID number of the CPU
328 * @opaque: pointer to the CPUState struct
329 */
330int cpu_write_elf64_note(WriteCoreDumpFunction f, CPUState *cpu,
331 int cpuid, void *opaque);
332
333/**
334 * cpu_write_elf64_qemunote:
335 * @f: pointer to a function that writes memory to a file
336 * @cpu: The CPU whose memory is to be dumped
337 * @cpuid: ID number of the CPU
338 * @opaque: pointer to the CPUState struct
339 */
340int cpu_write_elf64_qemunote(WriteCoreDumpFunction f, CPUState *cpu,
341 void *opaque);
342
343/**
344 * cpu_write_elf32_note:
345 * @f: pointer to a function that writes memory to a file
346 * @cpu: The CPU whose memory is to be dumped
347 * @cpuid: ID number of the CPU
348 * @opaque: pointer to the CPUState struct
349 */
350int cpu_write_elf32_note(WriteCoreDumpFunction f, CPUState *cpu,
351 int cpuid, void *opaque);
352
353/**
354 * cpu_write_elf32_qemunote:
355 * @f: pointer to a function that writes memory to a file
356 * @cpu: The CPU whose memory is to be dumped
357 * @cpuid: ID number of the CPU
358 * @opaque: pointer to the CPUState struct
359 */
360int cpu_write_elf32_qemunote(WriteCoreDumpFunction f, CPUState *cpu,
361 void *opaque);
dd83b06a 362
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363/**
364 * CPUDumpFlags:
365 * @CPU_DUMP_CODE:
366 * @CPU_DUMP_FPU: dump FPU register state, not just integer
367 * @CPU_DUMP_CCOP: dump info about TCG QEMU's condition code optimization state
368 */
369enum CPUDumpFlags {
370 CPU_DUMP_CODE = 0x00010000,
371 CPU_DUMP_FPU = 0x00020000,
372 CPU_DUMP_CCOP = 0x00040000,
373};
374
375/**
376 * cpu_dump_state:
377 * @cpu: The CPU whose state is to be dumped.
378 * @f: File to dump to.
379 * @cpu_fprintf: Function to dump with.
380 * @flags: Flags what to dump.
381 *
382 * Dumps CPU state.
383 */
384void cpu_dump_state(CPUState *cpu, FILE *f, fprintf_function cpu_fprintf,
385 int flags);
386
387/**
388 * cpu_dump_statistics:
389 * @cpu: The CPU whose state is to be dumped.
390 * @f: File to dump to.
391 * @cpu_fprintf: Function to dump with.
392 * @flags: Flags what to dump.
393 *
394 * Dumps CPU statistics.
395 */
396void cpu_dump_statistics(CPUState *cpu, FILE *f, fprintf_function cpu_fprintf,
397 int flags);
398
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399#ifndef CONFIG_USER_ONLY
400/**
401 * cpu_get_phys_page_debug:
402 * @cpu: The CPU to obtain the physical page address for.
403 * @addr: The virtual address.
404 *
405 * Obtains the physical page corresponding to a virtual one.
406 * Use it only for debugging because no protection checks are done.
407 *
408 * Returns: Corresponding physical page address or -1 if no page found.
409 */
410static inline hwaddr cpu_get_phys_page_debug(CPUState *cpu, vaddr addr)
411{
412 CPUClass *cc = CPU_GET_CLASS(cpu);
413
414 return cc->get_phys_page_debug(cpu, addr);
415}
416#endif
417
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418/**
419 * cpu_reset:
420 * @cpu: The CPU whose state is to be reset.
421 */
422void cpu_reset(CPUState *cpu);
423
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424/**
425 * cpu_class_by_name:
426 * @typename: The CPU base type.
427 * @cpu_model: The model string without any parameters.
428 *
429 * Looks up a CPU #ObjectClass matching name @cpu_model.
430 *
431 * Returns: A #CPUClass or %NULL if not matching class is found.
432 */
433ObjectClass *cpu_class_by_name(const char *typename, const char *cpu_model);
434
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435/**
436 * cpu_generic_init:
437 * @typename: The CPU base type.
438 * @cpu_model: The model string including optional parameters.
439 *
440 * Instantiates a CPU, processes optional parameters and realizes the CPU.
441 *
442 * Returns: A #CPUState or %NULL if an error occurred.
443 */
444CPUState *cpu_generic_init(const char *typename, const char *cpu_model);
445
3993c6bd 446/**
8c2e1b00 447 * cpu_has_work:
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448 * @cpu: The vCPU to check.
449 *
450 * Checks whether the CPU has work to do.
451 *
452 * Returns: %true if the CPU has work, %false otherwise.
453 */
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454static inline bool cpu_has_work(CPUState *cpu)
455{
456 CPUClass *cc = CPU_GET_CLASS(cpu);
457
458 g_assert(cc->has_work);
459 return cc->has_work(cpu);
460}
3993c6bd 461
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462/**
463 * qemu_cpu_is_self:
464 * @cpu: The vCPU to check against.
465 *
466 * Checks whether the caller is executing on the vCPU thread.
467 *
468 * Returns: %true if called from @cpu's thread, %false otherwise.
469 */
470bool qemu_cpu_is_self(CPUState *cpu);
471
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472/**
473 * qemu_cpu_kick:
474 * @cpu: The vCPU to kick.
475 *
476 * Kicks @cpu's thread.
477 */
478void qemu_cpu_kick(CPUState *cpu);
479
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480/**
481 * cpu_is_stopped:
482 * @cpu: The CPU to check.
483 *
484 * Checks whether the CPU is stopped.
485 *
486 * Returns: %true if run state is not running or if artificially stopped;
487 * %false otherwise.
488 */
489bool cpu_is_stopped(CPUState *cpu);
490
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491/**
492 * run_on_cpu:
493 * @cpu: The vCPU to run on.
494 * @func: The function to be executed.
495 * @data: Data to pass to the function.
496 *
497 * Schedules the function @func for execution on the vCPU @cpu.
498 */
499void run_on_cpu(CPUState *cpu, void (*func)(void *data), void *data);
500
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501/**
502 * async_run_on_cpu:
503 * @cpu: The vCPU to run on.
504 * @func: The function to be executed.
505 * @data: Data to pass to the function.
506 *
507 * Schedules the function @func for execution on the vCPU @cpu asynchronously.
508 */
509void async_run_on_cpu(CPUState *cpu, void (*func)(void *data), void *data);
510
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511/**
512 * qemu_get_cpu:
513 * @index: The CPUState@cpu_index value of the CPU to obtain.
514 *
515 * Gets a CPU matching @index.
516 *
517 * Returns: The CPU or %NULL if there is no matching CPU.
518 */
519CPUState *qemu_get_cpu(int index);
520
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IM
521/**
522 * cpu_exists:
523 * @id: Guest-exposed CPU ID to lookup.
524 *
525 * Search for CPU with specified ID.
526 *
527 * Returns: %true - CPU is found, %false - CPU isn't found.
528 */
529bool cpu_exists(int64_t id);
530
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531#ifndef CONFIG_USER_ONLY
532
533typedef void (*CPUInterruptHandler)(CPUState *, int);
534
535extern CPUInterruptHandler cpu_interrupt_handler;
536
537/**
538 * cpu_interrupt:
539 * @cpu: The CPU to set an interrupt on.
540 * @mask: The interupts to set.
541 *
542 * Invokes the interrupt handler.
543 */
544static inline void cpu_interrupt(CPUState *cpu, int mask)
545{
546 cpu_interrupt_handler(cpu, mask);
547}
548
549#else /* USER_ONLY */
550
551void cpu_interrupt(CPUState *cpu, int mask);
552
553#endif /* USER_ONLY */
554
93e22326 555#ifdef CONFIG_SOFTMMU
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556static inline void cpu_unassigned_access(CPUState *cpu, hwaddr addr,
557 bool is_write, bool is_exec,
558 int opaque, unsigned size)
559{
560 CPUClass *cc = CPU_GET_CLASS(cpu);
561
562 if (cc->do_unassigned_access) {
563 cc->do_unassigned_access(cpu, addr, is_write, is_exec, opaque, size);
564 }
565}
566
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PB
567static inline void cpu_unaligned_access(CPUState *cpu, vaddr addr,
568 int is_write, int is_user,
569 uintptr_t retaddr)
570{
571 CPUClass *cc = CPU_GET_CLASS(cpu);
572
573 return cc->do_unaligned_access(cpu, addr, is_write, is_user, retaddr);
574}
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575#endif
576
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577/**
578 * cpu_reset_interrupt:
579 * @cpu: The CPU to clear the interrupt on.
580 * @mask: The interrupt mask to clear.
581 *
582 * Resets interrupts on the vCPU @cpu.
583 */
584void cpu_reset_interrupt(CPUState *cpu, int mask);
585
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586/**
587 * cpu_exit:
588 * @cpu: The CPU to exit.
589 *
590 * Requests the CPU @cpu to exit execution.
591 */
592void cpu_exit(CPUState *cpu);
593
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594/**
595 * cpu_resume:
596 * @cpu: The CPU to resume.
597 *
598 * Resumes CPU, i.e. puts CPU into runnable state.
599 */
600void cpu_resume(CPUState *cpu);
dd83b06a 601
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602/**
603 * qemu_init_vcpu:
604 * @cpu: The vCPU to initialize.
605 *
606 * Initializes a vCPU.
607 */
608void qemu_init_vcpu(CPUState *cpu);
609
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610#define SSTEP_ENABLE 0x1 /* Enable simulated HW single stepping */
611#define SSTEP_NOIRQ 0x2 /* Do not use IRQ while single stepping */
612#define SSTEP_NOTIMER 0x4 /* Do not Timers while single stepping */
613
614/**
615 * cpu_single_step:
616 * @cpu: CPU to the flags for.
617 * @enabled: Flags to enable.
618 *
619 * Enables or disables single-stepping for @cpu.
620 */
621void cpu_single_step(CPUState *cpu, int enabled);
622
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623/* Breakpoint/watchpoint flags */
624#define BP_MEM_READ 0x01
625#define BP_MEM_WRITE 0x02
626#define BP_MEM_ACCESS (BP_MEM_READ | BP_MEM_WRITE)
627#define BP_STOP_BEFORE_ACCESS 0x04
08225676 628/* 0x08 currently unused */
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629#define BP_GDB 0x10
630#define BP_CPU 0x20
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631#define BP_WATCHPOINT_HIT_READ 0x40
632#define BP_WATCHPOINT_HIT_WRITE 0x80
633#define BP_WATCHPOINT_HIT (BP_WATCHPOINT_HIT_READ | BP_WATCHPOINT_HIT_WRITE)
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634
635int cpu_breakpoint_insert(CPUState *cpu, vaddr pc, int flags,
636 CPUBreakpoint **breakpoint);
637int cpu_breakpoint_remove(CPUState *cpu, vaddr pc, int flags);
638void cpu_breakpoint_remove_by_ref(CPUState *cpu, CPUBreakpoint *breakpoint);
639void cpu_breakpoint_remove_all(CPUState *cpu, int mask);
640
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641int cpu_watchpoint_insert(CPUState *cpu, vaddr addr, vaddr len,
642 int flags, CPUWatchpoint **watchpoint);
643int cpu_watchpoint_remove(CPUState *cpu, vaddr addr,
644 vaddr len, int flags);
645void cpu_watchpoint_remove_by_ref(CPUState *cpu, CPUWatchpoint *watchpoint);
646void cpu_watchpoint_remove_all(CPUState *cpu, int mask);
647
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648void QEMU_NORETURN cpu_abort(CPUState *cpu, const char *fmt, ...)
649 GCC_FMT_ATTR(2, 3);
650
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651#ifdef CONFIG_SOFTMMU
652extern const struct VMStateDescription vmstate_cpu_common;
653#else
654#define vmstate_cpu_common vmstate_dummy
655#endif
656
657#define VMSTATE_CPU() { \
658 .name = "parent_obj", \
659 .size = sizeof(CPUState), \
660 .vmsd = &vmstate_cpu_common, \
661 .flags = VMS_STRUCT, \
662 .offset = 0, \
663}
664
dd83b06a 665#endif