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dd83b06a AF |
1 | /* |
2 | * QEMU CPU model | |
3 | * | |
4 | * Copyright (c) 2012 SUSE LINUX Products GmbH | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or | |
7 | * modify it under the terms of the GNU General Public License | |
8 | * as published by the Free Software Foundation; either version 2 | |
9 | * of the License, or (at your option) any later version. | |
10 | * | |
11 | * This program is distributed in the hope that it will be useful, | |
12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
14 | * GNU General Public License for more details. | |
15 | * | |
16 | * You should have received a copy of the GNU General Public License | |
17 | * along with this program; if not, see | |
18 | * <http://www.gnu.org/licenses/gpl-2.0.html> | |
19 | */ | |
20 | #ifndef QEMU_CPU_H | |
21 | #define QEMU_CPU_H | |
22 | ||
fcd7d003 | 23 | #include <signal.h> |
6f03bef0 | 24 | #include <setjmp.h> |
961f8395 | 25 | #include "hw/qdev-core.h" |
37b9de46 | 26 | #include "disas/bfd.h" |
c658b94f | 27 | #include "exec/hwaddr.h" |
66b9b43c | 28 | #include "exec/memattrs.h" |
bdc44640 | 29 | #include "qemu/queue.h" |
1de7afc9 | 30 | #include "qemu/thread.h" |
a23bbfda | 31 | #include "qemu/typedefs.h" |
dd83b06a | 32 | |
b5ba1cc6 QN |
33 | typedef int (*WriteCoreDumpFunction)(const void *buf, size_t size, |
34 | void *opaque); | |
c72bf468 | 35 | |
577f42c0 AF |
36 | /** |
37 | * vaddr: | |
38 | * Type wide enough to contain any #target_ulong virtual address. | |
39 | */ | |
40 | typedef uint64_t vaddr; | |
41 | #define VADDR_PRId PRId64 | |
42 | #define VADDR_PRIu PRIu64 | |
43 | #define VADDR_PRIo PRIo64 | |
44 | #define VADDR_PRIx PRIx64 | |
45 | #define VADDR_PRIX PRIX64 | |
46 | #define VADDR_MAX UINT64_MAX | |
47 | ||
dd83b06a AF |
48 | /** |
49 | * SECTION:cpu | |
50 | * @section_id: QEMU-cpu | |
51 | * @title: CPU Class | |
52 | * @short_description: Base class for all CPUs | |
53 | */ | |
54 | ||
55 | #define TYPE_CPU "cpu" | |
56 | ||
0d6d1ab4 AF |
57 | /* Since this macro is used a lot in hot code paths and in conjunction with |
58 | * FooCPU *foo_env_get_cpu(), we deviate from usual QOM practice by using | |
59 | * an unchecked cast. | |
60 | */ | |
61 | #define CPU(obj) ((CPUState *)(obj)) | |
62 | ||
dd83b06a AF |
63 | #define CPU_CLASS(class) OBJECT_CLASS_CHECK(CPUClass, (class), TYPE_CPU) |
64 | #define CPU_GET_CLASS(obj) OBJECT_GET_CLASS(CPUClass, (obj), TYPE_CPU) | |
65 | ||
66 | typedef struct CPUState CPUState; | |
67 | ||
c658b94f AF |
68 | typedef void (*CPUUnassignedAccess)(CPUState *cpu, hwaddr addr, |
69 | bool is_write, bool is_exec, int opaque, | |
70 | unsigned size); | |
71 | ||
bdf7ae5b AF |
72 | struct TranslationBlock; |
73 | ||
dd83b06a AF |
74 | /** |
75 | * CPUClass: | |
2b8c2754 AF |
76 | * @class_by_name: Callback to map -cpu command line model name to an |
77 | * instantiatable CPU type. | |
94a444b2 | 78 | * @parse_features: Callback to parse command line arguments. |
f5df5baf | 79 | * @reset: Callback to reset the #CPUState to its initial state. |
91b1df8c | 80 | * @reset_dump_flags: #CPUDumpFlags to use for reset logging. |
8c2e1b00 | 81 | * @has_work: Callback for checking if there is work to do. |
97a8ea5a | 82 | * @do_interrupt: Callback for interrupt handling. |
c658b94f | 83 | * @do_unassigned_access: Callback for unassigned access handling. |
93e22326 PB |
84 | * @do_unaligned_access: Callback for unaligned access handling, if |
85 | * the target defines #ALIGNED_ONLY. | |
c08295d4 PM |
86 | * @virtio_is_big_endian: Callback to return %true if a CPU which supports |
87 | * runtime configurable endianness is currently big-endian. Non-configurable | |
88 | * CPUs can use the default implementation of this method. This method should | |
89 | * not be used by any callers other than the pre-1.0 virtio devices. | |
f3659eee | 90 | * @memory_rw_debug: Callback for GDB memory access. |
878096ee AF |
91 | * @dump_state: Callback for dumping state. |
92 | * @dump_statistics: Callback for dumping statistics. | |
997395d3 | 93 | * @get_arch_id: Callback for getting architecture-dependent CPU ID. |
444d5590 | 94 | * @get_paging_enabled: Callback for inquiring whether paging is enabled. |
a23bbfda | 95 | * @get_memory_mapping: Callback for obtaining the memory mappings. |
f45748f1 | 96 | * @set_pc: Callback for setting the Program Counter register. |
bdf7ae5b AF |
97 | * @synchronize_from_tb: Callback for synchronizing state from a TCG |
98 | * #TranslationBlock. | |
7510454e | 99 | * @handle_mmu_fault: Callback for handling an MMU fault. |
00b941e5 | 100 | * @get_phys_page_debug: Callback for obtaining a physical address. |
1dc6fb1f PM |
101 | * @get_phys_page_attrs_debug: Callback for obtaining a physical address and the |
102 | * associated memory transaction attributes to use for the access. | |
103 | * CPUs which use memory transaction attributes should implement this | |
104 | * instead of get_phys_page_debug. | |
5b50e790 AF |
105 | * @gdb_read_register: Callback for letting GDB read a register. |
106 | * @gdb_write_register: Callback for letting GDB write a register. | |
86025ee4 | 107 | * @debug_excp_handler: Callback for handling debug exceptions. |
c08295d4 PM |
108 | * @write_elf64_note: Callback for writing a CPU-specific ELF note to a |
109 | * 64-bit VM coredump. | |
110 | * @write_elf32_qemunote: Callback for writing a CPU- and QEMU-specific ELF | |
111 | * note to a 32-bit VM coredump. | |
112 | * @write_elf32_note: Callback for writing a CPU-specific ELF note to a | |
113 | * 32-bit VM coredump. | |
114 | * @write_elf32_qemunote: Callback for writing a CPU- and QEMU-specific ELF | |
115 | * note to a 32-bit VM coredump. | |
b170fce3 | 116 | * @vmsd: State description for migration. |
a0e372f0 | 117 | * @gdb_num_core_regs: Number of core registers accessible to GDB. |
5b24c641 | 118 | * @gdb_core_xml_file: File name for core registers GDB XML description. |
2472b6c0 PM |
119 | * @gdb_stop_before_watchpoint: Indicates whether GDB expects the CPU to stop |
120 | * before the insn which triggers a watchpoint rather than after it. | |
cffe7b32 RH |
121 | * @cpu_exec_enter: Callback for cpu_exec preparation. |
122 | * @cpu_exec_exit: Callback for cpu_exec cleanup. | |
9585db68 | 123 | * @cpu_exec_interrupt: Callback for processing interrupts in cpu_exec. |
37b9de46 | 124 | * @disas_set_info: Setup architecture specific components of disassembly info |
dd83b06a AF |
125 | * |
126 | * Represents a CPU family or model. | |
127 | */ | |
128 | typedef struct CPUClass { | |
129 | /*< private >*/ | |
961f8395 | 130 | DeviceClass parent_class; |
dd83b06a AF |
131 | /*< public >*/ |
132 | ||
2b8c2754 | 133 | ObjectClass *(*class_by_name)(const char *cpu_model); |
94a444b2 | 134 | void (*parse_features)(CPUState *cpu, char *str, Error **errp); |
2b8c2754 | 135 | |
dd83b06a | 136 | void (*reset)(CPUState *cpu); |
91b1df8c | 137 | int reset_dump_flags; |
8c2e1b00 | 138 | bool (*has_work)(CPUState *cpu); |
97a8ea5a | 139 | void (*do_interrupt)(CPUState *cpu); |
c658b94f | 140 | CPUUnassignedAccess do_unassigned_access; |
93e22326 PB |
141 | void (*do_unaligned_access)(CPUState *cpu, vaddr addr, |
142 | int is_write, int is_user, uintptr_t retaddr); | |
bf7663c4 | 143 | bool (*virtio_is_big_endian)(CPUState *cpu); |
f3659eee AF |
144 | int (*memory_rw_debug)(CPUState *cpu, vaddr addr, |
145 | uint8_t *buf, int len, bool is_write); | |
878096ee AF |
146 | void (*dump_state)(CPUState *cpu, FILE *f, fprintf_function cpu_fprintf, |
147 | int flags); | |
148 | void (*dump_statistics)(CPUState *cpu, FILE *f, | |
149 | fprintf_function cpu_fprintf, int flags); | |
997395d3 | 150 | int64_t (*get_arch_id)(CPUState *cpu); |
444d5590 | 151 | bool (*get_paging_enabled)(const CPUState *cpu); |
a23bbfda AF |
152 | void (*get_memory_mapping)(CPUState *cpu, MemoryMappingList *list, |
153 | Error **errp); | |
f45748f1 | 154 | void (*set_pc)(CPUState *cpu, vaddr value); |
bdf7ae5b | 155 | void (*synchronize_from_tb)(CPUState *cpu, struct TranslationBlock *tb); |
7510454e AF |
156 | int (*handle_mmu_fault)(CPUState *cpu, vaddr address, int rw, |
157 | int mmu_index); | |
00b941e5 | 158 | hwaddr (*get_phys_page_debug)(CPUState *cpu, vaddr addr); |
1dc6fb1f PM |
159 | hwaddr (*get_phys_page_attrs_debug)(CPUState *cpu, vaddr addr, |
160 | MemTxAttrs *attrs); | |
5b50e790 AF |
161 | int (*gdb_read_register)(CPUState *cpu, uint8_t *buf, int reg); |
162 | int (*gdb_write_register)(CPUState *cpu, uint8_t *buf, int reg); | |
86025ee4 | 163 | void (*debug_excp_handler)(CPUState *cpu); |
b170fce3 | 164 | |
c72bf468 JF |
165 | int (*write_elf64_note)(WriteCoreDumpFunction f, CPUState *cpu, |
166 | int cpuid, void *opaque); | |
167 | int (*write_elf64_qemunote)(WriteCoreDumpFunction f, CPUState *cpu, | |
168 | void *opaque); | |
169 | int (*write_elf32_note)(WriteCoreDumpFunction f, CPUState *cpu, | |
170 | int cpuid, void *opaque); | |
171 | int (*write_elf32_qemunote)(WriteCoreDumpFunction f, CPUState *cpu, | |
172 | void *opaque); | |
a0e372f0 AF |
173 | |
174 | const struct VMStateDescription *vmsd; | |
175 | int gdb_num_core_regs; | |
5b24c641 | 176 | const char *gdb_core_xml_file; |
2472b6c0 | 177 | bool gdb_stop_before_watchpoint; |
cffe7b32 RH |
178 | |
179 | void (*cpu_exec_enter)(CPUState *cpu); | |
180 | void (*cpu_exec_exit)(CPUState *cpu); | |
9585db68 | 181 | bool (*cpu_exec_interrupt)(CPUState *cpu, int interrupt_request); |
37b9de46 PC |
182 | |
183 | void (*disas_set_info)(CPUState *cpu, disassemble_info *info); | |
dd83b06a AF |
184 | } CPUClass; |
185 | ||
28ecfd7a AF |
186 | #ifdef HOST_WORDS_BIGENDIAN |
187 | typedef struct icount_decr_u16 { | |
188 | uint16_t high; | |
189 | uint16_t low; | |
190 | } icount_decr_u16; | |
191 | #else | |
192 | typedef struct icount_decr_u16 { | |
193 | uint16_t low; | |
194 | uint16_t high; | |
195 | } icount_decr_u16; | |
196 | #endif | |
197 | ||
f0c3c505 AF |
198 | typedef struct CPUBreakpoint { |
199 | vaddr pc; | |
200 | int flags; /* BP_* */ | |
201 | QTAILQ_ENTRY(CPUBreakpoint) entry; | |
202 | } CPUBreakpoint; | |
203 | ||
ff4700b0 AF |
204 | typedef struct CPUWatchpoint { |
205 | vaddr vaddr; | |
05068c0d | 206 | vaddr len; |
08225676 | 207 | vaddr hitaddr; |
66b9b43c | 208 | MemTxAttrs hitattrs; |
ff4700b0 AF |
209 | int flags; /* BP_* */ |
210 | QTAILQ_ENTRY(CPUWatchpoint) entry; | |
211 | } CPUWatchpoint; | |
212 | ||
a60f24b5 | 213 | struct KVMState; |
f7575c96 | 214 | struct kvm_run; |
a60f24b5 | 215 | |
8cd70437 AF |
216 | #define TB_JMP_CACHE_BITS 12 |
217 | #define TB_JMP_CACHE_SIZE (1 << TB_JMP_CACHE_BITS) | |
218 | ||
dd83b06a AF |
219 | /** |
220 | * CPUState: | |
55e5c285 | 221 | * @cpu_index: CPU index (informative). |
ce3960eb AF |
222 | * @nr_cores: Number of cores within this CPU package. |
223 | * @nr_threads: Number of threads within this CPU. | |
1b1ed8dc | 224 | * @numa_node: NUMA node this CPU is belonging to. |
0d34282f | 225 | * @host_tid: Host thread ID. |
0315c31c | 226 | * @running: #true if CPU is currently running (usermode). |
61a46217 | 227 | * @created: Indicates whether the CPU thread has been successfully created. |
259186a7 AF |
228 | * @interrupt_request: Indicates a pending interrupt request. |
229 | * @halted: Nonzero if the CPU is in suspended state. | |
4fdeee7c | 230 | * @stop: Indicates a pending stop request. |
f324e766 | 231 | * @stopped: Indicates the CPU has been artificially stopped. |
bac05aa9 | 232 | * @crash_occurred: Indicates the OS reported a crash (panic) for this CPU |
378df4b2 PM |
233 | * @tcg_exit_req: Set to force TCG to stop executing linked TBs for this |
234 | * CPU and return to its top level loop. | |
ed2803da | 235 | * @singlestep_enabled: Flags for single-stepping. |
efee7340 | 236 | * @icount_extra: Instructions until next timer event. |
28ecfd7a AF |
237 | * @icount_decr: Number of cycles left, with interrupt flag in high bit. |
238 | * This allows a single read-compare-cbranch-write sequence to test | |
239 | * for both decrementer underflow and exceptions. | |
414b15c9 PB |
240 | * @can_do_io: Nonzero if memory-mapped IO is safe. Deterministic execution |
241 | * requires that IO only be performed on the last instruction of a TB | |
242 | * so that interrupts take effect immediately. | |
32857f4d PM |
243 | * @cpu_ases: Pointer to array of CPUAddressSpaces (which define the |
244 | * AddressSpaces this CPU has) | |
12ebc9a7 | 245 | * @num_ases: number of CPUAddressSpaces in @cpu_ases |
32857f4d PM |
246 | * @as: Pointer to the first AddressSpace, for the convenience of targets which |
247 | * only have a single AddressSpace | |
c05efcb1 | 248 | * @env_ptr: Pointer to subclass-specific CPUArchState field. |
d77953b9 | 249 | * @current_tb: Currently executing TB. |
eac8b355 | 250 | * @gdb_regs: Additional GDB registers. |
a0e372f0 | 251 | * @gdb_num_regs: Number of total registers accessible to GDB. |
35143f01 | 252 | * @gdb_num_g_regs: Number of registers in GDB 'g' packets. |
182735ef | 253 | * @next_cpu: Next CPU sharing TB cache. |
0429a971 | 254 | * @opaque: User data. |
93afeade AF |
255 | * @mem_io_pc: Host Program Counter at which the memory was accessed. |
256 | * @mem_io_vaddr: Target virtual address at which the memory was accessed. | |
8737c51c | 257 | * @kvm_fd: vCPU file descriptor for KVM. |
376692b9 PB |
258 | * @work_mutex: Lock to prevent multiple access to queued_work_*. |
259 | * @queued_work_first: First asynchronous work pending. | |
dd83b06a AF |
260 | * |
261 | * State of one CPU core or thread. | |
262 | */ | |
263 | struct CPUState { | |
264 | /*< private >*/ | |
961f8395 | 265 | DeviceState parent_obj; |
dd83b06a AF |
266 | /*< public >*/ |
267 | ||
ce3960eb AF |
268 | int nr_cores; |
269 | int nr_threads; | |
1b1ed8dc | 270 | int numa_node; |
ce3960eb | 271 | |
814e612e | 272 | struct QemuThread *thread; |
bcba2a72 AF |
273 | #ifdef _WIN32 |
274 | HANDLE hThread; | |
275 | #endif | |
9f09e18a | 276 | int thread_id; |
0d34282f | 277 | uint32_t host_tid; |
0315c31c | 278 | bool running; |
f5c121b8 | 279 | struct QemuCond *halt_cond; |
216fc9a4 | 280 | bool thread_kicked; |
61a46217 | 281 | bool created; |
4fdeee7c | 282 | bool stop; |
f324e766 | 283 | bool stopped; |
bac05aa9 | 284 | bool crash_occurred; |
e0c38211 | 285 | bool exit_request; |
259186a7 | 286 | uint32_t interrupt_request; |
ed2803da | 287 | int singlestep_enabled; |
efee7340 | 288 | int64_t icount_extra; |
6f03bef0 | 289 | sigjmp_buf jmp_env; |
bcba2a72 | 290 | |
376692b9 PB |
291 | QemuMutex work_mutex; |
292 | struct qemu_work_item *queued_work_first, *queued_work_last; | |
293 | ||
32857f4d | 294 | CPUAddressSpace *cpu_ases; |
12ebc9a7 | 295 | int num_ases; |
09daed84 | 296 | AddressSpace *as; |
09daed84 | 297 | |
c05efcb1 | 298 | void *env_ptr; /* CPUArchState */ |
d77953b9 | 299 | struct TranslationBlock *current_tb; |
8cd70437 | 300 | struct TranslationBlock *tb_jmp_cache[TB_JMP_CACHE_SIZE]; |
eac8b355 | 301 | struct GDBRegisterState *gdb_regs; |
a0e372f0 | 302 | int gdb_num_regs; |
35143f01 | 303 | int gdb_num_g_regs; |
bdc44640 | 304 | QTAILQ_ENTRY(CPUState) node; |
d77953b9 | 305 | |
f0c3c505 AF |
306 | /* ice debug support */ |
307 | QTAILQ_HEAD(breakpoints_head, CPUBreakpoint) breakpoints; | |
308 | ||
ff4700b0 AF |
309 | QTAILQ_HEAD(watchpoints_head, CPUWatchpoint) watchpoints; |
310 | CPUWatchpoint *watchpoint_hit; | |
311 | ||
0429a971 AF |
312 | void *opaque; |
313 | ||
93afeade AF |
314 | /* In order to avoid passing too many arguments to the MMIO helpers, |
315 | * we store some rarely used information in the CPU context. | |
316 | */ | |
317 | uintptr_t mem_io_pc; | |
318 | vaddr mem_io_vaddr; | |
319 | ||
8737c51c | 320 | int kvm_fd; |
20d695a9 | 321 | bool kvm_vcpu_dirty; |
a60f24b5 | 322 | struct KVMState *kvm_state; |
f7575c96 | 323 | struct kvm_run *kvm_run; |
8737c51c | 324 | |
f5df5baf | 325 | /* TODO Move common fields from CPUArchState here. */ |
55e5c285 | 326 | int cpu_index; /* used by alpha TCG */ |
259186a7 | 327 | uint32_t halted; /* used by alpha, cris, ppc TCG */ |
28ecfd7a AF |
328 | union { |
329 | uint32_t u32; | |
330 | icount_decr_u16 u16; | |
331 | } icount_decr; | |
99df7dce | 332 | uint32_t can_do_io; |
27103424 | 333 | int32_t exception_index; /* used by m68k TCG */ |
7e4fb26d | 334 | |
2adcc85d JH |
335 | /* Used to keep track of an outstanding cpu throttle thread for migration |
336 | * autoconverge | |
337 | */ | |
338 | bool throttle_thread_scheduled; | |
339 | ||
7e4fb26d RH |
340 | /* Note that this is accessed at the start of every TB via a negative |
341 | offset from AREG0. Leave this field at the end so as to make the | |
342 | (absolute value) offset as small as possible. This reduces code | |
343 | size, especially for hosts without large memory offsets. */ | |
e0c38211 | 344 | uint32_t tcg_exit_req; |
dd83b06a AF |
345 | }; |
346 | ||
bdc44640 AF |
347 | QTAILQ_HEAD(CPUTailQ, CPUState); |
348 | extern struct CPUTailQ cpus; | |
349 | #define CPU_NEXT(cpu) QTAILQ_NEXT(cpu, node) | |
350 | #define CPU_FOREACH(cpu) QTAILQ_FOREACH(cpu, &cpus, node) | |
351 | #define CPU_FOREACH_SAFE(cpu, next_cpu) \ | |
352 | QTAILQ_FOREACH_SAFE(cpu, &cpus, node, next_cpu) | |
8487d123 BR |
353 | #define CPU_FOREACH_REVERSE(cpu) \ |
354 | QTAILQ_FOREACH_REVERSE(cpu, &cpus, CPUTailQ, node) | |
bdc44640 | 355 | #define first_cpu QTAILQ_FIRST(&cpus) |
182735ef | 356 | |
f240eb6f | 357 | extern __thread CPUState *current_cpu; |
4917cf44 | 358 | |
444d5590 AF |
359 | /** |
360 | * cpu_paging_enabled: | |
361 | * @cpu: The CPU whose state is to be inspected. | |
362 | * | |
363 | * Returns: %true if paging is enabled, %false otherwise. | |
364 | */ | |
365 | bool cpu_paging_enabled(const CPUState *cpu); | |
366 | ||
a23bbfda AF |
367 | /** |
368 | * cpu_get_memory_mapping: | |
369 | * @cpu: The CPU whose memory mappings are to be obtained. | |
370 | * @list: Where to write the memory mappings to. | |
371 | * @errp: Pointer for reporting an #Error. | |
372 | */ | |
373 | void cpu_get_memory_mapping(CPUState *cpu, MemoryMappingList *list, | |
374 | Error **errp); | |
375 | ||
c72bf468 JF |
376 | /** |
377 | * cpu_write_elf64_note: | |
378 | * @f: pointer to a function that writes memory to a file | |
379 | * @cpu: The CPU whose memory is to be dumped | |
380 | * @cpuid: ID number of the CPU | |
381 | * @opaque: pointer to the CPUState struct | |
382 | */ | |
383 | int cpu_write_elf64_note(WriteCoreDumpFunction f, CPUState *cpu, | |
384 | int cpuid, void *opaque); | |
385 | ||
386 | /** | |
387 | * cpu_write_elf64_qemunote: | |
388 | * @f: pointer to a function that writes memory to a file | |
389 | * @cpu: The CPU whose memory is to be dumped | |
390 | * @cpuid: ID number of the CPU | |
391 | * @opaque: pointer to the CPUState struct | |
392 | */ | |
393 | int cpu_write_elf64_qemunote(WriteCoreDumpFunction f, CPUState *cpu, | |
394 | void *opaque); | |
395 | ||
396 | /** | |
397 | * cpu_write_elf32_note: | |
398 | * @f: pointer to a function that writes memory to a file | |
399 | * @cpu: The CPU whose memory is to be dumped | |
400 | * @cpuid: ID number of the CPU | |
401 | * @opaque: pointer to the CPUState struct | |
402 | */ | |
403 | int cpu_write_elf32_note(WriteCoreDumpFunction f, CPUState *cpu, | |
404 | int cpuid, void *opaque); | |
405 | ||
406 | /** | |
407 | * cpu_write_elf32_qemunote: | |
408 | * @f: pointer to a function that writes memory to a file | |
409 | * @cpu: The CPU whose memory is to be dumped | |
410 | * @cpuid: ID number of the CPU | |
411 | * @opaque: pointer to the CPUState struct | |
412 | */ | |
413 | int cpu_write_elf32_qemunote(WriteCoreDumpFunction f, CPUState *cpu, | |
414 | void *opaque); | |
dd83b06a | 415 | |
878096ee AF |
416 | /** |
417 | * CPUDumpFlags: | |
418 | * @CPU_DUMP_CODE: | |
419 | * @CPU_DUMP_FPU: dump FPU register state, not just integer | |
420 | * @CPU_DUMP_CCOP: dump info about TCG QEMU's condition code optimization state | |
421 | */ | |
422 | enum CPUDumpFlags { | |
423 | CPU_DUMP_CODE = 0x00010000, | |
424 | CPU_DUMP_FPU = 0x00020000, | |
425 | CPU_DUMP_CCOP = 0x00040000, | |
426 | }; | |
427 | ||
428 | /** | |
429 | * cpu_dump_state: | |
430 | * @cpu: The CPU whose state is to be dumped. | |
431 | * @f: File to dump to. | |
432 | * @cpu_fprintf: Function to dump with. | |
433 | * @flags: Flags what to dump. | |
434 | * | |
435 | * Dumps CPU state. | |
436 | */ | |
437 | void cpu_dump_state(CPUState *cpu, FILE *f, fprintf_function cpu_fprintf, | |
438 | int flags); | |
439 | ||
440 | /** | |
441 | * cpu_dump_statistics: | |
442 | * @cpu: The CPU whose state is to be dumped. | |
443 | * @f: File to dump to. | |
444 | * @cpu_fprintf: Function to dump with. | |
445 | * @flags: Flags what to dump. | |
446 | * | |
447 | * Dumps CPU statistics. | |
448 | */ | |
449 | void cpu_dump_statistics(CPUState *cpu, FILE *f, fprintf_function cpu_fprintf, | |
450 | int flags); | |
451 | ||
00b941e5 | 452 | #ifndef CONFIG_USER_ONLY |
1dc6fb1f PM |
453 | /** |
454 | * cpu_get_phys_page_attrs_debug: | |
455 | * @cpu: The CPU to obtain the physical page address for. | |
456 | * @addr: The virtual address. | |
457 | * @attrs: Updated on return with the memory transaction attributes to use | |
458 | * for this access. | |
459 | * | |
460 | * Obtains the physical page corresponding to a virtual one, together | |
461 | * with the corresponding memory transaction attributes to use for the access. | |
462 | * Use it only for debugging because no protection checks are done. | |
463 | * | |
464 | * Returns: Corresponding physical page address or -1 if no page found. | |
465 | */ | |
466 | static inline hwaddr cpu_get_phys_page_attrs_debug(CPUState *cpu, vaddr addr, | |
467 | MemTxAttrs *attrs) | |
468 | { | |
469 | CPUClass *cc = CPU_GET_CLASS(cpu); | |
470 | ||
471 | if (cc->get_phys_page_attrs_debug) { | |
472 | return cc->get_phys_page_attrs_debug(cpu, addr, attrs); | |
473 | } | |
474 | /* Fallback for CPUs which don't implement the _attrs_ hook */ | |
475 | *attrs = MEMTXATTRS_UNSPECIFIED; | |
476 | return cc->get_phys_page_debug(cpu, addr); | |
477 | } | |
478 | ||
00b941e5 AF |
479 | /** |
480 | * cpu_get_phys_page_debug: | |
481 | * @cpu: The CPU to obtain the physical page address for. | |
482 | * @addr: The virtual address. | |
483 | * | |
484 | * Obtains the physical page corresponding to a virtual one. | |
485 | * Use it only for debugging because no protection checks are done. | |
486 | * | |
487 | * Returns: Corresponding physical page address or -1 if no page found. | |
488 | */ | |
489 | static inline hwaddr cpu_get_phys_page_debug(CPUState *cpu, vaddr addr) | |
490 | { | |
1dc6fb1f | 491 | MemTxAttrs attrs = {}; |
00b941e5 | 492 | |
1dc6fb1f | 493 | return cpu_get_phys_page_attrs_debug(cpu, addr, &attrs); |
00b941e5 AF |
494 | } |
495 | #endif | |
496 | ||
dd83b06a AF |
497 | /** |
498 | * cpu_reset: | |
499 | * @cpu: The CPU whose state is to be reset. | |
500 | */ | |
501 | void cpu_reset(CPUState *cpu); | |
502 | ||
2b8c2754 AF |
503 | /** |
504 | * cpu_class_by_name: | |
505 | * @typename: The CPU base type. | |
506 | * @cpu_model: The model string without any parameters. | |
507 | * | |
508 | * Looks up a CPU #ObjectClass matching name @cpu_model. | |
509 | * | |
510 | * Returns: A #CPUClass or %NULL if not matching class is found. | |
511 | */ | |
512 | ObjectClass *cpu_class_by_name(const char *typename, const char *cpu_model); | |
513 | ||
9262685b AF |
514 | /** |
515 | * cpu_generic_init: | |
516 | * @typename: The CPU base type. | |
517 | * @cpu_model: The model string including optional parameters. | |
518 | * | |
519 | * Instantiates a CPU, processes optional parameters and realizes the CPU. | |
520 | * | |
521 | * Returns: A #CPUState or %NULL if an error occurred. | |
522 | */ | |
523 | CPUState *cpu_generic_init(const char *typename, const char *cpu_model); | |
524 | ||
3993c6bd | 525 | /** |
8c2e1b00 | 526 | * cpu_has_work: |
3993c6bd AF |
527 | * @cpu: The vCPU to check. |
528 | * | |
529 | * Checks whether the CPU has work to do. | |
530 | * | |
531 | * Returns: %true if the CPU has work, %false otherwise. | |
532 | */ | |
8c2e1b00 AF |
533 | static inline bool cpu_has_work(CPUState *cpu) |
534 | { | |
535 | CPUClass *cc = CPU_GET_CLASS(cpu); | |
536 | ||
537 | g_assert(cc->has_work); | |
538 | return cc->has_work(cpu); | |
539 | } | |
3993c6bd | 540 | |
60e82579 AF |
541 | /** |
542 | * qemu_cpu_is_self: | |
543 | * @cpu: The vCPU to check against. | |
544 | * | |
545 | * Checks whether the caller is executing on the vCPU thread. | |
546 | * | |
547 | * Returns: %true if called from @cpu's thread, %false otherwise. | |
548 | */ | |
549 | bool qemu_cpu_is_self(CPUState *cpu); | |
550 | ||
c08d7424 AF |
551 | /** |
552 | * qemu_cpu_kick: | |
553 | * @cpu: The vCPU to kick. | |
554 | * | |
555 | * Kicks @cpu's thread. | |
556 | */ | |
557 | void qemu_cpu_kick(CPUState *cpu); | |
558 | ||
2fa45344 AF |
559 | /** |
560 | * cpu_is_stopped: | |
561 | * @cpu: The CPU to check. | |
562 | * | |
563 | * Checks whether the CPU is stopped. | |
564 | * | |
565 | * Returns: %true if run state is not running or if artificially stopped; | |
566 | * %false otherwise. | |
567 | */ | |
568 | bool cpu_is_stopped(CPUState *cpu); | |
569 | ||
f100f0b3 AF |
570 | /** |
571 | * run_on_cpu: | |
572 | * @cpu: The vCPU to run on. | |
573 | * @func: The function to be executed. | |
574 | * @data: Data to pass to the function. | |
575 | * | |
576 | * Schedules the function @func for execution on the vCPU @cpu. | |
577 | */ | |
578 | void run_on_cpu(CPUState *cpu, void (*func)(void *data), void *data); | |
579 | ||
3c02270d CV |
580 | /** |
581 | * async_run_on_cpu: | |
582 | * @cpu: The vCPU to run on. | |
583 | * @func: The function to be executed. | |
584 | * @data: Data to pass to the function. | |
585 | * | |
586 | * Schedules the function @func for execution on the vCPU @cpu asynchronously. | |
587 | */ | |
588 | void async_run_on_cpu(CPUState *cpu, void (*func)(void *data), void *data); | |
589 | ||
38d8f5c8 AF |
590 | /** |
591 | * qemu_get_cpu: | |
592 | * @index: The CPUState@cpu_index value of the CPU to obtain. | |
593 | * | |
594 | * Gets a CPU matching @index. | |
595 | * | |
596 | * Returns: The CPU or %NULL if there is no matching CPU. | |
597 | */ | |
598 | CPUState *qemu_get_cpu(int index); | |
599 | ||
69e5ff06 IM |
600 | /** |
601 | * cpu_exists: | |
602 | * @id: Guest-exposed CPU ID to lookup. | |
603 | * | |
604 | * Search for CPU with specified ID. | |
605 | * | |
606 | * Returns: %true - CPU is found, %false - CPU isn't found. | |
607 | */ | |
608 | bool cpu_exists(int64_t id); | |
609 | ||
2adcc85d JH |
610 | /** |
611 | * cpu_throttle_set: | |
612 | * @new_throttle_pct: Percent of sleep time. Valid range is 1 to 99. | |
613 | * | |
614 | * Throttles all vcpus by forcing them to sleep for the given percentage of | |
615 | * time. A throttle_percentage of 25 corresponds to a 75% duty cycle roughly. | |
616 | * (example: 10ms sleep for every 30ms awake). | |
617 | * | |
618 | * cpu_throttle_set can be called as needed to adjust new_throttle_pct. | |
619 | * Once the throttling starts, it will remain in effect until cpu_throttle_stop | |
620 | * is called. | |
621 | */ | |
622 | void cpu_throttle_set(int new_throttle_pct); | |
623 | ||
624 | /** | |
625 | * cpu_throttle_stop: | |
626 | * | |
627 | * Stops the vcpu throttling started by cpu_throttle_set. | |
628 | */ | |
629 | void cpu_throttle_stop(void); | |
630 | ||
631 | /** | |
632 | * cpu_throttle_active: | |
633 | * | |
634 | * Returns: %true if the vcpus are currently being throttled, %false otherwise. | |
635 | */ | |
636 | bool cpu_throttle_active(void); | |
637 | ||
638 | /** | |
639 | * cpu_throttle_get_percentage: | |
640 | * | |
641 | * Returns the vcpu throttle percentage. See cpu_throttle_set for details. | |
642 | * | |
643 | * Returns: The throttle percentage in range 1 to 99. | |
644 | */ | |
645 | int cpu_throttle_get_percentage(void); | |
646 | ||
c3affe56 AF |
647 | #ifndef CONFIG_USER_ONLY |
648 | ||
649 | typedef void (*CPUInterruptHandler)(CPUState *, int); | |
650 | ||
651 | extern CPUInterruptHandler cpu_interrupt_handler; | |
652 | ||
653 | /** | |
654 | * cpu_interrupt: | |
655 | * @cpu: The CPU to set an interrupt on. | |
656 | * @mask: The interupts to set. | |
657 | * | |
658 | * Invokes the interrupt handler. | |
659 | */ | |
660 | static inline void cpu_interrupt(CPUState *cpu, int mask) | |
661 | { | |
662 | cpu_interrupt_handler(cpu, mask); | |
663 | } | |
664 | ||
665 | #else /* USER_ONLY */ | |
666 | ||
667 | void cpu_interrupt(CPUState *cpu, int mask); | |
668 | ||
669 | #endif /* USER_ONLY */ | |
670 | ||
93e22326 | 671 | #ifdef CONFIG_SOFTMMU |
c658b94f AF |
672 | static inline void cpu_unassigned_access(CPUState *cpu, hwaddr addr, |
673 | bool is_write, bool is_exec, | |
674 | int opaque, unsigned size) | |
675 | { | |
676 | CPUClass *cc = CPU_GET_CLASS(cpu); | |
677 | ||
678 | if (cc->do_unassigned_access) { | |
679 | cc->do_unassigned_access(cpu, addr, is_write, is_exec, opaque, size); | |
680 | } | |
681 | } | |
682 | ||
93e22326 PB |
683 | static inline void cpu_unaligned_access(CPUState *cpu, vaddr addr, |
684 | int is_write, int is_user, | |
685 | uintptr_t retaddr) | |
686 | { | |
687 | CPUClass *cc = CPU_GET_CLASS(cpu); | |
688 | ||
e7ae771f | 689 | cc->do_unaligned_access(cpu, addr, is_write, is_user, retaddr); |
93e22326 | 690 | } |
c658b94f AF |
691 | #endif |
692 | ||
2991b890 PC |
693 | /** |
694 | * cpu_set_pc: | |
695 | * @cpu: The CPU to set the program counter for. | |
696 | * @addr: Program counter value. | |
697 | * | |
698 | * Sets the program counter for a CPU. | |
699 | */ | |
700 | static inline void cpu_set_pc(CPUState *cpu, vaddr addr) | |
701 | { | |
702 | CPUClass *cc = CPU_GET_CLASS(cpu); | |
703 | ||
704 | cc->set_pc(cpu, addr); | |
705 | } | |
706 | ||
d8ed887b AF |
707 | /** |
708 | * cpu_reset_interrupt: | |
709 | * @cpu: The CPU to clear the interrupt on. | |
710 | * @mask: The interrupt mask to clear. | |
711 | * | |
712 | * Resets interrupts on the vCPU @cpu. | |
713 | */ | |
714 | void cpu_reset_interrupt(CPUState *cpu, int mask); | |
715 | ||
60a3e17a AF |
716 | /** |
717 | * cpu_exit: | |
718 | * @cpu: The CPU to exit. | |
719 | * | |
720 | * Requests the CPU @cpu to exit execution. | |
721 | */ | |
722 | void cpu_exit(CPUState *cpu); | |
723 | ||
2993683b IM |
724 | /** |
725 | * cpu_resume: | |
726 | * @cpu: The CPU to resume. | |
727 | * | |
728 | * Resumes CPU, i.e. puts CPU into runnable state. | |
729 | */ | |
730 | void cpu_resume(CPUState *cpu); | |
dd83b06a | 731 | |
c643bed9 AF |
732 | /** |
733 | * qemu_init_vcpu: | |
734 | * @cpu: The vCPU to initialize. | |
735 | * | |
736 | * Initializes a vCPU. | |
737 | */ | |
738 | void qemu_init_vcpu(CPUState *cpu); | |
739 | ||
3825b28f AF |
740 | #define SSTEP_ENABLE 0x1 /* Enable simulated HW single stepping */ |
741 | #define SSTEP_NOIRQ 0x2 /* Do not use IRQ while single stepping */ | |
742 | #define SSTEP_NOTIMER 0x4 /* Do not Timers while single stepping */ | |
743 | ||
744 | /** | |
745 | * cpu_single_step: | |
746 | * @cpu: CPU to the flags for. | |
747 | * @enabled: Flags to enable. | |
748 | * | |
749 | * Enables or disables single-stepping for @cpu. | |
750 | */ | |
751 | void cpu_single_step(CPUState *cpu, int enabled); | |
752 | ||
b3310ab3 AF |
753 | /* Breakpoint/watchpoint flags */ |
754 | #define BP_MEM_READ 0x01 | |
755 | #define BP_MEM_WRITE 0x02 | |
756 | #define BP_MEM_ACCESS (BP_MEM_READ | BP_MEM_WRITE) | |
757 | #define BP_STOP_BEFORE_ACCESS 0x04 | |
08225676 | 758 | /* 0x08 currently unused */ |
b3310ab3 AF |
759 | #define BP_GDB 0x10 |
760 | #define BP_CPU 0x20 | |
b933066a | 761 | #define BP_ANY (BP_GDB | BP_CPU) |
08225676 PM |
762 | #define BP_WATCHPOINT_HIT_READ 0x40 |
763 | #define BP_WATCHPOINT_HIT_WRITE 0x80 | |
764 | #define BP_WATCHPOINT_HIT (BP_WATCHPOINT_HIT_READ | BP_WATCHPOINT_HIT_WRITE) | |
b3310ab3 AF |
765 | |
766 | int cpu_breakpoint_insert(CPUState *cpu, vaddr pc, int flags, | |
767 | CPUBreakpoint **breakpoint); | |
768 | int cpu_breakpoint_remove(CPUState *cpu, vaddr pc, int flags); | |
769 | void cpu_breakpoint_remove_by_ref(CPUState *cpu, CPUBreakpoint *breakpoint); | |
770 | void cpu_breakpoint_remove_all(CPUState *cpu, int mask); | |
771 | ||
b933066a RH |
772 | /* Return true if PC matches an installed breakpoint. */ |
773 | static inline bool cpu_breakpoint_test(CPUState *cpu, vaddr pc, int mask) | |
774 | { | |
775 | CPUBreakpoint *bp; | |
776 | ||
777 | if (unlikely(!QTAILQ_EMPTY(&cpu->breakpoints))) { | |
778 | QTAILQ_FOREACH(bp, &cpu->breakpoints, entry) { | |
779 | if (bp->pc == pc && (bp->flags & mask)) { | |
780 | return true; | |
781 | } | |
782 | } | |
783 | } | |
784 | return false; | |
785 | } | |
786 | ||
75a34036 AF |
787 | int cpu_watchpoint_insert(CPUState *cpu, vaddr addr, vaddr len, |
788 | int flags, CPUWatchpoint **watchpoint); | |
789 | int cpu_watchpoint_remove(CPUState *cpu, vaddr addr, | |
790 | vaddr len, int flags); | |
791 | void cpu_watchpoint_remove_by_ref(CPUState *cpu, CPUWatchpoint *watchpoint); | |
792 | void cpu_watchpoint_remove_all(CPUState *cpu, int mask); | |
793 | ||
a47dddd7 AF |
794 | void QEMU_NORETURN cpu_abort(CPUState *cpu, const char *fmt, ...) |
795 | GCC_FMT_ATTR(2, 3); | |
b7bca733 | 796 | void cpu_exec_exit(CPUState *cpu); |
a47dddd7 | 797 | |
1a1562f5 AF |
798 | #ifdef CONFIG_SOFTMMU |
799 | extern const struct VMStateDescription vmstate_cpu_common; | |
800 | #else | |
801 | #define vmstate_cpu_common vmstate_dummy | |
802 | #endif | |
803 | ||
804 | #define VMSTATE_CPU() { \ | |
805 | .name = "parent_obj", \ | |
806 | .size = sizeof(CPUState), \ | |
807 | .vmsd = &vmstate_cpu_common, \ | |
808 | .flags = VMS_STRUCT, \ | |
809 | .offset = 0, \ | |
810 | } | |
811 | ||
dd83b06a | 812 | #endif |