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dd83b06a AF |
1 | /* |
2 | * QEMU CPU model | |
3 | * | |
4 | * Copyright (c) 2012 SUSE LINUX Products GmbH | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or | |
7 | * modify it under the terms of the GNU General Public License | |
8 | * as published by the Free Software Foundation; either version 2 | |
9 | * of the License, or (at your option) any later version. | |
10 | * | |
11 | * This program is distributed in the hope that it will be useful, | |
12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
14 | * GNU General Public License for more details. | |
15 | * | |
16 | * You should have received a copy of the GNU General Public License | |
17 | * along with this program; if not, see | |
18 | * <http://www.gnu.org/licenses/gpl-2.0.html> | |
19 | */ | |
20 | #ifndef QEMU_CPU_H | |
21 | #define QEMU_CPU_H | |
22 | ||
961f8395 | 23 | #include "hw/qdev-core.h" |
37b9de46 | 24 | #include "disas/bfd.h" |
c658b94f | 25 | #include "exec/hwaddr.h" |
66b9b43c | 26 | #include "exec/memattrs.h" |
48151859 | 27 | #include "qemu/bitmap.h" |
bdc44640 | 28 | #include "qemu/queue.h" |
1de7afc9 | 29 | #include "qemu/thread.h" |
48151859 | 30 | #include "trace/generated-events.h" |
dd83b06a | 31 | |
b5ba1cc6 QN |
32 | typedef int (*WriteCoreDumpFunction)(const void *buf, size_t size, |
33 | void *opaque); | |
c72bf468 | 34 | |
577f42c0 AF |
35 | /** |
36 | * vaddr: | |
37 | * Type wide enough to contain any #target_ulong virtual address. | |
38 | */ | |
39 | typedef uint64_t vaddr; | |
40 | #define VADDR_PRId PRId64 | |
41 | #define VADDR_PRIu PRIu64 | |
42 | #define VADDR_PRIo PRIo64 | |
43 | #define VADDR_PRIx PRIx64 | |
44 | #define VADDR_PRIX PRIX64 | |
45 | #define VADDR_MAX UINT64_MAX | |
46 | ||
dd83b06a AF |
47 | /** |
48 | * SECTION:cpu | |
49 | * @section_id: QEMU-cpu | |
50 | * @title: CPU Class | |
51 | * @short_description: Base class for all CPUs | |
52 | */ | |
53 | ||
54 | #define TYPE_CPU "cpu" | |
55 | ||
0d6d1ab4 AF |
56 | /* Since this macro is used a lot in hot code paths and in conjunction with |
57 | * FooCPU *foo_env_get_cpu(), we deviate from usual QOM practice by using | |
58 | * an unchecked cast. | |
59 | */ | |
60 | #define CPU(obj) ((CPUState *)(obj)) | |
61 | ||
dd83b06a AF |
62 | #define CPU_CLASS(class) OBJECT_CLASS_CHECK(CPUClass, (class), TYPE_CPU) |
63 | #define CPU_GET_CLASS(obj) OBJECT_GET_CLASS(CPUClass, (obj), TYPE_CPU) | |
64 | ||
b35399bb SS |
65 | typedef enum MMUAccessType { |
66 | MMU_DATA_LOAD = 0, | |
67 | MMU_DATA_STORE = 1, | |
68 | MMU_INST_FETCH = 2 | |
69 | } MMUAccessType; | |
70 | ||
568496c0 | 71 | typedef struct CPUWatchpoint CPUWatchpoint; |
dd83b06a | 72 | |
c658b94f AF |
73 | typedef void (*CPUUnassignedAccess)(CPUState *cpu, hwaddr addr, |
74 | bool is_write, bool is_exec, int opaque, | |
75 | unsigned size); | |
76 | ||
bdf7ae5b AF |
77 | struct TranslationBlock; |
78 | ||
dd83b06a AF |
79 | /** |
80 | * CPUClass: | |
2b8c2754 AF |
81 | * @class_by_name: Callback to map -cpu command line model name to an |
82 | * instantiatable CPU type. | |
94a444b2 | 83 | * @parse_features: Callback to parse command line arguments. |
f5df5baf | 84 | * @reset: Callback to reset the #CPUState to its initial state. |
91b1df8c | 85 | * @reset_dump_flags: #CPUDumpFlags to use for reset logging. |
8c2e1b00 | 86 | * @has_work: Callback for checking if there is work to do. |
97a8ea5a | 87 | * @do_interrupt: Callback for interrupt handling. |
c658b94f | 88 | * @do_unassigned_access: Callback for unassigned access handling. |
93e22326 PB |
89 | * @do_unaligned_access: Callback for unaligned access handling, if |
90 | * the target defines #ALIGNED_ONLY. | |
c08295d4 PM |
91 | * @virtio_is_big_endian: Callback to return %true if a CPU which supports |
92 | * runtime configurable endianness is currently big-endian. Non-configurable | |
93 | * CPUs can use the default implementation of this method. This method should | |
94 | * not be used by any callers other than the pre-1.0 virtio devices. | |
f3659eee | 95 | * @memory_rw_debug: Callback for GDB memory access. |
878096ee AF |
96 | * @dump_state: Callback for dumping state. |
97 | * @dump_statistics: Callback for dumping statistics. | |
997395d3 | 98 | * @get_arch_id: Callback for getting architecture-dependent CPU ID. |
444d5590 | 99 | * @get_paging_enabled: Callback for inquiring whether paging is enabled. |
a23bbfda | 100 | * @get_memory_mapping: Callback for obtaining the memory mappings. |
f45748f1 | 101 | * @set_pc: Callback for setting the Program Counter register. |
bdf7ae5b AF |
102 | * @synchronize_from_tb: Callback for synchronizing state from a TCG |
103 | * #TranslationBlock. | |
7510454e | 104 | * @handle_mmu_fault: Callback for handling an MMU fault. |
00b941e5 | 105 | * @get_phys_page_debug: Callback for obtaining a physical address. |
1dc6fb1f PM |
106 | * @get_phys_page_attrs_debug: Callback for obtaining a physical address and the |
107 | * associated memory transaction attributes to use for the access. | |
108 | * CPUs which use memory transaction attributes should implement this | |
109 | * instead of get_phys_page_debug. | |
d7f25a9e PM |
110 | * @asidx_from_attrs: Callback to return the CPU AddressSpace to use for |
111 | * a memory access with the specified memory transaction attributes. | |
5b50e790 AF |
112 | * @gdb_read_register: Callback for letting GDB read a register. |
113 | * @gdb_write_register: Callback for letting GDB write a register. | |
568496c0 SF |
114 | * @debug_check_watchpoint: Callback: return true if the architectural |
115 | * watchpoint whose address has matched should really fire. | |
86025ee4 | 116 | * @debug_excp_handler: Callback for handling debug exceptions. |
c08295d4 PM |
117 | * @write_elf64_note: Callback for writing a CPU-specific ELF note to a |
118 | * 64-bit VM coredump. | |
119 | * @write_elf32_qemunote: Callback for writing a CPU- and QEMU-specific ELF | |
120 | * note to a 32-bit VM coredump. | |
121 | * @write_elf32_note: Callback for writing a CPU-specific ELF note to a | |
122 | * 32-bit VM coredump. | |
123 | * @write_elf32_qemunote: Callback for writing a CPU- and QEMU-specific ELF | |
124 | * note to a 32-bit VM coredump. | |
b170fce3 | 125 | * @vmsd: State description for migration. |
a0e372f0 | 126 | * @gdb_num_core_regs: Number of core registers accessible to GDB. |
5b24c641 | 127 | * @gdb_core_xml_file: File name for core registers GDB XML description. |
2472b6c0 PM |
128 | * @gdb_stop_before_watchpoint: Indicates whether GDB expects the CPU to stop |
129 | * before the insn which triggers a watchpoint rather than after it. | |
b3820e6c DH |
130 | * @gdb_arch_name: Optional callback that returns the architecture name known |
131 | * to GDB. The caller must free the returned string with g_free. | |
cffe7b32 RH |
132 | * @cpu_exec_enter: Callback for cpu_exec preparation. |
133 | * @cpu_exec_exit: Callback for cpu_exec cleanup. | |
9585db68 | 134 | * @cpu_exec_interrupt: Callback for processing interrupts in cpu_exec. |
37b9de46 | 135 | * @disas_set_info: Setup architecture specific components of disassembly info |
dd83b06a AF |
136 | * |
137 | * Represents a CPU family or model. | |
138 | */ | |
139 | typedef struct CPUClass { | |
140 | /*< private >*/ | |
961f8395 | 141 | DeviceClass parent_class; |
dd83b06a AF |
142 | /*< public >*/ |
143 | ||
2b8c2754 | 144 | ObjectClass *(*class_by_name)(const char *cpu_model); |
62a48a2a | 145 | void (*parse_features)(const char *typename, char *str, Error **errp); |
2b8c2754 | 146 | |
dd83b06a | 147 | void (*reset)(CPUState *cpu); |
91b1df8c | 148 | int reset_dump_flags; |
8c2e1b00 | 149 | bool (*has_work)(CPUState *cpu); |
97a8ea5a | 150 | void (*do_interrupt)(CPUState *cpu); |
c658b94f | 151 | CPUUnassignedAccess do_unassigned_access; |
93e22326 | 152 | void (*do_unaligned_access)(CPUState *cpu, vaddr addr, |
b35399bb SS |
153 | MMUAccessType access_type, |
154 | int mmu_idx, uintptr_t retaddr); | |
bf7663c4 | 155 | bool (*virtio_is_big_endian)(CPUState *cpu); |
f3659eee AF |
156 | int (*memory_rw_debug)(CPUState *cpu, vaddr addr, |
157 | uint8_t *buf, int len, bool is_write); | |
878096ee AF |
158 | void (*dump_state)(CPUState *cpu, FILE *f, fprintf_function cpu_fprintf, |
159 | int flags); | |
160 | void (*dump_statistics)(CPUState *cpu, FILE *f, | |
161 | fprintf_function cpu_fprintf, int flags); | |
997395d3 | 162 | int64_t (*get_arch_id)(CPUState *cpu); |
444d5590 | 163 | bool (*get_paging_enabled)(const CPUState *cpu); |
a23bbfda AF |
164 | void (*get_memory_mapping)(CPUState *cpu, MemoryMappingList *list, |
165 | Error **errp); | |
f45748f1 | 166 | void (*set_pc)(CPUState *cpu, vaddr value); |
bdf7ae5b | 167 | void (*synchronize_from_tb)(CPUState *cpu, struct TranslationBlock *tb); |
7510454e AF |
168 | int (*handle_mmu_fault)(CPUState *cpu, vaddr address, int rw, |
169 | int mmu_index); | |
00b941e5 | 170 | hwaddr (*get_phys_page_debug)(CPUState *cpu, vaddr addr); |
1dc6fb1f PM |
171 | hwaddr (*get_phys_page_attrs_debug)(CPUState *cpu, vaddr addr, |
172 | MemTxAttrs *attrs); | |
d7f25a9e | 173 | int (*asidx_from_attrs)(CPUState *cpu, MemTxAttrs attrs); |
5b50e790 AF |
174 | int (*gdb_read_register)(CPUState *cpu, uint8_t *buf, int reg); |
175 | int (*gdb_write_register)(CPUState *cpu, uint8_t *buf, int reg); | |
568496c0 | 176 | bool (*debug_check_watchpoint)(CPUState *cpu, CPUWatchpoint *wp); |
86025ee4 | 177 | void (*debug_excp_handler)(CPUState *cpu); |
b170fce3 | 178 | |
c72bf468 JF |
179 | int (*write_elf64_note)(WriteCoreDumpFunction f, CPUState *cpu, |
180 | int cpuid, void *opaque); | |
181 | int (*write_elf64_qemunote)(WriteCoreDumpFunction f, CPUState *cpu, | |
182 | void *opaque); | |
183 | int (*write_elf32_note)(WriteCoreDumpFunction f, CPUState *cpu, | |
184 | int cpuid, void *opaque); | |
185 | int (*write_elf32_qemunote)(WriteCoreDumpFunction f, CPUState *cpu, | |
186 | void *opaque); | |
a0e372f0 AF |
187 | |
188 | const struct VMStateDescription *vmsd; | |
189 | int gdb_num_core_regs; | |
5b24c641 | 190 | const char *gdb_core_xml_file; |
b3820e6c | 191 | gchar * (*gdb_arch_name)(CPUState *cpu); |
2472b6c0 | 192 | bool gdb_stop_before_watchpoint; |
cffe7b32 RH |
193 | |
194 | void (*cpu_exec_enter)(CPUState *cpu); | |
195 | void (*cpu_exec_exit)(CPUState *cpu); | |
9585db68 | 196 | bool (*cpu_exec_interrupt)(CPUState *cpu, int interrupt_request); |
37b9de46 PC |
197 | |
198 | void (*disas_set_info)(CPUState *cpu, disassemble_info *info); | |
dd83b06a AF |
199 | } CPUClass; |
200 | ||
28ecfd7a AF |
201 | #ifdef HOST_WORDS_BIGENDIAN |
202 | typedef struct icount_decr_u16 { | |
203 | uint16_t high; | |
204 | uint16_t low; | |
205 | } icount_decr_u16; | |
206 | #else | |
207 | typedef struct icount_decr_u16 { | |
208 | uint16_t low; | |
209 | uint16_t high; | |
210 | } icount_decr_u16; | |
211 | #endif | |
212 | ||
f0c3c505 AF |
213 | typedef struct CPUBreakpoint { |
214 | vaddr pc; | |
215 | int flags; /* BP_* */ | |
216 | QTAILQ_ENTRY(CPUBreakpoint) entry; | |
217 | } CPUBreakpoint; | |
218 | ||
568496c0 | 219 | struct CPUWatchpoint { |
ff4700b0 | 220 | vaddr vaddr; |
05068c0d | 221 | vaddr len; |
08225676 | 222 | vaddr hitaddr; |
66b9b43c | 223 | MemTxAttrs hitattrs; |
ff4700b0 AF |
224 | int flags; /* BP_* */ |
225 | QTAILQ_ENTRY(CPUWatchpoint) entry; | |
568496c0 | 226 | }; |
ff4700b0 | 227 | |
a60f24b5 | 228 | struct KVMState; |
f7575c96 | 229 | struct kvm_run; |
a60f24b5 | 230 | |
8cd70437 AF |
231 | #define TB_JMP_CACHE_BITS 12 |
232 | #define TB_JMP_CACHE_SIZE (1 << TB_JMP_CACHE_BITS) | |
233 | ||
4b4629d9 | 234 | /* work queue */ |
e0eeb4a2 AB |
235 | typedef void (*run_on_cpu_func)(CPUState *cpu, void *data); |
236 | ||
4b4629d9 PB |
237 | struct qemu_work_item { |
238 | struct qemu_work_item *next; | |
e0eeb4a2 | 239 | run_on_cpu_func func; |
4b4629d9 PB |
240 | void *data; |
241 | int done; | |
242 | bool free; | |
243 | }; | |
244 | ||
dd83b06a AF |
245 | /** |
246 | * CPUState: | |
55e5c285 | 247 | * @cpu_index: CPU index (informative). |
ce3960eb AF |
248 | * @nr_cores: Number of cores within this CPU package. |
249 | * @nr_threads: Number of threads within this CPU. | |
1b1ed8dc | 250 | * @numa_node: NUMA node this CPU is belonging to. |
0d34282f | 251 | * @host_tid: Host thread ID. |
0315c31c | 252 | * @running: #true if CPU is currently running (usermode). |
61a46217 | 253 | * @created: Indicates whether the CPU thread has been successfully created. |
259186a7 AF |
254 | * @interrupt_request: Indicates a pending interrupt request. |
255 | * @halted: Nonzero if the CPU is in suspended state. | |
4fdeee7c | 256 | * @stop: Indicates a pending stop request. |
f324e766 | 257 | * @stopped: Indicates the CPU has been artificially stopped. |
4c055ab5 | 258 | * @unplug: Indicates a pending CPU unplug request. |
bac05aa9 | 259 | * @crash_occurred: Indicates the OS reported a crash (panic) for this CPU |
378df4b2 PM |
260 | * @tcg_exit_req: Set to force TCG to stop executing linked TBs for this |
261 | * CPU and return to its top level loop. | |
6f789be5 | 262 | * @tb_flushed: Indicates the translation buffer has been flushed. |
ed2803da | 263 | * @singlestep_enabled: Flags for single-stepping. |
efee7340 | 264 | * @icount_extra: Instructions until next timer event. |
28ecfd7a AF |
265 | * @icount_decr: Number of cycles left, with interrupt flag in high bit. |
266 | * This allows a single read-compare-cbranch-write sequence to test | |
267 | * for both decrementer underflow and exceptions. | |
414b15c9 PB |
268 | * @can_do_io: Nonzero if memory-mapped IO is safe. Deterministic execution |
269 | * requires that IO only be performed on the last instruction of a TB | |
270 | * so that interrupts take effect immediately. | |
32857f4d PM |
271 | * @cpu_ases: Pointer to array of CPUAddressSpaces (which define the |
272 | * AddressSpaces this CPU has) | |
12ebc9a7 | 273 | * @num_ases: number of CPUAddressSpaces in @cpu_ases |
32857f4d PM |
274 | * @as: Pointer to the first AddressSpace, for the convenience of targets which |
275 | * only have a single AddressSpace | |
c05efcb1 | 276 | * @env_ptr: Pointer to subclass-specific CPUArchState field. |
eac8b355 | 277 | * @gdb_regs: Additional GDB registers. |
a0e372f0 | 278 | * @gdb_num_regs: Number of total registers accessible to GDB. |
35143f01 | 279 | * @gdb_num_g_regs: Number of registers in GDB 'g' packets. |
182735ef | 280 | * @next_cpu: Next CPU sharing TB cache. |
0429a971 | 281 | * @opaque: User data. |
93afeade AF |
282 | * @mem_io_pc: Host Program Counter at which the memory was accessed. |
283 | * @mem_io_vaddr: Target virtual address at which the memory was accessed. | |
8737c51c | 284 | * @kvm_fd: vCPU file descriptor for KVM. |
376692b9 PB |
285 | * @work_mutex: Lock to prevent multiple access to queued_work_*. |
286 | * @queued_work_first: First asynchronous work pending. | |
48151859 | 287 | * @trace_dstate: Dynamic tracing state of events for this vCPU (bitmask). |
dd83b06a AF |
288 | * |
289 | * State of one CPU core or thread. | |
290 | */ | |
291 | struct CPUState { | |
292 | /*< private >*/ | |
961f8395 | 293 | DeviceState parent_obj; |
dd83b06a AF |
294 | /*< public >*/ |
295 | ||
ce3960eb AF |
296 | int nr_cores; |
297 | int nr_threads; | |
1b1ed8dc | 298 | int numa_node; |
ce3960eb | 299 | |
814e612e | 300 | struct QemuThread *thread; |
bcba2a72 AF |
301 | #ifdef _WIN32 |
302 | HANDLE hThread; | |
303 | #endif | |
9f09e18a | 304 | int thread_id; |
0d34282f | 305 | uint32_t host_tid; |
0315c31c | 306 | bool running; |
f5c121b8 | 307 | struct QemuCond *halt_cond; |
216fc9a4 | 308 | bool thread_kicked; |
61a46217 | 309 | bool created; |
4fdeee7c | 310 | bool stop; |
f324e766 | 311 | bool stopped; |
4c055ab5 | 312 | bool unplug; |
bac05aa9 | 313 | bool crash_occurred; |
e0c38211 | 314 | bool exit_request; |
6f789be5 | 315 | bool tb_flushed; |
259186a7 | 316 | uint32_t interrupt_request; |
ed2803da | 317 | int singlestep_enabled; |
efee7340 | 318 | int64_t icount_extra; |
6f03bef0 | 319 | sigjmp_buf jmp_env; |
bcba2a72 | 320 | |
376692b9 PB |
321 | QemuMutex work_mutex; |
322 | struct qemu_work_item *queued_work_first, *queued_work_last; | |
323 | ||
32857f4d | 324 | CPUAddressSpace *cpu_ases; |
12ebc9a7 | 325 | int num_ases; |
09daed84 | 326 | AddressSpace *as; |
6731d864 | 327 | MemoryRegion *memory; |
09daed84 | 328 | |
c05efcb1 | 329 | void *env_ptr; /* CPUArchState */ |
8cd70437 | 330 | struct TranslationBlock *tb_jmp_cache[TB_JMP_CACHE_SIZE]; |
eac8b355 | 331 | struct GDBRegisterState *gdb_regs; |
a0e372f0 | 332 | int gdb_num_regs; |
35143f01 | 333 | int gdb_num_g_regs; |
bdc44640 | 334 | QTAILQ_ENTRY(CPUState) node; |
d77953b9 | 335 | |
f0c3c505 AF |
336 | /* ice debug support */ |
337 | QTAILQ_HEAD(breakpoints_head, CPUBreakpoint) breakpoints; | |
338 | ||
ff4700b0 AF |
339 | QTAILQ_HEAD(watchpoints_head, CPUWatchpoint) watchpoints; |
340 | CPUWatchpoint *watchpoint_hit; | |
341 | ||
0429a971 AF |
342 | void *opaque; |
343 | ||
93afeade AF |
344 | /* In order to avoid passing too many arguments to the MMIO helpers, |
345 | * we store some rarely used information in the CPU context. | |
346 | */ | |
347 | uintptr_t mem_io_pc; | |
348 | vaddr mem_io_vaddr; | |
349 | ||
8737c51c | 350 | int kvm_fd; |
20d695a9 | 351 | bool kvm_vcpu_dirty; |
a60f24b5 | 352 | struct KVMState *kvm_state; |
f7575c96 | 353 | struct kvm_run *kvm_run; |
8737c51c | 354 | |
48151859 LV |
355 | /* Used for events with 'vcpu' and *without* the 'disabled' properties */ |
356 | DECLARE_BITMAP(trace_dstate, TRACE_VCPU_EVENT_COUNT); | |
357 | ||
f5df5baf | 358 | /* TODO Move common fields from CPUArchState here. */ |
55e5c285 | 359 | int cpu_index; /* used by alpha TCG */ |
259186a7 | 360 | uint32_t halted; /* used by alpha, cris, ppc TCG */ |
28ecfd7a AF |
361 | union { |
362 | uint32_t u32; | |
363 | icount_decr_u16 u16; | |
364 | } icount_decr; | |
99df7dce | 365 | uint32_t can_do_io; |
27103424 | 366 | int32_t exception_index; /* used by m68k TCG */ |
7e4fb26d | 367 | |
2adcc85d JH |
368 | /* Used to keep track of an outstanding cpu throttle thread for migration |
369 | * autoconverge | |
370 | */ | |
371 | bool throttle_thread_scheduled; | |
372 | ||
7e4fb26d RH |
373 | /* Note that this is accessed at the start of every TB via a negative |
374 | offset from AREG0. Leave this field at the end so as to make the | |
375 | (absolute value) offset as small as possible. This reduces code | |
376 | size, especially for hosts without large memory offsets. */ | |
e0c38211 | 377 | uint32_t tcg_exit_req; |
dd83b06a AF |
378 | }; |
379 | ||
bdc44640 AF |
380 | QTAILQ_HEAD(CPUTailQ, CPUState); |
381 | extern struct CPUTailQ cpus; | |
382 | #define CPU_NEXT(cpu) QTAILQ_NEXT(cpu, node) | |
383 | #define CPU_FOREACH(cpu) QTAILQ_FOREACH(cpu, &cpus, node) | |
384 | #define CPU_FOREACH_SAFE(cpu, next_cpu) \ | |
385 | QTAILQ_FOREACH_SAFE(cpu, &cpus, node, next_cpu) | |
8487d123 BR |
386 | #define CPU_FOREACH_REVERSE(cpu) \ |
387 | QTAILQ_FOREACH_REVERSE(cpu, &cpus, CPUTailQ, node) | |
bdc44640 | 388 | #define first_cpu QTAILQ_FIRST(&cpus) |
182735ef | 389 | |
f240eb6f | 390 | extern __thread CPUState *current_cpu; |
4917cf44 | 391 | |
444d5590 AF |
392 | /** |
393 | * cpu_paging_enabled: | |
394 | * @cpu: The CPU whose state is to be inspected. | |
395 | * | |
396 | * Returns: %true if paging is enabled, %false otherwise. | |
397 | */ | |
398 | bool cpu_paging_enabled(const CPUState *cpu); | |
399 | ||
a23bbfda AF |
400 | /** |
401 | * cpu_get_memory_mapping: | |
402 | * @cpu: The CPU whose memory mappings are to be obtained. | |
403 | * @list: Where to write the memory mappings to. | |
404 | * @errp: Pointer for reporting an #Error. | |
405 | */ | |
406 | void cpu_get_memory_mapping(CPUState *cpu, MemoryMappingList *list, | |
407 | Error **errp); | |
408 | ||
c72bf468 JF |
409 | /** |
410 | * cpu_write_elf64_note: | |
411 | * @f: pointer to a function that writes memory to a file | |
412 | * @cpu: The CPU whose memory is to be dumped | |
413 | * @cpuid: ID number of the CPU | |
414 | * @opaque: pointer to the CPUState struct | |
415 | */ | |
416 | int cpu_write_elf64_note(WriteCoreDumpFunction f, CPUState *cpu, | |
417 | int cpuid, void *opaque); | |
418 | ||
419 | /** | |
420 | * cpu_write_elf64_qemunote: | |
421 | * @f: pointer to a function that writes memory to a file | |
422 | * @cpu: The CPU whose memory is to be dumped | |
423 | * @cpuid: ID number of the CPU | |
424 | * @opaque: pointer to the CPUState struct | |
425 | */ | |
426 | int cpu_write_elf64_qemunote(WriteCoreDumpFunction f, CPUState *cpu, | |
427 | void *opaque); | |
428 | ||
429 | /** | |
430 | * cpu_write_elf32_note: | |
431 | * @f: pointer to a function that writes memory to a file | |
432 | * @cpu: The CPU whose memory is to be dumped | |
433 | * @cpuid: ID number of the CPU | |
434 | * @opaque: pointer to the CPUState struct | |
435 | */ | |
436 | int cpu_write_elf32_note(WriteCoreDumpFunction f, CPUState *cpu, | |
437 | int cpuid, void *opaque); | |
438 | ||
439 | /** | |
440 | * cpu_write_elf32_qemunote: | |
441 | * @f: pointer to a function that writes memory to a file | |
442 | * @cpu: The CPU whose memory is to be dumped | |
443 | * @cpuid: ID number of the CPU | |
444 | * @opaque: pointer to the CPUState struct | |
445 | */ | |
446 | int cpu_write_elf32_qemunote(WriteCoreDumpFunction f, CPUState *cpu, | |
447 | void *opaque); | |
dd83b06a | 448 | |
878096ee AF |
449 | /** |
450 | * CPUDumpFlags: | |
451 | * @CPU_DUMP_CODE: | |
452 | * @CPU_DUMP_FPU: dump FPU register state, not just integer | |
453 | * @CPU_DUMP_CCOP: dump info about TCG QEMU's condition code optimization state | |
454 | */ | |
455 | enum CPUDumpFlags { | |
456 | CPU_DUMP_CODE = 0x00010000, | |
457 | CPU_DUMP_FPU = 0x00020000, | |
458 | CPU_DUMP_CCOP = 0x00040000, | |
459 | }; | |
460 | ||
461 | /** | |
462 | * cpu_dump_state: | |
463 | * @cpu: The CPU whose state is to be dumped. | |
464 | * @f: File to dump to. | |
465 | * @cpu_fprintf: Function to dump with. | |
466 | * @flags: Flags what to dump. | |
467 | * | |
468 | * Dumps CPU state. | |
469 | */ | |
470 | void cpu_dump_state(CPUState *cpu, FILE *f, fprintf_function cpu_fprintf, | |
471 | int flags); | |
472 | ||
473 | /** | |
474 | * cpu_dump_statistics: | |
475 | * @cpu: The CPU whose state is to be dumped. | |
476 | * @f: File to dump to. | |
477 | * @cpu_fprintf: Function to dump with. | |
478 | * @flags: Flags what to dump. | |
479 | * | |
480 | * Dumps CPU statistics. | |
481 | */ | |
482 | void cpu_dump_statistics(CPUState *cpu, FILE *f, fprintf_function cpu_fprintf, | |
483 | int flags); | |
484 | ||
00b941e5 | 485 | #ifndef CONFIG_USER_ONLY |
1dc6fb1f PM |
486 | /** |
487 | * cpu_get_phys_page_attrs_debug: | |
488 | * @cpu: The CPU to obtain the physical page address for. | |
489 | * @addr: The virtual address. | |
490 | * @attrs: Updated on return with the memory transaction attributes to use | |
491 | * for this access. | |
492 | * | |
493 | * Obtains the physical page corresponding to a virtual one, together | |
494 | * with the corresponding memory transaction attributes to use for the access. | |
495 | * Use it only for debugging because no protection checks are done. | |
496 | * | |
497 | * Returns: Corresponding physical page address or -1 if no page found. | |
498 | */ | |
499 | static inline hwaddr cpu_get_phys_page_attrs_debug(CPUState *cpu, vaddr addr, | |
500 | MemTxAttrs *attrs) | |
501 | { | |
502 | CPUClass *cc = CPU_GET_CLASS(cpu); | |
503 | ||
504 | if (cc->get_phys_page_attrs_debug) { | |
505 | return cc->get_phys_page_attrs_debug(cpu, addr, attrs); | |
506 | } | |
507 | /* Fallback for CPUs which don't implement the _attrs_ hook */ | |
508 | *attrs = MEMTXATTRS_UNSPECIFIED; | |
509 | return cc->get_phys_page_debug(cpu, addr); | |
510 | } | |
511 | ||
00b941e5 AF |
512 | /** |
513 | * cpu_get_phys_page_debug: | |
514 | * @cpu: The CPU to obtain the physical page address for. | |
515 | * @addr: The virtual address. | |
516 | * | |
517 | * Obtains the physical page corresponding to a virtual one. | |
518 | * Use it only for debugging because no protection checks are done. | |
519 | * | |
520 | * Returns: Corresponding physical page address or -1 if no page found. | |
521 | */ | |
522 | static inline hwaddr cpu_get_phys_page_debug(CPUState *cpu, vaddr addr) | |
523 | { | |
1dc6fb1f | 524 | MemTxAttrs attrs = {}; |
00b941e5 | 525 | |
1dc6fb1f | 526 | return cpu_get_phys_page_attrs_debug(cpu, addr, &attrs); |
00b941e5 | 527 | } |
d7f25a9e PM |
528 | |
529 | /** cpu_asidx_from_attrs: | |
530 | * @cpu: CPU | |
531 | * @attrs: memory transaction attributes | |
532 | * | |
533 | * Returns the address space index specifying the CPU AddressSpace | |
534 | * to use for a memory access with the given transaction attributes. | |
535 | */ | |
536 | static inline int cpu_asidx_from_attrs(CPUState *cpu, MemTxAttrs attrs) | |
537 | { | |
538 | CPUClass *cc = CPU_GET_CLASS(cpu); | |
539 | ||
540 | if (cc->asidx_from_attrs) { | |
541 | return cc->asidx_from_attrs(cpu, attrs); | |
542 | } | |
543 | return 0; | |
544 | } | |
00b941e5 AF |
545 | #endif |
546 | ||
267f685b PB |
547 | /** |
548 | * cpu_list_add: | |
549 | * @cpu: The CPU to be added to the list of CPUs. | |
550 | */ | |
551 | void cpu_list_add(CPUState *cpu); | |
552 | ||
553 | /** | |
554 | * cpu_list_remove: | |
555 | * @cpu: The CPU to be removed from the list of CPUs. | |
556 | */ | |
557 | void cpu_list_remove(CPUState *cpu); | |
558 | ||
dd83b06a AF |
559 | /** |
560 | * cpu_reset: | |
561 | * @cpu: The CPU whose state is to be reset. | |
562 | */ | |
563 | void cpu_reset(CPUState *cpu); | |
564 | ||
2b8c2754 AF |
565 | /** |
566 | * cpu_class_by_name: | |
567 | * @typename: The CPU base type. | |
568 | * @cpu_model: The model string without any parameters. | |
569 | * | |
570 | * Looks up a CPU #ObjectClass matching name @cpu_model. | |
571 | * | |
572 | * Returns: A #CPUClass or %NULL if not matching class is found. | |
573 | */ | |
574 | ObjectClass *cpu_class_by_name(const char *typename, const char *cpu_model); | |
575 | ||
9262685b AF |
576 | /** |
577 | * cpu_generic_init: | |
578 | * @typename: The CPU base type. | |
579 | * @cpu_model: The model string including optional parameters. | |
580 | * | |
581 | * Instantiates a CPU, processes optional parameters and realizes the CPU. | |
582 | * | |
583 | * Returns: A #CPUState or %NULL if an error occurred. | |
584 | */ | |
585 | CPUState *cpu_generic_init(const char *typename, const char *cpu_model); | |
586 | ||
3993c6bd | 587 | /** |
8c2e1b00 | 588 | * cpu_has_work: |
3993c6bd AF |
589 | * @cpu: The vCPU to check. |
590 | * | |
591 | * Checks whether the CPU has work to do. | |
592 | * | |
593 | * Returns: %true if the CPU has work, %false otherwise. | |
594 | */ | |
8c2e1b00 AF |
595 | static inline bool cpu_has_work(CPUState *cpu) |
596 | { | |
597 | CPUClass *cc = CPU_GET_CLASS(cpu); | |
598 | ||
599 | g_assert(cc->has_work); | |
600 | return cc->has_work(cpu); | |
601 | } | |
3993c6bd | 602 | |
60e82579 AF |
603 | /** |
604 | * qemu_cpu_is_self: | |
605 | * @cpu: The vCPU to check against. | |
606 | * | |
607 | * Checks whether the caller is executing on the vCPU thread. | |
608 | * | |
609 | * Returns: %true if called from @cpu's thread, %false otherwise. | |
610 | */ | |
611 | bool qemu_cpu_is_self(CPUState *cpu); | |
612 | ||
c08d7424 AF |
613 | /** |
614 | * qemu_cpu_kick: | |
615 | * @cpu: The vCPU to kick. | |
616 | * | |
617 | * Kicks @cpu's thread. | |
618 | */ | |
619 | void qemu_cpu_kick(CPUState *cpu); | |
620 | ||
2fa45344 AF |
621 | /** |
622 | * cpu_is_stopped: | |
623 | * @cpu: The CPU to check. | |
624 | * | |
625 | * Checks whether the CPU is stopped. | |
626 | * | |
627 | * Returns: %true if run state is not running or if artificially stopped; | |
628 | * %false otherwise. | |
629 | */ | |
630 | bool cpu_is_stopped(CPUState *cpu); | |
631 | ||
f100f0b3 AF |
632 | /** |
633 | * run_on_cpu: | |
634 | * @cpu: The vCPU to run on. | |
635 | * @func: The function to be executed. | |
636 | * @data: Data to pass to the function. | |
637 | * | |
638 | * Schedules the function @func for execution on the vCPU @cpu. | |
639 | */ | |
e0eeb4a2 | 640 | void run_on_cpu(CPUState *cpu, run_on_cpu_func func, void *data); |
f100f0b3 | 641 | |
3c02270d CV |
642 | /** |
643 | * async_run_on_cpu: | |
644 | * @cpu: The vCPU to run on. | |
645 | * @func: The function to be executed. | |
646 | * @data: Data to pass to the function. | |
647 | * | |
648 | * Schedules the function @func for execution on the vCPU @cpu asynchronously. | |
649 | */ | |
e0eeb4a2 | 650 | void async_run_on_cpu(CPUState *cpu, run_on_cpu_func func, void *data); |
3c02270d | 651 | |
38d8f5c8 AF |
652 | /** |
653 | * qemu_get_cpu: | |
654 | * @index: The CPUState@cpu_index value of the CPU to obtain. | |
655 | * | |
656 | * Gets a CPU matching @index. | |
657 | * | |
658 | * Returns: The CPU or %NULL if there is no matching CPU. | |
659 | */ | |
660 | CPUState *qemu_get_cpu(int index); | |
661 | ||
69e5ff06 IM |
662 | /** |
663 | * cpu_exists: | |
664 | * @id: Guest-exposed CPU ID to lookup. | |
665 | * | |
666 | * Search for CPU with specified ID. | |
667 | * | |
668 | * Returns: %true - CPU is found, %false - CPU isn't found. | |
669 | */ | |
670 | bool cpu_exists(int64_t id); | |
671 | ||
2adcc85d JH |
672 | /** |
673 | * cpu_throttle_set: | |
674 | * @new_throttle_pct: Percent of sleep time. Valid range is 1 to 99. | |
675 | * | |
676 | * Throttles all vcpus by forcing them to sleep for the given percentage of | |
677 | * time. A throttle_percentage of 25 corresponds to a 75% duty cycle roughly. | |
678 | * (example: 10ms sleep for every 30ms awake). | |
679 | * | |
680 | * cpu_throttle_set can be called as needed to adjust new_throttle_pct. | |
681 | * Once the throttling starts, it will remain in effect until cpu_throttle_stop | |
682 | * is called. | |
683 | */ | |
684 | void cpu_throttle_set(int new_throttle_pct); | |
685 | ||
686 | /** | |
687 | * cpu_throttle_stop: | |
688 | * | |
689 | * Stops the vcpu throttling started by cpu_throttle_set. | |
690 | */ | |
691 | void cpu_throttle_stop(void); | |
692 | ||
693 | /** | |
694 | * cpu_throttle_active: | |
695 | * | |
696 | * Returns: %true if the vcpus are currently being throttled, %false otherwise. | |
697 | */ | |
698 | bool cpu_throttle_active(void); | |
699 | ||
700 | /** | |
701 | * cpu_throttle_get_percentage: | |
702 | * | |
703 | * Returns the vcpu throttle percentage. See cpu_throttle_set for details. | |
704 | * | |
705 | * Returns: The throttle percentage in range 1 to 99. | |
706 | */ | |
707 | int cpu_throttle_get_percentage(void); | |
708 | ||
c3affe56 AF |
709 | #ifndef CONFIG_USER_ONLY |
710 | ||
711 | typedef void (*CPUInterruptHandler)(CPUState *, int); | |
712 | ||
713 | extern CPUInterruptHandler cpu_interrupt_handler; | |
714 | ||
715 | /** | |
716 | * cpu_interrupt: | |
717 | * @cpu: The CPU to set an interrupt on. | |
718 | * @mask: The interupts to set. | |
719 | * | |
720 | * Invokes the interrupt handler. | |
721 | */ | |
722 | static inline void cpu_interrupt(CPUState *cpu, int mask) | |
723 | { | |
724 | cpu_interrupt_handler(cpu, mask); | |
725 | } | |
726 | ||
727 | #else /* USER_ONLY */ | |
728 | ||
729 | void cpu_interrupt(CPUState *cpu, int mask); | |
730 | ||
731 | #endif /* USER_ONLY */ | |
732 | ||
93e22326 | 733 | #ifdef CONFIG_SOFTMMU |
c658b94f AF |
734 | static inline void cpu_unassigned_access(CPUState *cpu, hwaddr addr, |
735 | bool is_write, bool is_exec, | |
736 | int opaque, unsigned size) | |
737 | { | |
738 | CPUClass *cc = CPU_GET_CLASS(cpu); | |
739 | ||
740 | if (cc->do_unassigned_access) { | |
741 | cc->do_unassigned_access(cpu, addr, is_write, is_exec, opaque, size); | |
742 | } | |
743 | } | |
744 | ||
93e22326 | 745 | static inline void cpu_unaligned_access(CPUState *cpu, vaddr addr, |
b35399bb SS |
746 | MMUAccessType access_type, |
747 | int mmu_idx, uintptr_t retaddr) | |
93e22326 PB |
748 | { |
749 | CPUClass *cc = CPU_GET_CLASS(cpu); | |
750 | ||
b35399bb | 751 | cc->do_unaligned_access(cpu, addr, access_type, mmu_idx, retaddr); |
93e22326 | 752 | } |
c658b94f AF |
753 | #endif |
754 | ||
2991b890 PC |
755 | /** |
756 | * cpu_set_pc: | |
757 | * @cpu: The CPU to set the program counter for. | |
758 | * @addr: Program counter value. | |
759 | * | |
760 | * Sets the program counter for a CPU. | |
761 | */ | |
762 | static inline void cpu_set_pc(CPUState *cpu, vaddr addr) | |
763 | { | |
764 | CPUClass *cc = CPU_GET_CLASS(cpu); | |
765 | ||
766 | cc->set_pc(cpu, addr); | |
767 | } | |
768 | ||
d8ed887b AF |
769 | /** |
770 | * cpu_reset_interrupt: | |
771 | * @cpu: The CPU to clear the interrupt on. | |
772 | * @mask: The interrupt mask to clear. | |
773 | * | |
774 | * Resets interrupts on the vCPU @cpu. | |
775 | */ | |
776 | void cpu_reset_interrupt(CPUState *cpu, int mask); | |
777 | ||
60a3e17a AF |
778 | /** |
779 | * cpu_exit: | |
780 | * @cpu: The CPU to exit. | |
781 | * | |
782 | * Requests the CPU @cpu to exit execution. | |
783 | */ | |
784 | void cpu_exit(CPUState *cpu); | |
785 | ||
2993683b IM |
786 | /** |
787 | * cpu_resume: | |
788 | * @cpu: The CPU to resume. | |
789 | * | |
790 | * Resumes CPU, i.e. puts CPU into runnable state. | |
791 | */ | |
792 | void cpu_resume(CPUState *cpu); | |
dd83b06a | 793 | |
4c055ab5 GZ |
794 | /** |
795 | * cpu_remove: | |
796 | * @cpu: The CPU to remove. | |
797 | * | |
798 | * Requests the CPU to be removed. | |
799 | */ | |
800 | void cpu_remove(CPUState *cpu); | |
801 | ||
2c579042 BR |
802 | /** |
803 | * cpu_remove_sync: | |
804 | * @cpu: The CPU to remove. | |
805 | * | |
806 | * Requests the CPU to be removed and waits till it is removed. | |
807 | */ | |
808 | void cpu_remove_sync(CPUState *cpu); | |
809 | ||
c643bed9 AF |
810 | /** |
811 | * qemu_init_vcpu: | |
812 | * @cpu: The vCPU to initialize. | |
813 | * | |
814 | * Initializes a vCPU. | |
815 | */ | |
816 | void qemu_init_vcpu(CPUState *cpu); | |
817 | ||
3825b28f AF |
818 | #define SSTEP_ENABLE 0x1 /* Enable simulated HW single stepping */ |
819 | #define SSTEP_NOIRQ 0x2 /* Do not use IRQ while single stepping */ | |
820 | #define SSTEP_NOTIMER 0x4 /* Do not Timers while single stepping */ | |
821 | ||
822 | /** | |
823 | * cpu_single_step: | |
824 | * @cpu: CPU to the flags for. | |
825 | * @enabled: Flags to enable. | |
826 | * | |
827 | * Enables or disables single-stepping for @cpu. | |
828 | */ | |
829 | void cpu_single_step(CPUState *cpu, int enabled); | |
830 | ||
b3310ab3 AF |
831 | /* Breakpoint/watchpoint flags */ |
832 | #define BP_MEM_READ 0x01 | |
833 | #define BP_MEM_WRITE 0x02 | |
834 | #define BP_MEM_ACCESS (BP_MEM_READ | BP_MEM_WRITE) | |
835 | #define BP_STOP_BEFORE_ACCESS 0x04 | |
08225676 | 836 | /* 0x08 currently unused */ |
b3310ab3 AF |
837 | #define BP_GDB 0x10 |
838 | #define BP_CPU 0x20 | |
b933066a | 839 | #define BP_ANY (BP_GDB | BP_CPU) |
08225676 PM |
840 | #define BP_WATCHPOINT_HIT_READ 0x40 |
841 | #define BP_WATCHPOINT_HIT_WRITE 0x80 | |
842 | #define BP_WATCHPOINT_HIT (BP_WATCHPOINT_HIT_READ | BP_WATCHPOINT_HIT_WRITE) | |
b3310ab3 AF |
843 | |
844 | int cpu_breakpoint_insert(CPUState *cpu, vaddr pc, int flags, | |
845 | CPUBreakpoint **breakpoint); | |
846 | int cpu_breakpoint_remove(CPUState *cpu, vaddr pc, int flags); | |
847 | void cpu_breakpoint_remove_by_ref(CPUState *cpu, CPUBreakpoint *breakpoint); | |
848 | void cpu_breakpoint_remove_all(CPUState *cpu, int mask); | |
849 | ||
b933066a RH |
850 | /* Return true if PC matches an installed breakpoint. */ |
851 | static inline bool cpu_breakpoint_test(CPUState *cpu, vaddr pc, int mask) | |
852 | { | |
853 | CPUBreakpoint *bp; | |
854 | ||
855 | if (unlikely(!QTAILQ_EMPTY(&cpu->breakpoints))) { | |
856 | QTAILQ_FOREACH(bp, &cpu->breakpoints, entry) { | |
857 | if (bp->pc == pc && (bp->flags & mask)) { | |
858 | return true; | |
859 | } | |
860 | } | |
861 | } | |
862 | return false; | |
863 | } | |
864 | ||
75a34036 AF |
865 | int cpu_watchpoint_insert(CPUState *cpu, vaddr addr, vaddr len, |
866 | int flags, CPUWatchpoint **watchpoint); | |
867 | int cpu_watchpoint_remove(CPUState *cpu, vaddr addr, | |
868 | vaddr len, int flags); | |
869 | void cpu_watchpoint_remove_by_ref(CPUState *cpu, CPUWatchpoint *watchpoint); | |
870 | void cpu_watchpoint_remove_all(CPUState *cpu, int mask); | |
871 | ||
63c91552 PB |
872 | /** |
873 | * cpu_get_address_space: | |
874 | * @cpu: CPU to get address space from | |
875 | * @asidx: index identifying which address space to get | |
876 | * | |
877 | * Return the requested address space of this CPU. @asidx | |
878 | * specifies which address space to read. | |
879 | */ | |
880 | AddressSpace *cpu_get_address_space(CPUState *cpu, int asidx); | |
881 | ||
a47dddd7 AF |
882 | void QEMU_NORETURN cpu_abort(CPUState *cpu, const char *fmt, ...) |
883 | GCC_FMT_ATTR(2, 3); | |
b7bca733 | 884 | void cpu_exec_exit(CPUState *cpu); |
a47dddd7 | 885 | |
1a1562f5 AF |
886 | #ifdef CONFIG_SOFTMMU |
887 | extern const struct VMStateDescription vmstate_cpu_common; | |
888 | #else | |
889 | #define vmstate_cpu_common vmstate_dummy | |
890 | #endif | |
891 | ||
892 | #define VMSTATE_CPU() { \ | |
893 | .name = "parent_obj", \ | |
894 | .size = sizeof(CPUState), \ | |
895 | .vmsd = &vmstate_cpu_common, \ | |
896 | .flags = VMS_STRUCT, \ | |
897 | .offset = 0, \ | |
898 | } | |
899 | ||
a07f953e IM |
900 | #define UNASSIGNED_CPU_INDEX -1 |
901 | ||
dd83b06a | 902 | #endif |