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dd83b06a AF |
1 | /* |
2 | * QEMU CPU model | |
3 | * | |
4 | * Copyright (c) 2012 SUSE LINUX Products GmbH | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or | |
7 | * modify it under the terms of the GNU General Public License | |
8 | * as published by the Free Software Foundation; either version 2 | |
9 | * of the License, or (at your option) any later version. | |
10 | * | |
11 | * This program is distributed in the hope that it will be useful, | |
12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
14 | * GNU General Public License for more details. | |
15 | * | |
16 | * You should have received a copy of the GNU General Public License | |
17 | * along with this program; if not, see | |
18 | * <http://www.gnu.org/licenses/gpl-2.0.html> | |
19 | */ | |
20 | #ifndef QEMU_CPU_H | |
21 | #define QEMU_CPU_H | |
22 | ||
fcd7d003 | 23 | #include <signal.h> |
6f03bef0 | 24 | #include <setjmp.h> |
961f8395 | 25 | #include "hw/qdev-core.h" |
37b9de46 | 26 | #include "disas/bfd.h" |
c658b94f | 27 | #include "exec/hwaddr.h" |
66b9b43c | 28 | #include "exec/memattrs.h" |
bdc44640 | 29 | #include "qemu/queue.h" |
1de7afc9 | 30 | #include "qemu/thread.h" |
a23bbfda | 31 | #include "qemu/typedefs.h" |
dd83b06a | 32 | |
b5ba1cc6 QN |
33 | typedef int (*WriteCoreDumpFunction)(const void *buf, size_t size, |
34 | void *opaque); | |
c72bf468 | 35 | |
577f42c0 AF |
36 | /** |
37 | * vaddr: | |
38 | * Type wide enough to contain any #target_ulong virtual address. | |
39 | */ | |
40 | typedef uint64_t vaddr; | |
41 | #define VADDR_PRId PRId64 | |
42 | #define VADDR_PRIu PRIu64 | |
43 | #define VADDR_PRIo PRIo64 | |
44 | #define VADDR_PRIx PRIx64 | |
45 | #define VADDR_PRIX PRIX64 | |
46 | #define VADDR_MAX UINT64_MAX | |
47 | ||
dd83b06a AF |
48 | /** |
49 | * SECTION:cpu | |
50 | * @section_id: QEMU-cpu | |
51 | * @title: CPU Class | |
52 | * @short_description: Base class for all CPUs | |
53 | */ | |
54 | ||
55 | #define TYPE_CPU "cpu" | |
56 | ||
0d6d1ab4 AF |
57 | /* Since this macro is used a lot in hot code paths and in conjunction with |
58 | * FooCPU *foo_env_get_cpu(), we deviate from usual QOM practice by using | |
59 | * an unchecked cast. | |
60 | */ | |
61 | #define CPU(obj) ((CPUState *)(obj)) | |
62 | ||
dd83b06a AF |
63 | #define CPU_CLASS(class) OBJECT_CLASS_CHECK(CPUClass, (class), TYPE_CPU) |
64 | #define CPU_GET_CLASS(obj) OBJECT_GET_CLASS(CPUClass, (obj), TYPE_CPU) | |
65 | ||
66 | typedef struct CPUState CPUState; | |
67 | ||
c658b94f AF |
68 | typedef void (*CPUUnassignedAccess)(CPUState *cpu, hwaddr addr, |
69 | bool is_write, bool is_exec, int opaque, | |
70 | unsigned size); | |
71 | ||
bdf7ae5b AF |
72 | struct TranslationBlock; |
73 | ||
dd83b06a AF |
74 | /** |
75 | * CPUClass: | |
2b8c2754 AF |
76 | * @class_by_name: Callback to map -cpu command line model name to an |
77 | * instantiatable CPU type. | |
94a444b2 | 78 | * @parse_features: Callback to parse command line arguments. |
f5df5baf | 79 | * @reset: Callback to reset the #CPUState to its initial state. |
91b1df8c | 80 | * @reset_dump_flags: #CPUDumpFlags to use for reset logging. |
8c2e1b00 | 81 | * @has_work: Callback for checking if there is work to do. |
97a8ea5a | 82 | * @do_interrupt: Callback for interrupt handling. |
c658b94f | 83 | * @do_unassigned_access: Callback for unassigned access handling. |
93e22326 PB |
84 | * @do_unaligned_access: Callback for unaligned access handling, if |
85 | * the target defines #ALIGNED_ONLY. | |
c08295d4 PM |
86 | * @virtio_is_big_endian: Callback to return %true if a CPU which supports |
87 | * runtime configurable endianness is currently big-endian. Non-configurable | |
88 | * CPUs can use the default implementation of this method. This method should | |
89 | * not be used by any callers other than the pre-1.0 virtio devices. | |
f3659eee | 90 | * @memory_rw_debug: Callback for GDB memory access. |
878096ee AF |
91 | * @dump_state: Callback for dumping state. |
92 | * @dump_statistics: Callback for dumping statistics. | |
997395d3 | 93 | * @get_arch_id: Callback for getting architecture-dependent CPU ID. |
444d5590 | 94 | * @get_paging_enabled: Callback for inquiring whether paging is enabled. |
a23bbfda | 95 | * @get_memory_mapping: Callback for obtaining the memory mappings. |
f45748f1 | 96 | * @set_pc: Callback for setting the Program Counter register. |
bdf7ae5b AF |
97 | * @synchronize_from_tb: Callback for synchronizing state from a TCG |
98 | * #TranslationBlock. | |
7510454e | 99 | * @handle_mmu_fault: Callback for handling an MMU fault. |
00b941e5 | 100 | * @get_phys_page_debug: Callback for obtaining a physical address. |
5b50e790 AF |
101 | * @gdb_read_register: Callback for letting GDB read a register. |
102 | * @gdb_write_register: Callback for letting GDB write a register. | |
86025ee4 | 103 | * @debug_excp_handler: Callback for handling debug exceptions. |
c08295d4 PM |
104 | * @write_elf64_note: Callback for writing a CPU-specific ELF note to a |
105 | * 64-bit VM coredump. | |
106 | * @write_elf32_qemunote: Callback for writing a CPU- and QEMU-specific ELF | |
107 | * note to a 32-bit VM coredump. | |
108 | * @write_elf32_note: Callback for writing a CPU-specific ELF note to a | |
109 | * 32-bit VM coredump. | |
110 | * @write_elf32_qemunote: Callback for writing a CPU- and QEMU-specific ELF | |
111 | * note to a 32-bit VM coredump. | |
b170fce3 | 112 | * @vmsd: State description for migration. |
a0e372f0 | 113 | * @gdb_num_core_regs: Number of core registers accessible to GDB. |
5b24c641 | 114 | * @gdb_core_xml_file: File name for core registers GDB XML description. |
2472b6c0 PM |
115 | * @gdb_stop_before_watchpoint: Indicates whether GDB expects the CPU to stop |
116 | * before the insn which triggers a watchpoint rather than after it. | |
cffe7b32 RH |
117 | * @cpu_exec_enter: Callback for cpu_exec preparation. |
118 | * @cpu_exec_exit: Callback for cpu_exec cleanup. | |
9585db68 | 119 | * @cpu_exec_interrupt: Callback for processing interrupts in cpu_exec. |
37b9de46 | 120 | * @disas_set_info: Setup architecture specific components of disassembly info |
dd83b06a AF |
121 | * |
122 | * Represents a CPU family or model. | |
123 | */ | |
124 | typedef struct CPUClass { | |
125 | /*< private >*/ | |
961f8395 | 126 | DeviceClass parent_class; |
dd83b06a AF |
127 | /*< public >*/ |
128 | ||
2b8c2754 | 129 | ObjectClass *(*class_by_name)(const char *cpu_model); |
94a444b2 | 130 | void (*parse_features)(CPUState *cpu, char *str, Error **errp); |
2b8c2754 | 131 | |
dd83b06a | 132 | void (*reset)(CPUState *cpu); |
91b1df8c | 133 | int reset_dump_flags; |
8c2e1b00 | 134 | bool (*has_work)(CPUState *cpu); |
97a8ea5a | 135 | void (*do_interrupt)(CPUState *cpu); |
c658b94f | 136 | CPUUnassignedAccess do_unassigned_access; |
93e22326 PB |
137 | void (*do_unaligned_access)(CPUState *cpu, vaddr addr, |
138 | int is_write, int is_user, uintptr_t retaddr); | |
bf7663c4 | 139 | bool (*virtio_is_big_endian)(CPUState *cpu); |
f3659eee AF |
140 | int (*memory_rw_debug)(CPUState *cpu, vaddr addr, |
141 | uint8_t *buf, int len, bool is_write); | |
878096ee AF |
142 | void (*dump_state)(CPUState *cpu, FILE *f, fprintf_function cpu_fprintf, |
143 | int flags); | |
144 | void (*dump_statistics)(CPUState *cpu, FILE *f, | |
145 | fprintf_function cpu_fprintf, int flags); | |
997395d3 | 146 | int64_t (*get_arch_id)(CPUState *cpu); |
444d5590 | 147 | bool (*get_paging_enabled)(const CPUState *cpu); |
a23bbfda AF |
148 | void (*get_memory_mapping)(CPUState *cpu, MemoryMappingList *list, |
149 | Error **errp); | |
f45748f1 | 150 | void (*set_pc)(CPUState *cpu, vaddr value); |
bdf7ae5b | 151 | void (*synchronize_from_tb)(CPUState *cpu, struct TranslationBlock *tb); |
7510454e AF |
152 | int (*handle_mmu_fault)(CPUState *cpu, vaddr address, int rw, |
153 | int mmu_index); | |
00b941e5 | 154 | hwaddr (*get_phys_page_debug)(CPUState *cpu, vaddr addr); |
5b50e790 AF |
155 | int (*gdb_read_register)(CPUState *cpu, uint8_t *buf, int reg); |
156 | int (*gdb_write_register)(CPUState *cpu, uint8_t *buf, int reg); | |
86025ee4 | 157 | void (*debug_excp_handler)(CPUState *cpu); |
b170fce3 | 158 | |
c72bf468 JF |
159 | int (*write_elf64_note)(WriteCoreDumpFunction f, CPUState *cpu, |
160 | int cpuid, void *opaque); | |
161 | int (*write_elf64_qemunote)(WriteCoreDumpFunction f, CPUState *cpu, | |
162 | void *opaque); | |
163 | int (*write_elf32_note)(WriteCoreDumpFunction f, CPUState *cpu, | |
164 | int cpuid, void *opaque); | |
165 | int (*write_elf32_qemunote)(WriteCoreDumpFunction f, CPUState *cpu, | |
166 | void *opaque); | |
a0e372f0 AF |
167 | |
168 | const struct VMStateDescription *vmsd; | |
169 | int gdb_num_core_regs; | |
5b24c641 | 170 | const char *gdb_core_xml_file; |
2472b6c0 | 171 | bool gdb_stop_before_watchpoint; |
cffe7b32 RH |
172 | |
173 | void (*cpu_exec_enter)(CPUState *cpu); | |
174 | void (*cpu_exec_exit)(CPUState *cpu); | |
9585db68 | 175 | bool (*cpu_exec_interrupt)(CPUState *cpu, int interrupt_request); |
37b9de46 PC |
176 | |
177 | void (*disas_set_info)(CPUState *cpu, disassemble_info *info); | |
dd83b06a AF |
178 | } CPUClass; |
179 | ||
28ecfd7a AF |
180 | #ifdef HOST_WORDS_BIGENDIAN |
181 | typedef struct icount_decr_u16 { | |
182 | uint16_t high; | |
183 | uint16_t low; | |
184 | } icount_decr_u16; | |
185 | #else | |
186 | typedef struct icount_decr_u16 { | |
187 | uint16_t low; | |
188 | uint16_t high; | |
189 | } icount_decr_u16; | |
190 | #endif | |
191 | ||
f0c3c505 AF |
192 | typedef struct CPUBreakpoint { |
193 | vaddr pc; | |
194 | int flags; /* BP_* */ | |
195 | QTAILQ_ENTRY(CPUBreakpoint) entry; | |
196 | } CPUBreakpoint; | |
197 | ||
ff4700b0 AF |
198 | typedef struct CPUWatchpoint { |
199 | vaddr vaddr; | |
05068c0d | 200 | vaddr len; |
08225676 | 201 | vaddr hitaddr; |
66b9b43c | 202 | MemTxAttrs hitattrs; |
ff4700b0 AF |
203 | int flags; /* BP_* */ |
204 | QTAILQ_ENTRY(CPUWatchpoint) entry; | |
205 | } CPUWatchpoint; | |
206 | ||
a60f24b5 | 207 | struct KVMState; |
f7575c96 | 208 | struct kvm_run; |
a60f24b5 | 209 | |
8cd70437 AF |
210 | #define TB_JMP_CACHE_BITS 12 |
211 | #define TB_JMP_CACHE_SIZE (1 << TB_JMP_CACHE_BITS) | |
212 | ||
dd83b06a AF |
213 | /** |
214 | * CPUState: | |
55e5c285 | 215 | * @cpu_index: CPU index (informative). |
ce3960eb AF |
216 | * @nr_cores: Number of cores within this CPU package. |
217 | * @nr_threads: Number of threads within this CPU. | |
1b1ed8dc | 218 | * @numa_node: NUMA node this CPU is belonging to. |
0d34282f | 219 | * @host_tid: Host thread ID. |
0315c31c | 220 | * @running: #true if CPU is currently running (usermode). |
61a46217 | 221 | * @created: Indicates whether the CPU thread has been successfully created. |
259186a7 AF |
222 | * @interrupt_request: Indicates a pending interrupt request. |
223 | * @halted: Nonzero if the CPU is in suspended state. | |
4fdeee7c | 224 | * @stop: Indicates a pending stop request. |
f324e766 | 225 | * @stopped: Indicates the CPU has been artificially stopped. |
378df4b2 PM |
226 | * @tcg_exit_req: Set to force TCG to stop executing linked TBs for this |
227 | * CPU and return to its top level loop. | |
ed2803da | 228 | * @singlestep_enabled: Flags for single-stepping. |
efee7340 | 229 | * @icount_extra: Instructions until next timer event. |
28ecfd7a AF |
230 | * @icount_decr: Number of cycles left, with interrupt flag in high bit. |
231 | * This allows a single read-compare-cbranch-write sequence to test | |
232 | * for both decrementer underflow and exceptions. | |
414b15c9 PB |
233 | * @can_do_io: Nonzero if memory-mapped IO is safe. Deterministic execution |
234 | * requires that IO only be performed on the last instruction of a TB | |
235 | * so that interrupts take effect immediately. | |
c05efcb1 | 236 | * @env_ptr: Pointer to subclass-specific CPUArchState field. |
d77953b9 | 237 | * @current_tb: Currently executing TB. |
eac8b355 | 238 | * @gdb_regs: Additional GDB registers. |
a0e372f0 | 239 | * @gdb_num_regs: Number of total registers accessible to GDB. |
35143f01 | 240 | * @gdb_num_g_regs: Number of registers in GDB 'g' packets. |
182735ef | 241 | * @next_cpu: Next CPU sharing TB cache. |
0429a971 | 242 | * @opaque: User data. |
93afeade AF |
243 | * @mem_io_pc: Host Program Counter at which the memory was accessed. |
244 | * @mem_io_vaddr: Target virtual address at which the memory was accessed. | |
8737c51c | 245 | * @kvm_fd: vCPU file descriptor for KVM. |
376692b9 PB |
246 | * @work_mutex: Lock to prevent multiple access to queued_work_*. |
247 | * @queued_work_first: First asynchronous work pending. | |
dd83b06a AF |
248 | * |
249 | * State of one CPU core or thread. | |
250 | */ | |
251 | struct CPUState { | |
252 | /*< private >*/ | |
961f8395 | 253 | DeviceState parent_obj; |
dd83b06a AF |
254 | /*< public >*/ |
255 | ||
ce3960eb AF |
256 | int nr_cores; |
257 | int nr_threads; | |
1b1ed8dc | 258 | int numa_node; |
ce3960eb | 259 | |
814e612e | 260 | struct QemuThread *thread; |
bcba2a72 AF |
261 | #ifdef _WIN32 |
262 | HANDLE hThread; | |
263 | #endif | |
9f09e18a | 264 | int thread_id; |
0d34282f | 265 | uint32_t host_tid; |
0315c31c | 266 | bool running; |
f5c121b8 | 267 | struct QemuCond *halt_cond; |
216fc9a4 | 268 | bool thread_kicked; |
61a46217 | 269 | bool created; |
4fdeee7c | 270 | bool stop; |
f324e766 | 271 | bool stopped; |
e0c38211 | 272 | bool exit_request; |
259186a7 | 273 | uint32_t interrupt_request; |
ed2803da | 274 | int singlestep_enabled; |
efee7340 | 275 | int64_t icount_extra; |
6f03bef0 | 276 | sigjmp_buf jmp_env; |
bcba2a72 | 277 | |
376692b9 PB |
278 | QemuMutex work_mutex; |
279 | struct qemu_work_item *queued_work_first, *queued_work_last; | |
280 | ||
09daed84 | 281 | AddressSpace *as; |
9d82b5a7 | 282 | struct AddressSpaceDispatch *memory_dispatch; |
09daed84 EI |
283 | MemoryListener *tcg_as_listener; |
284 | ||
c05efcb1 | 285 | void *env_ptr; /* CPUArchState */ |
d77953b9 | 286 | struct TranslationBlock *current_tb; |
8cd70437 | 287 | struct TranslationBlock *tb_jmp_cache[TB_JMP_CACHE_SIZE]; |
eac8b355 | 288 | struct GDBRegisterState *gdb_regs; |
a0e372f0 | 289 | int gdb_num_regs; |
35143f01 | 290 | int gdb_num_g_regs; |
bdc44640 | 291 | QTAILQ_ENTRY(CPUState) node; |
d77953b9 | 292 | |
f0c3c505 AF |
293 | /* ice debug support */ |
294 | QTAILQ_HEAD(breakpoints_head, CPUBreakpoint) breakpoints; | |
295 | ||
ff4700b0 AF |
296 | QTAILQ_HEAD(watchpoints_head, CPUWatchpoint) watchpoints; |
297 | CPUWatchpoint *watchpoint_hit; | |
298 | ||
0429a971 AF |
299 | void *opaque; |
300 | ||
93afeade AF |
301 | /* In order to avoid passing too many arguments to the MMIO helpers, |
302 | * we store some rarely used information in the CPU context. | |
303 | */ | |
304 | uintptr_t mem_io_pc; | |
305 | vaddr mem_io_vaddr; | |
306 | ||
8737c51c | 307 | int kvm_fd; |
20d695a9 | 308 | bool kvm_vcpu_dirty; |
a60f24b5 | 309 | struct KVMState *kvm_state; |
f7575c96 | 310 | struct kvm_run *kvm_run; |
8737c51c | 311 | |
f5df5baf | 312 | /* TODO Move common fields from CPUArchState here. */ |
55e5c285 | 313 | int cpu_index; /* used by alpha TCG */ |
259186a7 | 314 | uint32_t halted; /* used by alpha, cris, ppc TCG */ |
28ecfd7a AF |
315 | union { |
316 | uint32_t u32; | |
317 | icount_decr_u16 u16; | |
318 | } icount_decr; | |
99df7dce | 319 | uint32_t can_do_io; |
27103424 | 320 | int32_t exception_index; /* used by m68k TCG */ |
7e4fb26d RH |
321 | |
322 | /* Note that this is accessed at the start of every TB via a negative | |
323 | offset from AREG0. Leave this field at the end so as to make the | |
324 | (absolute value) offset as small as possible. This reduces code | |
325 | size, especially for hosts without large memory offsets. */ | |
e0c38211 | 326 | uint32_t tcg_exit_req; |
dd83b06a AF |
327 | }; |
328 | ||
bdc44640 AF |
329 | QTAILQ_HEAD(CPUTailQ, CPUState); |
330 | extern struct CPUTailQ cpus; | |
331 | #define CPU_NEXT(cpu) QTAILQ_NEXT(cpu, node) | |
332 | #define CPU_FOREACH(cpu) QTAILQ_FOREACH(cpu, &cpus, node) | |
333 | #define CPU_FOREACH_SAFE(cpu, next_cpu) \ | |
334 | QTAILQ_FOREACH_SAFE(cpu, &cpus, node, next_cpu) | |
8487d123 BR |
335 | #define CPU_FOREACH_REVERSE(cpu) \ |
336 | QTAILQ_FOREACH_REVERSE(cpu, &cpus, CPUTailQ, node) | |
bdc44640 | 337 | #define first_cpu QTAILQ_FIRST(&cpus) |
182735ef | 338 | |
f240eb6f | 339 | extern __thread CPUState *current_cpu; |
4917cf44 | 340 | |
444d5590 AF |
341 | /** |
342 | * cpu_paging_enabled: | |
343 | * @cpu: The CPU whose state is to be inspected. | |
344 | * | |
345 | * Returns: %true if paging is enabled, %false otherwise. | |
346 | */ | |
347 | bool cpu_paging_enabled(const CPUState *cpu); | |
348 | ||
a23bbfda AF |
349 | /** |
350 | * cpu_get_memory_mapping: | |
351 | * @cpu: The CPU whose memory mappings are to be obtained. | |
352 | * @list: Where to write the memory mappings to. | |
353 | * @errp: Pointer for reporting an #Error. | |
354 | */ | |
355 | void cpu_get_memory_mapping(CPUState *cpu, MemoryMappingList *list, | |
356 | Error **errp); | |
357 | ||
c72bf468 JF |
358 | /** |
359 | * cpu_write_elf64_note: | |
360 | * @f: pointer to a function that writes memory to a file | |
361 | * @cpu: The CPU whose memory is to be dumped | |
362 | * @cpuid: ID number of the CPU | |
363 | * @opaque: pointer to the CPUState struct | |
364 | */ | |
365 | int cpu_write_elf64_note(WriteCoreDumpFunction f, CPUState *cpu, | |
366 | int cpuid, void *opaque); | |
367 | ||
368 | /** | |
369 | * cpu_write_elf64_qemunote: | |
370 | * @f: pointer to a function that writes memory to a file | |
371 | * @cpu: The CPU whose memory is to be dumped | |
372 | * @cpuid: ID number of the CPU | |
373 | * @opaque: pointer to the CPUState struct | |
374 | */ | |
375 | int cpu_write_elf64_qemunote(WriteCoreDumpFunction f, CPUState *cpu, | |
376 | void *opaque); | |
377 | ||
378 | /** | |
379 | * cpu_write_elf32_note: | |
380 | * @f: pointer to a function that writes memory to a file | |
381 | * @cpu: The CPU whose memory is to be dumped | |
382 | * @cpuid: ID number of the CPU | |
383 | * @opaque: pointer to the CPUState struct | |
384 | */ | |
385 | int cpu_write_elf32_note(WriteCoreDumpFunction f, CPUState *cpu, | |
386 | int cpuid, void *opaque); | |
387 | ||
388 | /** | |
389 | * cpu_write_elf32_qemunote: | |
390 | * @f: pointer to a function that writes memory to a file | |
391 | * @cpu: The CPU whose memory is to be dumped | |
392 | * @cpuid: ID number of the CPU | |
393 | * @opaque: pointer to the CPUState struct | |
394 | */ | |
395 | int cpu_write_elf32_qemunote(WriteCoreDumpFunction f, CPUState *cpu, | |
396 | void *opaque); | |
dd83b06a | 397 | |
878096ee AF |
398 | /** |
399 | * CPUDumpFlags: | |
400 | * @CPU_DUMP_CODE: | |
401 | * @CPU_DUMP_FPU: dump FPU register state, not just integer | |
402 | * @CPU_DUMP_CCOP: dump info about TCG QEMU's condition code optimization state | |
403 | */ | |
404 | enum CPUDumpFlags { | |
405 | CPU_DUMP_CODE = 0x00010000, | |
406 | CPU_DUMP_FPU = 0x00020000, | |
407 | CPU_DUMP_CCOP = 0x00040000, | |
408 | }; | |
409 | ||
410 | /** | |
411 | * cpu_dump_state: | |
412 | * @cpu: The CPU whose state is to be dumped. | |
413 | * @f: File to dump to. | |
414 | * @cpu_fprintf: Function to dump with. | |
415 | * @flags: Flags what to dump. | |
416 | * | |
417 | * Dumps CPU state. | |
418 | */ | |
419 | void cpu_dump_state(CPUState *cpu, FILE *f, fprintf_function cpu_fprintf, | |
420 | int flags); | |
421 | ||
422 | /** | |
423 | * cpu_dump_statistics: | |
424 | * @cpu: The CPU whose state is to be dumped. | |
425 | * @f: File to dump to. | |
426 | * @cpu_fprintf: Function to dump with. | |
427 | * @flags: Flags what to dump. | |
428 | * | |
429 | * Dumps CPU statistics. | |
430 | */ | |
431 | void cpu_dump_statistics(CPUState *cpu, FILE *f, fprintf_function cpu_fprintf, | |
432 | int flags); | |
433 | ||
00b941e5 AF |
434 | #ifndef CONFIG_USER_ONLY |
435 | /** | |
436 | * cpu_get_phys_page_debug: | |
437 | * @cpu: The CPU to obtain the physical page address for. | |
438 | * @addr: The virtual address. | |
439 | * | |
440 | * Obtains the physical page corresponding to a virtual one. | |
441 | * Use it only for debugging because no protection checks are done. | |
442 | * | |
443 | * Returns: Corresponding physical page address or -1 if no page found. | |
444 | */ | |
445 | static inline hwaddr cpu_get_phys_page_debug(CPUState *cpu, vaddr addr) | |
446 | { | |
447 | CPUClass *cc = CPU_GET_CLASS(cpu); | |
448 | ||
449 | return cc->get_phys_page_debug(cpu, addr); | |
450 | } | |
451 | #endif | |
452 | ||
dd83b06a AF |
453 | /** |
454 | * cpu_reset: | |
455 | * @cpu: The CPU whose state is to be reset. | |
456 | */ | |
457 | void cpu_reset(CPUState *cpu); | |
458 | ||
2b8c2754 AF |
459 | /** |
460 | * cpu_class_by_name: | |
461 | * @typename: The CPU base type. | |
462 | * @cpu_model: The model string without any parameters. | |
463 | * | |
464 | * Looks up a CPU #ObjectClass matching name @cpu_model. | |
465 | * | |
466 | * Returns: A #CPUClass or %NULL if not matching class is found. | |
467 | */ | |
468 | ObjectClass *cpu_class_by_name(const char *typename, const char *cpu_model); | |
469 | ||
9262685b AF |
470 | /** |
471 | * cpu_generic_init: | |
472 | * @typename: The CPU base type. | |
473 | * @cpu_model: The model string including optional parameters. | |
474 | * | |
475 | * Instantiates a CPU, processes optional parameters and realizes the CPU. | |
476 | * | |
477 | * Returns: A #CPUState or %NULL if an error occurred. | |
478 | */ | |
479 | CPUState *cpu_generic_init(const char *typename, const char *cpu_model); | |
480 | ||
3993c6bd | 481 | /** |
8c2e1b00 | 482 | * cpu_has_work: |
3993c6bd AF |
483 | * @cpu: The vCPU to check. |
484 | * | |
485 | * Checks whether the CPU has work to do. | |
486 | * | |
487 | * Returns: %true if the CPU has work, %false otherwise. | |
488 | */ | |
8c2e1b00 AF |
489 | static inline bool cpu_has_work(CPUState *cpu) |
490 | { | |
491 | CPUClass *cc = CPU_GET_CLASS(cpu); | |
492 | ||
493 | g_assert(cc->has_work); | |
494 | return cc->has_work(cpu); | |
495 | } | |
3993c6bd | 496 | |
60e82579 AF |
497 | /** |
498 | * qemu_cpu_is_self: | |
499 | * @cpu: The vCPU to check against. | |
500 | * | |
501 | * Checks whether the caller is executing on the vCPU thread. | |
502 | * | |
503 | * Returns: %true if called from @cpu's thread, %false otherwise. | |
504 | */ | |
505 | bool qemu_cpu_is_self(CPUState *cpu); | |
506 | ||
c08d7424 AF |
507 | /** |
508 | * qemu_cpu_kick: | |
509 | * @cpu: The vCPU to kick. | |
510 | * | |
511 | * Kicks @cpu's thread. | |
512 | */ | |
513 | void qemu_cpu_kick(CPUState *cpu); | |
514 | ||
2fa45344 AF |
515 | /** |
516 | * cpu_is_stopped: | |
517 | * @cpu: The CPU to check. | |
518 | * | |
519 | * Checks whether the CPU is stopped. | |
520 | * | |
521 | * Returns: %true if run state is not running or if artificially stopped; | |
522 | * %false otherwise. | |
523 | */ | |
524 | bool cpu_is_stopped(CPUState *cpu); | |
525 | ||
f100f0b3 AF |
526 | /** |
527 | * run_on_cpu: | |
528 | * @cpu: The vCPU to run on. | |
529 | * @func: The function to be executed. | |
530 | * @data: Data to pass to the function. | |
531 | * | |
532 | * Schedules the function @func for execution on the vCPU @cpu. | |
533 | */ | |
534 | void run_on_cpu(CPUState *cpu, void (*func)(void *data), void *data); | |
535 | ||
3c02270d CV |
536 | /** |
537 | * async_run_on_cpu: | |
538 | * @cpu: The vCPU to run on. | |
539 | * @func: The function to be executed. | |
540 | * @data: Data to pass to the function. | |
541 | * | |
542 | * Schedules the function @func for execution on the vCPU @cpu asynchronously. | |
543 | */ | |
544 | void async_run_on_cpu(CPUState *cpu, void (*func)(void *data), void *data); | |
545 | ||
38d8f5c8 AF |
546 | /** |
547 | * qemu_get_cpu: | |
548 | * @index: The CPUState@cpu_index value of the CPU to obtain. | |
549 | * | |
550 | * Gets a CPU matching @index. | |
551 | * | |
552 | * Returns: The CPU or %NULL if there is no matching CPU. | |
553 | */ | |
554 | CPUState *qemu_get_cpu(int index); | |
555 | ||
69e5ff06 IM |
556 | /** |
557 | * cpu_exists: | |
558 | * @id: Guest-exposed CPU ID to lookup. | |
559 | * | |
560 | * Search for CPU with specified ID. | |
561 | * | |
562 | * Returns: %true - CPU is found, %false - CPU isn't found. | |
563 | */ | |
564 | bool cpu_exists(int64_t id); | |
565 | ||
c3affe56 AF |
566 | #ifndef CONFIG_USER_ONLY |
567 | ||
568 | typedef void (*CPUInterruptHandler)(CPUState *, int); | |
569 | ||
570 | extern CPUInterruptHandler cpu_interrupt_handler; | |
571 | ||
572 | /** | |
573 | * cpu_interrupt: | |
574 | * @cpu: The CPU to set an interrupt on. | |
575 | * @mask: The interupts to set. | |
576 | * | |
577 | * Invokes the interrupt handler. | |
578 | */ | |
579 | static inline void cpu_interrupt(CPUState *cpu, int mask) | |
580 | { | |
581 | cpu_interrupt_handler(cpu, mask); | |
582 | } | |
583 | ||
584 | #else /* USER_ONLY */ | |
585 | ||
586 | void cpu_interrupt(CPUState *cpu, int mask); | |
587 | ||
588 | #endif /* USER_ONLY */ | |
589 | ||
93e22326 | 590 | #ifdef CONFIG_SOFTMMU |
c658b94f AF |
591 | static inline void cpu_unassigned_access(CPUState *cpu, hwaddr addr, |
592 | bool is_write, bool is_exec, | |
593 | int opaque, unsigned size) | |
594 | { | |
595 | CPUClass *cc = CPU_GET_CLASS(cpu); | |
596 | ||
597 | if (cc->do_unassigned_access) { | |
598 | cc->do_unassigned_access(cpu, addr, is_write, is_exec, opaque, size); | |
599 | } | |
600 | } | |
601 | ||
93e22326 PB |
602 | static inline void cpu_unaligned_access(CPUState *cpu, vaddr addr, |
603 | int is_write, int is_user, | |
604 | uintptr_t retaddr) | |
605 | { | |
606 | CPUClass *cc = CPU_GET_CLASS(cpu); | |
607 | ||
e7ae771f | 608 | cc->do_unaligned_access(cpu, addr, is_write, is_user, retaddr); |
93e22326 | 609 | } |
c658b94f AF |
610 | #endif |
611 | ||
2991b890 PC |
612 | /** |
613 | * cpu_set_pc: | |
614 | * @cpu: The CPU to set the program counter for. | |
615 | * @addr: Program counter value. | |
616 | * | |
617 | * Sets the program counter for a CPU. | |
618 | */ | |
619 | static inline void cpu_set_pc(CPUState *cpu, vaddr addr) | |
620 | { | |
621 | CPUClass *cc = CPU_GET_CLASS(cpu); | |
622 | ||
623 | cc->set_pc(cpu, addr); | |
624 | } | |
625 | ||
d8ed887b AF |
626 | /** |
627 | * cpu_reset_interrupt: | |
628 | * @cpu: The CPU to clear the interrupt on. | |
629 | * @mask: The interrupt mask to clear. | |
630 | * | |
631 | * Resets interrupts on the vCPU @cpu. | |
632 | */ | |
633 | void cpu_reset_interrupt(CPUState *cpu, int mask); | |
634 | ||
60a3e17a AF |
635 | /** |
636 | * cpu_exit: | |
637 | * @cpu: The CPU to exit. | |
638 | * | |
639 | * Requests the CPU @cpu to exit execution. | |
640 | */ | |
641 | void cpu_exit(CPUState *cpu); | |
642 | ||
2993683b IM |
643 | /** |
644 | * cpu_resume: | |
645 | * @cpu: The CPU to resume. | |
646 | * | |
647 | * Resumes CPU, i.e. puts CPU into runnable state. | |
648 | */ | |
649 | void cpu_resume(CPUState *cpu); | |
dd83b06a | 650 | |
c643bed9 AF |
651 | /** |
652 | * qemu_init_vcpu: | |
653 | * @cpu: The vCPU to initialize. | |
654 | * | |
655 | * Initializes a vCPU. | |
656 | */ | |
657 | void qemu_init_vcpu(CPUState *cpu); | |
658 | ||
3825b28f AF |
659 | #define SSTEP_ENABLE 0x1 /* Enable simulated HW single stepping */ |
660 | #define SSTEP_NOIRQ 0x2 /* Do not use IRQ while single stepping */ | |
661 | #define SSTEP_NOTIMER 0x4 /* Do not Timers while single stepping */ | |
662 | ||
663 | /** | |
664 | * cpu_single_step: | |
665 | * @cpu: CPU to the flags for. | |
666 | * @enabled: Flags to enable. | |
667 | * | |
668 | * Enables or disables single-stepping for @cpu. | |
669 | */ | |
670 | void cpu_single_step(CPUState *cpu, int enabled); | |
671 | ||
b3310ab3 AF |
672 | /* Breakpoint/watchpoint flags */ |
673 | #define BP_MEM_READ 0x01 | |
674 | #define BP_MEM_WRITE 0x02 | |
675 | #define BP_MEM_ACCESS (BP_MEM_READ | BP_MEM_WRITE) | |
676 | #define BP_STOP_BEFORE_ACCESS 0x04 | |
08225676 | 677 | /* 0x08 currently unused */ |
b3310ab3 AF |
678 | #define BP_GDB 0x10 |
679 | #define BP_CPU 0x20 | |
08225676 PM |
680 | #define BP_WATCHPOINT_HIT_READ 0x40 |
681 | #define BP_WATCHPOINT_HIT_WRITE 0x80 | |
682 | #define BP_WATCHPOINT_HIT (BP_WATCHPOINT_HIT_READ | BP_WATCHPOINT_HIT_WRITE) | |
b3310ab3 AF |
683 | |
684 | int cpu_breakpoint_insert(CPUState *cpu, vaddr pc, int flags, | |
685 | CPUBreakpoint **breakpoint); | |
686 | int cpu_breakpoint_remove(CPUState *cpu, vaddr pc, int flags); | |
687 | void cpu_breakpoint_remove_by_ref(CPUState *cpu, CPUBreakpoint *breakpoint); | |
688 | void cpu_breakpoint_remove_all(CPUState *cpu, int mask); | |
689 | ||
75a34036 AF |
690 | int cpu_watchpoint_insert(CPUState *cpu, vaddr addr, vaddr len, |
691 | int flags, CPUWatchpoint **watchpoint); | |
692 | int cpu_watchpoint_remove(CPUState *cpu, vaddr addr, | |
693 | vaddr len, int flags); | |
694 | void cpu_watchpoint_remove_by_ref(CPUState *cpu, CPUWatchpoint *watchpoint); | |
695 | void cpu_watchpoint_remove_all(CPUState *cpu, int mask); | |
696 | ||
a47dddd7 AF |
697 | void QEMU_NORETURN cpu_abort(CPUState *cpu, const char *fmt, ...) |
698 | GCC_FMT_ATTR(2, 3); | |
b7bca733 | 699 | void cpu_exec_exit(CPUState *cpu); |
a47dddd7 | 700 | |
1a1562f5 AF |
701 | #ifdef CONFIG_SOFTMMU |
702 | extern const struct VMStateDescription vmstate_cpu_common; | |
703 | #else | |
704 | #define vmstate_cpu_common vmstate_dummy | |
705 | #endif | |
706 | ||
707 | #define VMSTATE_CPU() { \ | |
708 | .name = "parent_obj", \ | |
709 | .size = sizeof(CPUState), \ | |
710 | .vmsd = &vmstate_cpu_common, \ | |
711 | .flags = VMS_STRUCT, \ | |
712 | .offset = 0, \ | |
713 | } | |
714 | ||
dd83b06a | 715 | #endif |