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dd83b06a AF |
1 | /* |
2 | * QEMU CPU model | |
3 | * | |
4 | * Copyright (c) 2012 SUSE LINUX Products GmbH | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or | |
7 | * modify it under the terms of the GNU General Public License | |
8 | * as published by the Free Software Foundation; either version 2 | |
9 | * of the License, or (at your option) any later version. | |
10 | * | |
11 | * This program is distributed in the hope that it will be useful, | |
12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
14 | * GNU General Public License for more details. | |
15 | * | |
16 | * You should have received a copy of the GNU General Public License | |
17 | * along with this program; if not, see | |
18 | * <http://www.gnu.org/licenses/gpl-2.0.html> | |
19 | */ | |
20 | #ifndef QEMU_CPU_H | |
21 | #define QEMU_CPU_H | |
22 | ||
fcd7d003 | 23 | #include <signal.h> |
6f03bef0 | 24 | #include <setjmp.h> |
961f8395 | 25 | #include "hw/qdev-core.h" |
c658b94f | 26 | #include "exec/hwaddr.h" |
bdc44640 | 27 | #include "qemu/queue.h" |
1de7afc9 | 28 | #include "qemu/thread.h" |
4917cf44 | 29 | #include "qemu/tls.h" |
a23bbfda | 30 | #include "qemu/typedefs.h" |
dd83b06a | 31 | |
b5ba1cc6 QN |
32 | typedef int (*WriteCoreDumpFunction)(const void *buf, size_t size, |
33 | void *opaque); | |
c72bf468 | 34 | |
577f42c0 AF |
35 | /** |
36 | * vaddr: | |
37 | * Type wide enough to contain any #target_ulong virtual address. | |
38 | */ | |
39 | typedef uint64_t vaddr; | |
40 | #define VADDR_PRId PRId64 | |
41 | #define VADDR_PRIu PRIu64 | |
42 | #define VADDR_PRIo PRIo64 | |
43 | #define VADDR_PRIx PRIx64 | |
44 | #define VADDR_PRIX PRIX64 | |
45 | #define VADDR_MAX UINT64_MAX | |
46 | ||
dd83b06a AF |
47 | /** |
48 | * SECTION:cpu | |
49 | * @section_id: QEMU-cpu | |
50 | * @title: CPU Class | |
51 | * @short_description: Base class for all CPUs | |
52 | */ | |
53 | ||
54 | #define TYPE_CPU "cpu" | |
55 | ||
0d6d1ab4 AF |
56 | /* Since this macro is used a lot in hot code paths and in conjunction with |
57 | * FooCPU *foo_env_get_cpu(), we deviate from usual QOM practice by using | |
58 | * an unchecked cast. | |
59 | */ | |
60 | #define CPU(obj) ((CPUState *)(obj)) | |
61 | ||
dd83b06a AF |
62 | #define CPU_CLASS(class) OBJECT_CLASS_CHECK(CPUClass, (class), TYPE_CPU) |
63 | #define CPU_GET_CLASS(obj) OBJECT_GET_CLASS(CPUClass, (obj), TYPE_CPU) | |
64 | ||
65 | typedef struct CPUState CPUState; | |
66 | ||
c658b94f AF |
67 | typedef void (*CPUUnassignedAccess)(CPUState *cpu, hwaddr addr, |
68 | bool is_write, bool is_exec, int opaque, | |
69 | unsigned size); | |
70 | ||
bdf7ae5b AF |
71 | struct TranslationBlock; |
72 | ||
dd83b06a AF |
73 | /** |
74 | * CPUClass: | |
2b8c2754 AF |
75 | * @class_by_name: Callback to map -cpu command line model name to an |
76 | * instantiatable CPU type. | |
94a444b2 | 77 | * @parse_features: Callback to parse command line arguments. |
f5df5baf | 78 | * @reset: Callback to reset the #CPUState to its initial state. |
91b1df8c | 79 | * @reset_dump_flags: #CPUDumpFlags to use for reset logging. |
8c2e1b00 | 80 | * @has_work: Callback for checking if there is work to do. |
97a8ea5a | 81 | * @do_interrupt: Callback for interrupt handling. |
c658b94f | 82 | * @do_unassigned_access: Callback for unassigned access handling. |
93e22326 PB |
83 | * @do_unaligned_access: Callback for unaligned access handling, if |
84 | * the target defines #ALIGNED_ONLY. | |
f3659eee | 85 | * @memory_rw_debug: Callback for GDB memory access. |
878096ee AF |
86 | * @dump_state: Callback for dumping state. |
87 | * @dump_statistics: Callback for dumping statistics. | |
997395d3 | 88 | * @get_arch_id: Callback for getting architecture-dependent CPU ID. |
444d5590 | 89 | * @get_paging_enabled: Callback for inquiring whether paging is enabled. |
a23bbfda | 90 | * @get_memory_mapping: Callback for obtaining the memory mappings. |
f45748f1 | 91 | * @set_pc: Callback for setting the Program Counter register. |
bdf7ae5b AF |
92 | * @synchronize_from_tb: Callback for synchronizing state from a TCG |
93 | * #TranslationBlock. | |
7510454e | 94 | * @handle_mmu_fault: Callback for handling an MMU fault. |
00b941e5 | 95 | * @get_phys_page_debug: Callback for obtaining a physical address. |
5b50e790 AF |
96 | * @gdb_read_register: Callback for letting GDB read a register. |
97 | * @gdb_write_register: Callback for letting GDB write a register. | |
86025ee4 | 98 | * @debug_excp_handler: Callback for handling debug exceptions. |
b170fce3 | 99 | * @vmsd: State description for migration. |
a0e372f0 | 100 | * @gdb_num_core_regs: Number of core registers accessible to GDB. |
5b24c641 | 101 | * @gdb_core_xml_file: File name for core registers GDB XML description. |
cffe7b32 RH |
102 | * @cpu_exec_enter: Callback for cpu_exec preparation. |
103 | * @cpu_exec_exit: Callback for cpu_exec cleanup. | |
dd83b06a AF |
104 | * |
105 | * Represents a CPU family or model. | |
106 | */ | |
107 | typedef struct CPUClass { | |
108 | /*< private >*/ | |
961f8395 | 109 | DeviceClass parent_class; |
dd83b06a AF |
110 | /*< public >*/ |
111 | ||
2b8c2754 | 112 | ObjectClass *(*class_by_name)(const char *cpu_model); |
94a444b2 | 113 | void (*parse_features)(CPUState *cpu, char *str, Error **errp); |
2b8c2754 | 114 | |
dd83b06a | 115 | void (*reset)(CPUState *cpu); |
91b1df8c | 116 | int reset_dump_flags; |
8c2e1b00 | 117 | bool (*has_work)(CPUState *cpu); |
97a8ea5a | 118 | void (*do_interrupt)(CPUState *cpu); |
c658b94f | 119 | CPUUnassignedAccess do_unassigned_access; |
93e22326 PB |
120 | void (*do_unaligned_access)(CPUState *cpu, vaddr addr, |
121 | int is_write, int is_user, uintptr_t retaddr); | |
bf7663c4 | 122 | bool (*virtio_is_big_endian)(CPUState *cpu); |
f3659eee AF |
123 | int (*memory_rw_debug)(CPUState *cpu, vaddr addr, |
124 | uint8_t *buf, int len, bool is_write); | |
878096ee AF |
125 | void (*dump_state)(CPUState *cpu, FILE *f, fprintf_function cpu_fprintf, |
126 | int flags); | |
127 | void (*dump_statistics)(CPUState *cpu, FILE *f, | |
128 | fprintf_function cpu_fprintf, int flags); | |
997395d3 | 129 | int64_t (*get_arch_id)(CPUState *cpu); |
444d5590 | 130 | bool (*get_paging_enabled)(const CPUState *cpu); |
a23bbfda AF |
131 | void (*get_memory_mapping)(CPUState *cpu, MemoryMappingList *list, |
132 | Error **errp); | |
f45748f1 | 133 | void (*set_pc)(CPUState *cpu, vaddr value); |
bdf7ae5b | 134 | void (*synchronize_from_tb)(CPUState *cpu, struct TranslationBlock *tb); |
7510454e AF |
135 | int (*handle_mmu_fault)(CPUState *cpu, vaddr address, int rw, |
136 | int mmu_index); | |
00b941e5 | 137 | hwaddr (*get_phys_page_debug)(CPUState *cpu, vaddr addr); |
5b50e790 AF |
138 | int (*gdb_read_register)(CPUState *cpu, uint8_t *buf, int reg); |
139 | int (*gdb_write_register)(CPUState *cpu, uint8_t *buf, int reg); | |
86025ee4 | 140 | void (*debug_excp_handler)(CPUState *cpu); |
b170fce3 | 141 | |
c72bf468 JF |
142 | int (*write_elf64_note)(WriteCoreDumpFunction f, CPUState *cpu, |
143 | int cpuid, void *opaque); | |
144 | int (*write_elf64_qemunote)(WriteCoreDumpFunction f, CPUState *cpu, | |
145 | void *opaque); | |
146 | int (*write_elf32_note)(WriteCoreDumpFunction f, CPUState *cpu, | |
147 | int cpuid, void *opaque); | |
148 | int (*write_elf32_qemunote)(WriteCoreDumpFunction f, CPUState *cpu, | |
149 | void *opaque); | |
a0e372f0 AF |
150 | |
151 | const struct VMStateDescription *vmsd; | |
152 | int gdb_num_core_regs; | |
5b24c641 | 153 | const char *gdb_core_xml_file; |
cffe7b32 RH |
154 | |
155 | void (*cpu_exec_enter)(CPUState *cpu); | |
156 | void (*cpu_exec_exit)(CPUState *cpu); | |
dd83b06a AF |
157 | } CPUClass; |
158 | ||
28ecfd7a AF |
159 | #ifdef HOST_WORDS_BIGENDIAN |
160 | typedef struct icount_decr_u16 { | |
161 | uint16_t high; | |
162 | uint16_t low; | |
163 | } icount_decr_u16; | |
164 | #else | |
165 | typedef struct icount_decr_u16 { | |
166 | uint16_t low; | |
167 | uint16_t high; | |
168 | } icount_decr_u16; | |
169 | #endif | |
170 | ||
f0c3c505 AF |
171 | typedef struct CPUBreakpoint { |
172 | vaddr pc; | |
173 | int flags; /* BP_* */ | |
174 | QTAILQ_ENTRY(CPUBreakpoint) entry; | |
175 | } CPUBreakpoint; | |
176 | ||
ff4700b0 AF |
177 | typedef struct CPUWatchpoint { |
178 | vaddr vaddr; | |
05068c0d | 179 | vaddr len; |
08225676 | 180 | vaddr hitaddr; |
ff4700b0 AF |
181 | int flags; /* BP_* */ |
182 | QTAILQ_ENTRY(CPUWatchpoint) entry; | |
183 | } CPUWatchpoint; | |
184 | ||
a60f24b5 | 185 | struct KVMState; |
f7575c96 | 186 | struct kvm_run; |
a60f24b5 | 187 | |
8cd70437 AF |
188 | #define TB_JMP_CACHE_BITS 12 |
189 | #define TB_JMP_CACHE_SIZE (1 << TB_JMP_CACHE_BITS) | |
190 | ||
dd83b06a AF |
191 | /** |
192 | * CPUState: | |
55e5c285 | 193 | * @cpu_index: CPU index (informative). |
ce3960eb AF |
194 | * @nr_cores: Number of cores within this CPU package. |
195 | * @nr_threads: Number of threads within this CPU. | |
1b1ed8dc | 196 | * @numa_node: NUMA node this CPU is belonging to. |
0d34282f | 197 | * @host_tid: Host thread ID. |
0315c31c | 198 | * @running: #true if CPU is currently running (usermode). |
61a46217 | 199 | * @created: Indicates whether the CPU thread has been successfully created. |
259186a7 AF |
200 | * @interrupt_request: Indicates a pending interrupt request. |
201 | * @halted: Nonzero if the CPU is in suspended state. | |
4fdeee7c | 202 | * @stop: Indicates a pending stop request. |
f324e766 | 203 | * @stopped: Indicates the CPU has been artificially stopped. |
378df4b2 PM |
204 | * @tcg_exit_req: Set to force TCG to stop executing linked TBs for this |
205 | * CPU and return to its top level loop. | |
ed2803da | 206 | * @singlestep_enabled: Flags for single-stepping. |
efee7340 | 207 | * @icount_extra: Instructions until next timer event. |
28ecfd7a AF |
208 | * @icount_decr: Number of cycles left, with interrupt flag in high bit. |
209 | * This allows a single read-compare-cbranch-write sequence to test | |
210 | * for both decrementer underflow and exceptions. | |
99df7dce | 211 | * @can_do_io: Nonzero if memory-mapped IO is safe. |
c05efcb1 | 212 | * @env_ptr: Pointer to subclass-specific CPUArchState field. |
d77953b9 | 213 | * @current_tb: Currently executing TB. |
eac8b355 | 214 | * @gdb_regs: Additional GDB registers. |
a0e372f0 | 215 | * @gdb_num_regs: Number of total registers accessible to GDB. |
35143f01 | 216 | * @gdb_num_g_regs: Number of registers in GDB 'g' packets. |
182735ef | 217 | * @next_cpu: Next CPU sharing TB cache. |
0429a971 | 218 | * @opaque: User data. |
93afeade AF |
219 | * @mem_io_pc: Host Program Counter at which the memory was accessed. |
220 | * @mem_io_vaddr: Target virtual address at which the memory was accessed. | |
8737c51c | 221 | * @kvm_fd: vCPU file descriptor for KVM. |
dd83b06a AF |
222 | * |
223 | * State of one CPU core or thread. | |
224 | */ | |
225 | struct CPUState { | |
226 | /*< private >*/ | |
961f8395 | 227 | DeviceState parent_obj; |
dd83b06a AF |
228 | /*< public >*/ |
229 | ||
ce3960eb AF |
230 | int nr_cores; |
231 | int nr_threads; | |
1b1ed8dc | 232 | int numa_node; |
ce3960eb | 233 | |
814e612e | 234 | struct QemuThread *thread; |
bcba2a72 AF |
235 | #ifdef _WIN32 |
236 | HANDLE hThread; | |
237 | #endif | |
9f09e18a | 238 | int thread_id; |
0d34282f | 239 | uint32_t host_tid; |
0315c31c | 240 | bool running; |
f5c121b8 | 241 | struct QemuCond *halt_cond; |
c64ca814 | 242 | struct qemu_work_item *queued_work_first, *queued_work_last; |
216fc9a4 | 243 | bool thread_kicked; |
61a46217 | 244 | bool created; |
4fdeee7c | 245 | bool stop; |
f324e766 | 246 | bool stopped; |
fcd7d003 | 247 | volatile sig_atomic_t exit_request; |
259186a7 | 248 | uint32_t interrupt_request; |
ed2803da | 249 | int singlestep_enabled; |
efee7340 | 250 | int64_t icount_extra; |
6f03bef0 | 251 | sigjmp_buf jmp_env; |
bcba2a72 | 252 | |
09daed84 EI |
253 | AddressSpace *as; |
254 | MemoryListener *tcg_as_listener; | |
255 | ||
c05efcb1 | 256 | void *env_ptr; /* CPUArchState */ |
d77953b9 | 257 | struct TranslationBlock *current_tb; |
8cd70437 | 258 | struct TranslationBlock *tb_jmp_cache[TB_JMP_CACHE_SIZE]; |
eac8b355 | 259 | struct GDBRegisterState *gdb_regs; |
a0e372f0 | 260 | int gdb_num_regs; |
35143f01 | 261 | int gdb_num_g_regs; |
bdc44640 | 262 | QTAILQ_ENTRY(CPUState) node; |
d77953b9 | 263 | |
f0c3c505 AF |
264 | /* ice debug support */ |
265 | QTAILQ_HEAD(breakpoints_head, CPUBreakpoint) breakpoints; | |
266 | ||
ff4700b0 AF |
267 | QTAILQ_HEAD(watchpoints_head, CPUWatchpoint) watchpoints; |
268 | CPUWatchpoint *watchpoint_hit; | |
269 | ||
0429a971 AF |
270 | void *opaque; |
271 | ||
93afeade AF |
272 | /* In order to avoid passing too many arguments to the MMIO helpers, |
273 | * we store some rarely used information in the CPU context. | |
274 | */ | |
275 | uintptr_t mem_io_pc; | |
276 | vaddr mem_io_vaddr; | |
277 | ||
8737c51c | 278 | int kvm_fd; |
20d695a9 | 279 | bool kvm_vcpu_dirty; |
a60f24b5 | 280 | struct KVMState *kvm_state; |
f7575c96 | 281 | struct kvm_run *kvm_run; |
8737c51c | 282 | |
f5df5baf | 283 | /* TODO Move common fields from CPUArchState here. */ |
55e5c285 | 284 | int cpu_index; /* used by alpha TCG */ |
259186a7 | 285 | uint32_t halted; /* used by alpha, cris, ppc TCG */ |
28ecfd7a AF |
286 | union { |
287 | uint32_t u32; | |
288 | icount_decr_u16 u16; | |
289 | } icount_decr; | |
99df7dce | 290 | uint32_t can_do_io; |
27103424 | 291 | int32_t exception_index; /* used by m68k TCG */ |
7e4fb26d RH |
292 | |
293 | /* Note that this is accessed at the start of every TB via a negative | |
294 | offset from AREG0. Leave this field at the end so as to make the | |
295 | (absolute value) offset as small as possible. This reduces code | |
296 | size, especially for hosts without large memory offsets. */ | |
297 | volatile sig_atomic_t tcg_exit_req; | |
dd83b06a AF |
298 | }; |
299 | ||
bdc44640 AF |
300 | QTAILQ_HEAD(CPUTailQ, CPUState); |
301 | extern struct CPUTailQ cpus; | |
302 | #define CPU_NEXT(cpu) QTAILQ_NEXT(cpu, node) | |
303 | #define CPU_FOREACH(cpu) QTAILQ_FOREACH(cpu, &cpus, node) | |
304 | #define CPU_FOREACH_SAFE(cpu, next_cpu) \ | |
305 | QTAILQ_FOREACH_SAFE(cpu, &cpus, node, next_cpu) | |
306 | #define first_cpu QTAILQ_FIRST(&cpus) | |
182735ef | 307 | |
4917cf44 AF |
308 | DECLARE_TLS(CPUState *, current_cpu); |
309 | #define current_cpu tls_var(current_cpu) | |
310 | ||
444d5590 AF |
311 | /** |
312 | * cpu_paging_enabled: | |
313 | * @cpu: The CPU whose state is to be inspected. | |
314 | * | |
315 | * Returns: %true if paging is enabled, %false otherwise. | |
316 | */ | |
317 | bool cpu_paging_enabled(const CPUState *cpu); | |
318 | ||
a23bbfda AF |
319 | /** |
320 | * cpu_get_memory_mapping: | |
321 | * @cpu: The CPU whose memory mappings are to be obtained. | |
322 | * @list: Where to write the memory mappings to. | |
323 | * @errp: Pointer for reporting an #Error. | |
324 | */ | |
325 | void cpu_get_memory_mapping(CPUState *cpu, MemoryMappingList *list, | |
326 | Error **errp); | |
327 | ||
c72bf468 JF |
328 | /** |
329 | * cpu_write_elf64_note: | |
330 | * @f: pointer to a function that writes memory to a file | |
331 | * @cpu: The CPU whose memory is to be dumped | |
332 | * @cpuid: ID number of the CPU | |
333 | * @opaque: pointer to the CPUState struct | |
334 | */ | |
335 | int cpu_write_elf64_note(WriteCoreDumpFunction f, CPUState *cpu, | |
336 | int cpuid, void *opaque); | |
337 | ||
338 | /** | |
339 | * cpu_write_elf64_qemunote: | |
340 | * @f: pointer to a function that writes memory to a file | |
341 | * @cpu: The CPU whose memory is to be dumped | |
342 | * @cpuid: ID number of the CPU | |
343 | * @opaque: pointer to the CPUState struct | |
344 | */ | |
345 | int cpu_write_elf64_qemunote(WriteCoreDumpFunction f, CPUState *cpu, | |
346 | void *opaque); | |
347 | ||
348 | /** | |
349 | * cpu_write_elf32_note: | |
350 | * @f: pointer to a function that writes memory to a file | |
351 | * @cpu: The CPU whose memory is to be dumped | |
352 | * @cpuid: ID number of the CPU | |
353 | * @opaque: pointer to the CPUState struct | |
354 | */ | |
355 | int cpu_write_elf32_note(WriteCoreDumpFunction f, CPUState *cpu, | |
356 | int cpuid, void *opaque); | |
357 | ||
358 | /** | |
359 | * cpu_write_elf32_qemunote: | |
360 | * @f: pointer to a function that writes memory to a file | |
361 | * @cpu: The CPU whose memory is to be dumped | |
362 | * @cpuid: ID number of the CPU | |
363 | * @opaque: pointer to the CPUState struct | |
364 | */ | |
365 | int cpu_write_elf32_qemunote(WriteCoreDumpFunction f, CPUState *cpu, | |
366 | void *opaque); | |
dd83b06a | 367 | |
878096ee AF |
368 | /** |
369 | * CPUDumpFlags: | |
370 | * @CPU_DUMP_CODE: | |
371 | * @CPU_DUMP_FPU: dump FPU register state, not just integer | |
372 | * @CPU_DUMP_CCOP: dump info about TCG QEMU's condition code optimization state | |
373 | */ | |
374 | enum CPUDumpFlags { | |
375 | CPU_DUMP_CODE = 0x00010000, | |
376 | CPU_DUMP_FPU = 0x00020000, | |
377 | CPU_DUMP_CCOP = 0x00040000, | |
378 | }; | |
379 | ||
380 | /** | |
381 | * cpu_dump_state: | |
382 | * @cpu: The CPU whose state is to be dumped. | |
383 | * @f: File to dump to. | |
384 | * @cpu_fprintf: Function to dump with. | |
385 | * @flags: Flags what to dump. | |
386 | * | |
387 | * Dumps CPU state. | |
388 | */ | |
389 | void cpu_dump_state(CPUState *cpu, FILE *f, fprintf_function cpu_fprintf, | |
390 | int flags); | |
391 | ||
392 | /** | |
393 | * cpu_dump_statistics: | |
394 | * @cpu: The CPU whose state is to be dumped. | |
395 | * @f: File to dump to. | |
396 | * @cpu_fprintf: Function to dump with. | |
397 | * @flags: Flags what to dump. | |
398 | * | |
399 | * Dumps CPU statistics. | |
400 | */ | |
401 | void cpu_dump_statistics(CPUState *cpu, FILE *f, fprintf_function cpu_fprintf, | |
402 | int flags); | |
403 | ||
00b941e5 AF |
404 | #ifndef CONFIG_USER_ONLY |
405 | /** | |
406 | * cpu_get_phys_page_debug: | |
407 | * @cpu: The CPU to obtain the physical page address for. | |
408 | * @addr: The virtual address. | |
409 | * | |
410 | * Obtains the physical page corresponding to a virtual one. | |
411 | * Use it only for debugging because no protection checks are done. | |
412 | * | |
413 | * Returns: Corresponding physical page address or -1 if no page found. | |
414 | */ | |
415 | static inline hwaddr cpu_get_phys_page_debug(CPUState *cpu, vaddr addr) | |
416 | { | |
417 | CPUClass *cc = CPU_GET_CLASS(cpu); | |
418 | ||
419 | return cc->get_phys_page_debug(cpu, addr); | |
420 | } | |
421 | #endif | |
422 | ||
dd83b06a AF |
423 | /** |
424 | * cpu_reset: | |
425 | * @cpu: The CPU whose state is to be reset. | |
426 | */ | |
427 | void cpu_reset(CPUState *cpu); | |
428 | ||
2b8c2754 AF |
429 | /** |
430 | * cpu_class_by_name: | |
431 | * @typename: The CPU base type. | |
432 | * @cpu_model: The model string without any parameters. | |
433 | * | |
434 | * Looks up a CPU #ObjectClass matching name @cpu_model. | |
435 | * | |
436 | * Returns: A #CPUClass or %NULL if not matching class is found. | |
437 | */ | |
438 | ObjectClass *cpu_class_by_name(const char *typename, const char *cpu_model); | |
439 | ||
9262685b AF |
440 | /** |
441 | * cpu_generic_init: | |
442 | * @typename: The CPU base type. | |
443 | * @cpu_model: The model string including optional parameters. | |
444 | * | |
445 | * Instantiates a CPU, processes optional parameters and realizes the CPU. | |
446 | * | |
447 | * Returns: A #CPUState or %NULL if an error occurred. | |
448 | */ | |
449 | CPUState *cpu_generic_init(const char *typename, const char *cpu_model); | |
450 | ||
3993c6bd | 451 | /** |
8c2e1b00 | 452 | * cpu_has_work: |
3993c6bd AF |
453 | * @cpu: The vCPU to check. |
454 | * | |
455 | * Checks whether the CPU has work to do. | |
456 | * | |
457 | * Returns: %true if the CPU has work, %false otherwise. | |
458 | */ | |
8c2e1b00 AF |
459 | static inline bool cpu_has_work(CPUState *cpu) |
460 | { | |
461 | CPUClass *cc = CPU_GET_CLASS(cpu); | |
462 | ||
463 | g_assert(cc->has_work); | |
464 | return cc->has_work(cpu); | |
465 | } | |
3993c6bd | 466 | |
60e82579 AF |
467 | /** |
468 | * qemu_cpu_is_self: | |
469 | * @cpu: The vCPU to check against. | |
470 | * | |
471 | * Checks whether the caller is executing on the vCPU thread. | |
472 | * | |
473 | * Returns: %true if called from @cpu's thread, %false otherwise. | |
474 | */ | |
475 | bool qemu_cpu_is_self(CPUState *cpu); | |
476 | ||
c08d7424 AF |
477 | /** |
478 | * qemu_cpu_kick: | |
479 | * @cpu: The vCPU to kick. | |
480 | * | |
481 | * Kicks @cpu's thread. | |
482 | */ | |
483 | void qemu_cpu_kick(CPUState *cpu); | |
484 | ||
2fa45344 AF |
485 | /** |
486 | * cpu_is_stopped: | |
487 | * @cpu: The CPU to check. | |
488 | * | |
489 | * Checks whether the CPU is stopped. | |
490 | * | |
491 | * Returns: %true if run state is not running or if artificially stopped; | |
492 | * %false otherwise. | |
493 | */ | |
494 | bool cpu_is_stopped(CPUState *cpu); | |
495 | ||
f100f0b3 AF |
496 | /** |
497 | * run_on_cpu: | |
498 | * @cpu: The vCPU to run on. | |
499 | * @func: The function to be executed. | |
500 | * @data: Data to pass to the function. | |
501 | * | |
502 | * Schedules the function @func for execution on the vCPU @cpu. | |
503 | */ | |
504 | void run_on_cpu(CPUState *cpu, void (*func)(void *data), void *data); | |
505 | ||
3c02270d CV |
506 | /** |
507 | * async_run_on_cpu: | |
508 | * @cpu: The vCPU to run on. | |
509 | * @func: The function to be executed. | |
510 | * @data: Data to pass to the function. | |
511 | * | |
512 | * Schedules the function @func for execution on the vCPU @cpu asynchronously. | |
513 | */ | |
514 | void async_run_on_cpu(CPUState *cpu, void (*func)(void *data), void *data); | |
515 | ||
38d8f5c8 AF |
516 | /** |
517 | * qemu_get_cpu: | |
518 | * @index: The CPUState@cpu_index value of the CPU to obtain. | |
519 | * | |
520 | * Gets a CPU matching @index. | |
521 | * | |
522 | * Returns: The CPU or %NULL if there is no matching CPU. | |
523 | */ | |
524 | CPUState *qemu_get_cpu(int index); | |
525 | ||
69e5ff06 IM |
526 | /** |
527 | * cpu_exists: | |
528 | * @id: Guest-exposed CPU ID to lookup. | |
529 | * | |
530 | * Search for CPU with specified ID. | |
531 | * | |
532 | * Returns: %true - CPU is found, %false - CPU isn't found. | |
533 | */ | |
534 | bool cpu_exists(int64_t id); | |
535 | ||
c3affe56 AF |
536 | #ifndef CONFIG_USER_ONLY |
537 | ||
538 | typedef void (*CPUInterruptHandler)(CPUState *, int); | |
539 | ||
540 | extern CPUInterruptHandler cpu_interrupt_handler; | |
541 | ||
542 | /** | |
543 | * cpu_interrupt: | |
544 | * @cpu: The CPU to set an interrupt on. | |
545 | * @mask: The interupts to set. | |
546 | * | |
547 | * Invokes the interrupt handler. | |
548 | */ | |
549 | static inline void cpu_interrupt(CPUState *cpu, int mask) | |
550 | { | |
551 | cpu_interrupt_handler(cpu, mask); | |
552 | } | |
553 | ||
554 | #else /* USER_ONLY */ | |
555 | ||
556 | void cpu_interrupt(CPUState *cpu, int mask); | |
557 | ||
558 | #endif /* USER_ONLY */ | |
559 | ||
93e22326 | 560 | #ifdef CONFIG_SOFTMMU |
c658b94f AF |
561 | static inline void cpu_unassigned_access(CPUState *cpu, hwaddr addr, |
562 | bool is_write, bool is_exec, | |
563 | int opaque, unsigned size) | |
564 | { | |
565 | CPUClass *cc = CPU_GET_CLASS(cpu); | |
566 | ||
567 | if (cc->do_unassigned_access) { | |
568 | cc->do_unassigned_access(cpu, addr, is_write, is_exec, opaque, size); | |
569 | } | |
570 | } | |
571 | ||
93e22326 PB |
572 | static inline void cpu_unaligned_access(CPUState *cpu, vaddr addr, |
573 | int is_write, int is_user, | |
574 | uintptr_t retaddr) | |
575 | { | |
576 | CPUClass *cc = CPU_GET_CLASS(cpu); | |
577 | ||
578 | return cc->do_unaligned_access(cpu, addr, is_write, is_user, retaddr); | |
579 | } | |
c658b94f AF |
580 | #endif |
581 | ||
d8ed887b AF |
582 | /** |
583 | * cpu_reset_interrupt: | |
584 | * @cpu: The CPU to clear the interrupt on. | |
585 | * @mask: The interrupt mask to clear. | |
586 | * | |
587 | * Resets interrupts on the vCPU @cpu. | |
588 | */ | |
589 | void cpu_reset_interrupt(CPUState *cpu, int mask); | |
590 | ||
60a3e17a AF |
591 | /** |
592 | * cpu_exit: | |
593 | * @cpu: The CPU to exit. | |
594 | * | |
595 | * Requests the CPU @cpu to exit execution. | |
596 | */ | |
597 | void cpu_exit(CPUState *cpu); | |
598 | ||
2993683b IM |
599 | /** |
600 | * cpu_resume: | |
601 | * @cpu: The CPU to resume. | |
602 | * | |
603 | * Resumes CPU, i.e. puts CPU into runnable state. | |
604 | */ | |
605 | void cpu_resume(CPUState *cpu); | |
dd83b06a | 606 | |
c643bed9 AF |
607 | /** |
608 | * qemu_init_vcpu: | |
609 | * @cpu: The vCPU to initialize. | |
610 | * | |
611 | * Initializes a vCPU. | |
612 | */ | |
613 | void qemu_init_vcpu(CPUState *cpu); | |
614 | ||
3825b28f AF |
615 | #define SSTEP_ENABLE 0x1 /* Enable simulated HW single stepping */ |
616 | #define SSTEP_NOIRQ 0x2 /* Do not use IRQ while single stepping */ | |
617 | #define SSTEP_NOTIMER 0x4 /* Do not Timers while single stepping */ | |
618 | ||
619 | /** | |
620 | * cpu_single_step: | |
621 | * @cpu: CPU to the flags for. | |
622 | * @enabled: Flags to enable. | |
623 | * | |
624 | * Enables or disables single-stepping for @cpu. | |
625 | */ | |
626 | void cpu_single_step(CPUState *cpu, int enabled); | |
627 | ||
b3310ab3 AF |
628 | /* Breakpoint/watchpoint flags */ |
629 | #define BP_MEM_READ 0x01 | |
630 | #define BP_MEM_WRITE 0x02 | |
631 | #define BP_MEM_ACCESS (BP_MEM_READ | BP_MEM_WRITE) | |
632 | #define BP_STOP_BEFORE_ACCESS 0x04 | |
08225676 | 633 | /* 0x08 currently unused */ |
b3310ab3 AF |
634 | #define BP_GDB 0x10 |
635 | #define BP_CPU 0x20 | |
08225676 PM |
636 | #define BP_WATCHPOINT_HIT_READ 0x40 |
637 | #define BP_WATCHPOINT_HIT_WRITE 0x80 | |
638 | #define BP_WATCHPOINT_HIT (BP_WATCHPOINT_HIT_READ | BP_WATCHPOINT_HIT_WRITE) | |
b3310ab3 AF |
639 | |
640 | int cpu_breakpoint_insert(CPUState *cpu, vaddr pc, int flags, | |
641 | CPUBreakpoint **breakpoint); | |
642 | int cpu_breakpoint_remove(CPUState *cpu, vaddr pc, int flags); | |
643 | void cpu_breakpoint_remove_by_ref(CPUState *cpu, CPUBreakpoint *breakpoint); | |
644 | void cpu_breakpoint_remove_all(CPUState *cpu, int mask); | |
645 | ||
75a34036 AF |
646 | int cpu_watchpoint_insert(CPUState *cpu, vaddr addr, vaddr len, |
647 | int flags, CPUWatchpoint **watchpoint); | |
648 | int cpu_watchpoint_remove(CPUState *cpu, vaddr addr, | |
649 | vaddr len, int flags); | |
650 | void cpu_watchpoint_remove_by_ref(CPUState *cpu, CPUWatchpoint *watchpoint); | |
651 | void cpu_watchpoint_remove_all(CPUState *cpu, int mask); | |
652 | ||
a47dddd7 AF |
653 | void QEMU_NORETURN cpu_abort(CPUState *cpu, const char *fmt, ...) |
654 | GCC_FMT_ATTR(2, 3); | |
655 | ||
1a1562f5 AF |
656 | #ifdef CONFIG_SOFTMMU |
657 | extern const struct VMStateDescription vmstate_cpu_common; | |
658 | #else | |
659 | #define vmstate_cpu_common vmstate_dummy | |
660 | #endif | |
661 | ||
662 | #define VMSTATE_CPU() { \ | |
663 | .name = "parent_obj", \ | |
664 | .size = sizeof(CPUState), \ | |
665 | .vmsd = &vmstate_cpu_common, \ | |
666 | .flags = VMS_STRUCT, \ | |
667 | .offset = 0, \ | |
668 | } | |
669 | ||
dd83b06a | 670 | #endif |