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dd83b06a AF |
1 | /* |
2 | * QEMU CPU model | |
3 | * | |
4 | * Copyright (c) 2012 SUSE LINUX Products GmbH | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or | |
7 | * modify it under the terms of the GNU General Public License | |
8 | * as published by the Free Software Foundation; either version 2 | |
9 | * of the License, or (at your option) any later version. | |
10 | * | |
11 | * This program is distributed in the hope that it will be useful, | |
12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
14 | * GNU General Public License for more details. | |
15 | * | |
16 | * You should have received a copy of the GNU General Public License | |
17 | * along with this program; if not, see | |
18 | * <http://www.gnu.org/licenses/gpl-2.0.html> | |
19 | */ | |
20 | #ifndef QEMU_CPU_H | |
21 | #define QEMU_CPU_H | |
22 | ||
fcd7d003 | 23 | #include <signal.h> |
6f03bef0 | 24 | #include <setjmp.h> |
961f8395 | 25 | #include "hw/qdev-core.h" |
c658b94f | 26 | #include "exec/hwaddr.h" |
bdc44640 | 27 | #include "qemu/queue.h" |
1de7afc9 | 28 | #include "qemu/thread.h" |
4917cf44 | 29 | #include "qemu/tls.h" |
a23bbfda | 30 | #include "qemu/typedefs.h" |
dd83b06a | 31 | |
b5ba1cc6 QN |
32 | typedef int (*WriteCoreDumpFunction)(const void *buf, size_t size, |
33 | void *opaque); | |
c72bf468 | 34 | |
577f42c0 AF |
35 | /** |
36 | * vaddr: | |
37 | * Type wide enough to contain any #target_ulong virtual address. | |
38 | */ | |
39 | typedef uint64_t vaddr; | |
40 | #define VADDR_PRId PRId64 | |
41 | #define VADDR_PRIu PRIu64 | |
42 | #define VADDR_PRIo PRIo64 | |
43 | #define VADDR_PRIx PRIx64 | |
44 | #define VADDR_PRIX PRIX64 | |
45 | #define VADDR_MAX UINT64_MAX | |
46 | ||
dd83b06a AF |
47 | /** |
48 | * SECTION:cpu | |
49 | * @section_id: QEMU-cpu | |
50 | * @title: CPU Class | |
51 | * @short_description: Base class for all CPUs | |
52 | */ | |
53 | ||
54 | #define TYPE_CPU "cpu" | |
55 | ||
0d6d1ab4 AF |
56 | /* Since this macro is used a lot in hot code paths and in conjunction with |
57 | * FooCPU *foo_env_get_cpu(), we deviate from usual QOM practice by using | |
58 | * an unchecked cast. | |
59 | */ | |
60 | #define CPU(obj) ((CPUState *)(obj)) | |
61 | ||
dd83b06a AF |
62 | #define CPU_CLASS(class) OBJECT_CLASS_CHECK(CPUClass, (class), TYPE_CPU) |
63 | #define CPU_GET_CLASS(obj) OBJECT_GET_CLASS(CPUClass, (obj), TYPE_CPU) | |
64 | ||
65 | typedef struct CPUState CPUState; | |
66 | ||
c658b94f AF |
67 | typedef void (*CPUUnassignedAccess)(CPUState *cpu, hwaddr addr, |
68 | bool is_write, bool is_exec, int opaque, | |
69 | unsigned size); | |
70 | ||
bdf7ae5b AF |
71 | struct TranslationBlock; |
72 | ||
dd83b06a AF |
73 | /** |
74 | * CPUClass: | |
2b8c2754 AF |
75 | * @class_by_name: Callback to map -cpu command line model name to an |
76 | * instantiatable CPU type. | |
94a444b2 | 77 | * @parse_features: Callback to parse command line arguments. |
f5df5baf | 78 | * @reset: Callback to reset the #CPUState to its initial state. |
91b1df8c | 79 | * @reset_dump_flags: #CPUDumpFlags to use for reset logging. |
8c2e1b00 | 80 | * @has_work: Callback for checking if there is work to do. |
97a8ea5a | 81 | * @do_interrupt: Callback for interrupt handling. |
c658b94f | 82 | * @do_unassigned_access: Callback for unassigned access handling. |
f3659eee | 83 | * @memory_rw_debug: Callback for GDB memory access. |
878096ee AF |
84 | * @dump_state: Callback for dumping state. |
85 | * @dump_statistics: Callback for dumping statistics. | |
997395d3 | 86 | * @get_arch_id: Callback for getting architecture-dependent CPU ID. |
444d5590 | 87 | * @get_paging_enabled: Callback for inquiring whether paging is enabled. |
a23bbfda | 88 | * @get_memory_mapping: Callback for obtaining the memory mappings. |
f45748f1 | 89 | * @set_pc: Callback for setting the Program Counter register. |
bdf7ae5b AF |
90 | * @synchronize_from_tb: Callback for synchronizing state from a TCG |
91 | * #TranslationBlock. | |
7510454e | 92 | * @handle_mmu_fault: Callback for handling an MMU fault. |
00b941e5 | 93 | * @get_phys_page_debug: Callback for obtaining a physical address. |
5b50e790 AF |
94 | * @gdb_read_register: Callback for letting GDB read a register. |
95 | * @gdb_write_register: Callback for letting GDB write a register. | |
b170fce3 | 96 | * @vmsd: State description for migration. |
a0e372f0 | 97 | * @gdb_num_core_regs: Number of core registers accessible to GDB. |
5b24c641 | 98 | * @gdb_core_xml_file: File name for core registers GDB XML description. |
dd83b06a AF |
99 | * |
100 | * Represents a CPU family or model. | |
101 | */ | |
102 | typedef struct CPUClass { | |
103 | /*< private >*/ | |
961f8395 | 104 | DeviceClass parent_class; |
dd83b06a AF |
105 | /*< public >*/ |
106 | ||
2b8c2754 | 107 | ObjectClass *(*class_by_name)(const char *cpu_model); |
94a444b2 | 108 | void (*parse_features)(CPUState *cpu, char *str, Error **errp); |
2b8c2754 | 109 | |
dd83b06a | 110 | void (*reset)(CPUState *cpu); |
91b1df8c | 111 | int reset_dump_flags; |
8c2e1b00 | 112 | bool (*has_work)(CPUState *cpu); |
97a8ea5a | 113 | void (*do_interrupt)(CPUState *cpu); |
c658b94f | 114 | CPUUnassignedAccess do_unassigned_access; |
f3659eee AF |
115 | int (*memory_rw_debug)(CPUState *cpu, vaddr addr, |
116 | uint8_t *buf, int len, bool is_write); | |
878096ee AF |
117 | void (*dump_state)(CPUState *cpu, FILE *f, fprintf_function cpu_fprintf, |
118 | int flags); | |
119 | void (*dump_statistics)(CPUState *cpu, FILE *f, | |
120 | fprintf_function cpu_fprintf, int flags); | |
997395d3 | 121 | int64_t (*get_arch_id)(CPUState *cpu); |
444d5590 | 122 | bool (*get_paging_enabled)(const CPUState *cpu); |
a23bbfda AF |
123 | void (*get_memory_mapping)(CPUState *cpu, MemoryMappingList *list, |
124 | Error **errp); | |
f45748f1 | 125 | void (*set_pc)(CPUState *cpu, vaddr value); |
bdf7ae5b | 126 | void (*synchronize_from_tb)(CPUState *cpu, struct TranslationBlock *tb); |
7510454e AF |
127 | int (*handle_mmu_fault)(CPUState *cpu, vaddr address, int rw, |
128 | int mmu_index); | |
00b941e5 | 129 | hwaddr (*get_phys_page_debug)(CPUState *cpu, vaddr addr); |
5b50e790 AF |
130 | int (*gdb_read_register)(CPUState *cpu, uint8_t *buf, int reg); |
131 | int (*gdb_write_register)(CPUState *cpu, uint8_t *buf, int reg); | |
b170fce3 | 132 | |
c72bf468 JF |
133 | int (*write_elf64_note)(WriteCoreDumpFunction f, CPUState *cpu, |
134 | int cpuid, void *opaque); | |
135 | int (*write_elf64_qemunote)(WriteCoreDumpFunction f, CPUState *cpu, | |
136 | void *opaque); | |
137 | int (*write_elf32_note)(WriteCoreDumpFunction f, CPUState *cpu, | |
138 | int cpuid, void *opaque); | |
139 | int (*write_elf32_qemunote)(WriteCoreDumpFunction f, CPUState *cpu, | |
140 | void *opaque); | |
a0e372f0 AF |
141 | |
142 | const struct VMStateDescription *vmsd; | |
143 | int gdb_num_core_regs; | |
5b24c641 | 144 | const char *gdb_core_xml_file; |
dd83b06a AF |
145 | } CPUClass; |
146 | ||
28ecfd7a AF |
147 | #ifdef HOST_WORDS_BIGENDIAN |
148 | typedef struct icount_decr_u16 { | |
149 | uint16_t high; | |
150 | uint16_t low; | |
151 | } icount_decr_u16; | |
152 | #else | |
153 | typedef struct icount_decr_u16 { | |
154 | uint16_t low; | |
155 | uint16_t high; | |
156 | } icount_decr_u16; | |
157 | #endif | |
158 | ||
f0c3c505 AF |
159 | typedef struct CPUBreakpoint { |
160 | vaddr pc; | |
161 | int flags; /* BP_* */ | |
162 | QTAILQ_ENTRY(CPUBreakpoint) entry; | |
163 | } CPUBreakpoint; | |
164 | ||
ff4700b0 AF |
165 | typedef struct CPUWatchpoint { |
166 | vaddr vaddr; | |
167 | vaddr len_mask; | |
168 | int flags; /* BP_* */ | |
169 | QTAILQ_ENTRY(CPUWatchpoint) entry; | |
170 | } CPUWatchpoint; | |
171 | ||
a60f24b5 | 172 | struct KVMState; |
f7575c96 | 173 | struct kvm_run; |
a60f24b5 | 174 | |
8cd70437 AF |
175 | #define TB_JMP_CACHE_BITS 12 |
176 | #define TB_JMP_CACHE_SIZE (1 << TB_JMP_CACHE_BITS) | |
177 | ||
dd83b06a AF |
178 | /** |
179 | * CPUState: | |
55e5c285 | 180 | * @cpu_index: CPU index (informative). |
ce3960eb AF |
181 | * @nr_cores: Number of cores within this CPU package. |
182 | * @nr_threads: Number of threads within this CPU. | |
1b1ed8dc | 183 | * @numa_node: NUMA node this CPU is belonging to. |
0d34282f | 184 | * @host_tid: Host thread ID. |
0315c31c | 185 | * @running: #true if CPU is currently running (usermode). |
61a46217 | 186 | * @created: Indicates whether the CPU thread has been successfully created. |
259186a7 AF |
187 | * @interrupt_request: Indicates a pending interrupt request. |
188 | * @halted: Nonzero if the CPU is in suspended state. | |
4fdeee7c | 189 | * @stop: Indicates a pending stop request. |
f324e766 | 190 | * @stopped: Indicates the CPU has been artificially stopped. |
378df4b2 PM |
191 | * @tcg_exit_req: Set to force TCG to stop executing linked TBs for this |
192 | * CPU and return to its top level loop. | |
ed2803da | 193 | * @singlestep_enabled: Flags for single-stepping. |
efee7340 | 194 | * @icount_extra: Instructions until next timer event. |
28ecfd7a AF |
195 | * @icount_decr: Number of cycles left, with interrupt flag in high bit. |
196 | * This allows a single read-compare-cbranch-write sequence to test | |
197 | * for both decrementer underflow and exceptions. | |
99df7dce | 198 | * @can_do_io: Nonzero if memory-mapped IO is safe. |
c05efcb1 | 199 | * @env_ptr: Pointer to subclass-specific CPUArchState field. |
d77953b9 | 200 | * @current_tb: Currently executing TB. |
eac8b355 | 201 | * @gdb_regs: Additional GDB registers. |
a0e372f0 | 202 | * @gdb_num_regs: Number of total registers accessible to GDB. |
35143f01 | 203 | * @gdb_num_g_regs: Number of registers in GDB 'g' packets. |
182735ef | 204 | * @next_cpu: Next CPU sharing TB cache. |
0429a971 | 205 | * @opaque: User data. |
93afeade AF |
206 | * @mem_io_pc: Host Program Counter at which the memory was accessed. |
207 | * @mem_io_vaddr: Target virtual address at which the memory was accessed. | |
8737c51c | 208 | * @kvm_fd: vCPU file descriptor for KVM. |
dd83b06a AF |
209 | * |
210 | * State of one CPU core or thread. | |
211 | */ | |
212 | struct CPUState { | |
213 | /*< private >*/ | |
961f8395 | 214 | DeviceState parent_obj; |
dd83b06a AF |
215 | /*< public >*/ |
216 | ||
ce3960eb AF |
217 | int nr_cores; |
218 | int nr_threads; | |
1b1ed8dc | 219 | int numa_node; |
ce3960eb | 220 | |
814e612e | 221 | struct QemuThread *thread; |
bcba2a72 AF |
222 | #ifdef _WIN32 |
223 | HANDLE hThread; | |
224 | #endif | |
9f09e18a | 225 | int thread_id; |
0d34282f | 226 | uint32_t host_tid; |
0315c31c | 227 | bool running; |
f5c121b8 | 228 | struct QemuCond *halt_cond; |
c64ca814 | 229 | struct qemu_work_item *queued_work_first, *queued_work_last; |
216fc9a4 | 230 | bool thread_kicked; |
61a46217 | 231 | bool created; |
4fdeee7c | 232 | bool stop; |
f324e766 | 233 | bool stopped; |
fcd7d003 | 234 | volatile sig_atomic_t exit_request; |
259186a7 | 235 | uint32_t interrupt_request; |
ed2803da | 236 | int singlestep_enabled; |
efee7340 | 237 | int64_t icount_extra; |
6f03bef0 | 238 | sigjmp_buf jmp_env; |
bcba2a72 | 239 | |
09daed84 EI |
240 | AddressSpace *as; |
241 | MemoryListener *tcg_as_listener; | |
242 | ||
c05efcb1 | 243 | void *env_ptr; /* CPUArchState */ |
d77953b9 | 244 | struct TranslationBlock *current_tb; |
8cd70437 | 245 | struct TranslationBlock *tb_jmp_cache[TB_JMP_CACHE_SIZE]; |
eac8b355 | 246 | struct GDBRegisterState *gdb_regs; |
a0e372f0 | 247 | int gdb_num_regs; |
35143f01 | 248 | int gdb_num_g_regs; |
bdc44640 | 249 | QTAILQ_ENTRY(CPUState) node; |
d77953b9 | 250 | |
f0c3c505 AF |
251 | /* ice debug support */ |
252 | QTAILQ_HEAD(breakpoints_head, CPUBreakpoint) breakpoints; | |
253 | ||
ff4700b0 AF |
254 | QTAILQ_HEAD(watchpoints_head, CPUWatchpoint) watchpoints; |
255 | CPUWatchpoint *watchpoint_hit; | |
256 | ||
0429a971 AF |
257 | void *opaque; |
258 | ||
93afeade AF |
259 | /* In order to avoid passing too many arguments to the MMIO helpers, |
260 | * we store some rarely used information in the CPU context. | |
261 | */ | |
262 | uintptr_t mem_io_pc; | |
263 | vaddr mem_io_vaddr; | |
264 | ||
8737c51c | 265 | int kvm_fd; |
20d695a9 | 266 | bool kvm_vcpu_dirty; |
a60f24b5 | 267 | struct KVMState *kvm_state; |
f7575c96 | 268 | struct kvm_run *kvm_run; |
8737c51c | 269 | |
f5df5baf | 270 | /* TODO Move common fields from CPUArchState here. */ |
55e5c285 | 271 | int cpu_index; /* used by alpha TCG */ |
259186a7 | 272 | uint32_t halted; /* used by alpha, cris, ppc TCG */ |
28ecfd7a AF |
273 | union { |
274 | uint32_t u32; | |
275 | icount_decr_u16 u16; | |
276 | } icount_decr; | |
99df7dce | 277 | uint32_t can_do_io; |
27103424 | 278 | int32_t exception_index; /* used by m68k TCG */ |
7e4fb26d RH |
279 | |
280 | /* Note that this is accessed at the start of every TB via a negative | |
281 | offset from AREG0. Leave this field at the end so as to make the | |
282 | (absolute value) offset as small as possible. This reduces code | |
283 | size, especially for hosts without large memory offsets. */ | |
284 | volatile sig_atomic_t tcg_exit_req; | |
dd83b06a AF |
285 | }; |
286 | ||
bdc44640 AF |
287 | QTAILQ_HEAD(CPUTailQ, CPUState); |
288 | extern struct CPUTailQ cpus; | |
289 | #define CPU_NEXT(cpu) QTAILQ_NEXT(cpu, node) | |
290 | #define CPU_FOREACH(cpu) QTAILQ_FOREACH(cpu, &cpus, node) | |
291 | #define CPU_FOREACH_SAFE(cpu, next_cpu) \ | |
292 | QTAILQ_FOREACH_SAFE(cpu, &cpus, node, next_cpu) | |
293 | #define first_cpu QTAILQ_FIRST(&cpus) | |
182735ef | 294 | |
4917cf44 AF |
295 | DECLARE_TLS(CPUState *, current_cpu); |
296 | #define current_cpu tls_var(current_cpu) | |
297 | ||
444d5590 AF |
298 | /** |
299 | * cpu_paging_enabled: | |
300 | * @cpu: The CPU whose state is to be inspected. | |
301 | * | |
302 | * Returns: %true if paging is enabled, %false otherwise. | |
303 | */ | |
304 | bool cpu_paging_enabled(const CPUState *cpu); | |
305 | ||
a23bbfda AF |
306 | /** |
307 | * cpu_get_memory_mapping: | |
308 | * @cpu: The CPU whose memory mappings are to be obtained. | |
309 | * @list: Where to write the memory mappings to. | |
310 | * @errp: Pointer for reporting an #Error. | |
311 | */ | |
312 | void cpu_get_memory_mapping(CPUState *cpu, MemoryMappingList *list, | |
313 | Error **errp); | |
314 | ||
c72bf468 JF |
315 | /** |
316 | * cpu_write_elf64_note: | |
317 | * @f: pointer to a function that writes memory to a file | |
318 | * @cpu: The CPU whose memory is to be dumped | |
319 | * @cpuid: ID number of the CPU | |
320 | * @opaque: pointer to the CPUState struct | |
321 | */ | |
322 | int cpu_write_elf64_note(WriteCoreDumpFunction f, CPUState *cpu, | |
323 | int cpuid, void *opaque); | |
324 | ||
325 | /** | |
326 | * cpu_write_elf64_qemunote: | |
327 | * @f: pointer to a function that writes memory to a file | |
328 | * @cpu: The CPU whose memory is to be dumped | |
329 | * @cpuid: ID number of the CPU | |
330 | * @opaque: pointer to the CPUState struct | |
331 | */ | |
332 | int cpu_write_elf64_qemunote(WriteCoreDumpFunction f, CPUState *cpu, | |
333 | void *opaque); | |
334 | ||
335 | /** | |
336 | * cpu_write_elf32_note: | |
337 | * @f: pointer to a function that writes memory to a file | |
338 | * @cpu: The CPU whose memory is to be dumped | |
339 | * @cpuid: ID number of the CPU | |
340 | * @opaque: pointer to the CPUState struct | |
341 | */ | |
342 | int cpu_write_elf32_note(WriteCoreDumpFunction f, CPUState *cpu, | |
343 | int cpuid, void *opaque); | |
344 | ||
345 | /** | |
346 | * cpu_write_elf32_qemunote: | |
347 | * @f: pointer to a function that writes memory to a file | |
348 | * @cpu: The CPU whose memory is to be dumped | |
349 | * @cpuid: ID number of the CPU | |
350 | * @opaque: pointer to the CPUState struct | |
351 | */ | |
352 | int cpu_write_elf32_qemunote(WriteCoreDumpFunction f, CPUState *cpu, | |
353 | void *opaque); | |
dd83b06a | 354 | |
878096ee AF |
355 | /** |
356 | * CPUDumpFlags: | |
357 | * @CPU_DUMP_CODE: | |
358 | * @CPU_DUMP_FPU: dump FPU register state, not just integer | |
359 | * @CPU_DUMP_CCOP: dump info about TCG QEMU's condition code optimization state | |
360 | */ | |
361 | enum CPUDumpFlags { | |
362 | CPU_DUMP_CODE = 0x00010000, | |
363 | CPU_DUMP_FPU = 0x00020000, | |
364 | CPU_DUMP_CCOP = 0x00040000, | |
365 | }; | |
366 | ||
367 | /** | |
368 | * cpu_dump_state: | |
369 | * @cpu: The CPU whose state is to be dumped. | |
370 | * @f: File to dump to. | |
371 | * @cpu_fprintf: Function to dump with. | |
372 | * @flags: Flags what to dump. | |
373 | * | |
374 | * Dumps CPU state. | |
375 | */ | |
376 | void cpu_dump_state(CPUState *cpu, FILE *f, fprintf_function cpu_fprintf, | |
377 | int flags); | |
378 | ||
379 | /** | |
380 | * cpu_dump_statistics: | |
381 | * @cpu: The CPU whose state is to be dumped. | |
382 | * @f: File to dump to. | |
383 | * @cpu_fprintf: Function to dump with. | |
384 | * @flags: Flags what to dump. | |
385 | * | |
386 | * Dumps CPU statistics. | |
387 | */ | |
388 | void cpu_dump_statistics(CPUState *cpu, FILE *f, fprintf_function cpu_fprintf, | |
389 | int flags); | |
390 | ||
00b941e5 AF |
391 | #ifndef CONFIG_USER_ONLY |
392 | /** | |
393 | * cpu_get_phys_page_debug: | |
394 | * @cpu: The CPU to obtain the physical page address for. | |
395 | * @addr: The virtual address. | |
396 | * | |
397 | * Obtains the physical page corresponding to a virtual one. | |
398 | * Use it only for debugging because no protection checks are done. | |
399 | * | |
400 | * Returns: Corresponding physical page address or -1 if no page found. | |
401 | */ | |
402 | static inline hwaddr cpu_get_phys_page_debug(CPUState *cpu, vaddr addr) | |
403 | { | |
404 | CPUClass *cc = CPU_GET_CLASS(cpu); | |
405 | ||
406 | return cc->get_phys_page_debug(cpu, addr); | |
407 | } | |
408 | #endif | |
409 | ||
dd83b06a AF |
410 | /** |
411 | * cpu_reset: | |
412 | * @cpu: The CPU whose state is to be reset. | |
413 | */ | |
414 | void cpu_reset(CPUState *cpu); | |
415 | ||
2b8c2754 AF |
416 | /** |
417 | * cpu_class_by_name: | |
418 | * @typename: The CPU base type. | |
419 | * @cpu_model: The model string without any parameters. | |
420 | * | |
421 | * Looks up a CPU #ObjectClass matching name @cpu_model. | |
422 | * | |
423 | * Returns: A #CPUClass or %NULL if not matching class is found. | |
424 | */ | |
425 | ObjectClass *cpu_class_by_name(const char *typename, const char *cpu_model); | |
426 | ||
9262685b AF |
427 | /** |
428 | * cpu_generic_init: | |
429 | * @typename: The CPU base type. | |
430 | * @cpu_model: The model string including optional parameters. | |
431 | * | |
432 | * Instantiates a CPU, processes optional parameters and realizes the CPU. | |
433 | * | |
434 | * Returns: A #CPUState or %NULL if an error occurred. | |
435 | */ | |
436 | CPUState *cpu_generic_init(const char *typename, const char *cpu_model); | |
437 | ||
3993c6bd | 438 | /** |
8c2e1b00 | 439 | * cpu_has_work: |
3993c6bd AF |
440 | * @cpu: The vCPU to check. |
441 | * | |
442 | * Checks whether the CPU has work to do. | |
443 | * | |
444 | * Returns: %true if the CPU has work, %false otherwise. | |
445 | */ | |
8c2e1b00 AF |
446 | static inline bool cpu_has_work(CPUState *cpu) |
447 | { | |
448 | CPUClass *cc = CPU_GET_CLASS(cpu); | |
449 | ||
450 | g_assert(cc->has_work); | |
451 | return cc->has_work(cpu); | |
452 | } | |
3993c6bd | 453 | |
60e82579 AF |
454 | /** |
455 | * qemu_cpu_is_self: | |
456 | * @cpu: The vCPU to check against. | |
457 | * | |
458 | * Checks whether the caller is executing on the vCPU thread. | |
459 | * | |
460 | * Returns: %true if called from @cpu's thread, %false otherwise. | |
461 | */ | |
462 | bool qemu_cpu_is_self(CPUState *cpu); | |
463 | ||
c08d7424 AF |
464 | /** |
465 | * qemu_cpu_kick: | |
466 | * @cpu: The vCPU to kick. | |
467 | * | |
468 | * Kicks @cpu's thread. | |
469 | */ | |
470 | void qemu_cpu_kick(CPUState *cpu); | |
471 | ||
2fa45344 AF |
472 | /** |
473 | * cpu_is_stopped: | |
474 | * @cpu: The CPU to check. | |
475 | * | |
476 | * Checks whether the CPU is stopped. | |
477 | * | |
478 | * Returns: %true if run state is not running or if artificially stopped; | |
479 | * %false otherwise. | |
480 | */ | |
481 | bool cpu_is_stopped(CPUState *cpu); | |
482 | ||
f100f0b3 AF |
483 | /** |
484 | * run_on_cpu: | |
485 | * @cpu: The vCPU to run on. | |
486 | * @func: The function to be executed. | |
487 | * @data: Data to pass to the function. | |
488 | * | |
489 | * Schedules the function @func for execution on the vCPU @cpu. | |
490 | */ | |
491 | void run_on_cpu(CPUState *cpu, void (*func)(void *data), void *data); | |
492 | ||
3c02270d CV |
493 | /** |
494 | * async_run_on_cpu: | |
495 | * @cpu: The vCPU to run on. | |
496 | * @func: The function to be executed. | |
497 | * @data: Data to pass to the function. | |
498 | * | |
499 | * Schedules the function @func for execution on the vCPU @cpu asynchronously. | |
500 | */ | |
501 | void async_run_on_cpu(CPUState *cpu, void (*func)(void *data), void *data); | |
502 | ||
38d8f5c8 AF |
503 | /** |
504 | * qemu_get_cpu: | |
505 | * @index: The CPUState@cpu_index value of the CPU to obtain. | |
506 | * | |
507 | * Gets a CPU matching @index. | |
508 | * | |
509 | * Returns: The CPU or %NULL if there is no matching CPU. | |
510 | */ | |
511 | CPUState *qemu_get_cpu(int index); | |
512 | ||
69e5ff06 IM |
513 | /** |
514 | * cpu_exists: | |
515 | * @id: Guest-exposed CPU ID to lookup. | |
516 | * | |
517 | * Search for CPU with specified ID. | |
518 | * | |
519 | * Returns: %true - CPU is found, %false - CPU isn't found. | |
520 | */ | |
521 | bool cpu_exists(int64_t id); | |
522 | ||
c3affe56 AF |
523 | #ifndef CONFIG_USER_ONLY |
524 | ||
525 | typedef void (*CPUInterruptHandler)(CPUState *, int); | |
526 | ||
527 | extern CPUInterruptHandler cpu_interrupt_handler; | |
528 | ||
529 | /** | |
530 | * cpu_interrupt: | |
531 | * @cpu: The CPU to set an interrupt on. | |
532 | * @mask: The interupts to set. | |
533 | * | |
534 | * Invokes the interrupt handler. | |
535 | */ | |
536 | static inline void cpu_interrupt(CPUState *cpu, int mask) | |
537 | { | |
538 | cpu_interrupt_handler(cpu, mask); | |
539 | } | |
540 | ||
541 | #else /* USER_ONLY */ | |
542 | ||
543 | void cpu_interrupt(CPUState *cpu, int mask); | |
544 | ||
545 | #endif /* USER_ONLY */ | |
546 | ||
c658b94f AF |
547 | #ifndef CONFIG_USER_ONLY |
548 | ||
549 | static inline void cpu_unassigned_access(CPUState *cpu, hwaddr addr, | |
550 | bool is_write, bool is_exec, | |
551 | int opaque, unsigned size) | |
552 | { | |
553 | CPUClass *cc = CPU_GET_CLASS(cpu); | |
554 | ||
555 | if (cc->do_unassigned_access) { | |
556 | cc->do_unassigned_access(cpu, addr, is_write, is_exec, opaque, size); | |
557 | } | |
558 | } | |
559 | ||
560 | #endif | |
561 | ||
d8ed887b AF |
562 | /** |
563 | * cpu_reset_interrupt: | |
564 | * @cpu: The CPU to clear the interrupt on. | |
565 | * @mask: The interrupt mask to clear. | |
566 | * | |
567 | * Resets interrupts on the vCPU @cpu. | |
568 | */ | |
569 | void cpu_reset_interrupt(CPUState *cpu, int mask); | |
570 | ||
60a3e17a AF |
571 | /** |
572 | * cpu_exit: | |
573 | * @cpu: The CPU to exit. | |
574 | * | |
575 | * Requests the CPU @cpu to exit execution. | |
576 | */ | |
577 | void cpu_exit(CPUState *cpu); | |
578 | ||
2993683b IM |
579 | /** |
580 | * cpu_resume: | |
581 | * @cpu: The CPU to resume. | |
582 | * | |
583 | * Resumes CPU, i.e. puts CPU into runnable state. | |
584 | */ | |
585 | void cpu_resume(CPUState *cpu); | |
dd83b06a | 586 | |
c643bed9 AF |
587 | /** |
588 | * qemu_init_vcpu: | |
589 | * @cpu: The vCPU to initialize. | |
590 | * | |
591 | * Initializes a vCPU. | |
592 | */ | |
593 | void qemu_init_vcpu(CPUState *cpu); | |
594 | ||
3825b28f AF |
595 | #define SSTEP_ENABLE 0x1 /* Enable simulated HW single stepping */ |
596 | #define SSTEP_NOIRQ 0x2 /* Do not use IRQ while single stepping */ | |
597 | #define SSTEP_NOTIMER 0x4 /* Do not Timers while single stepping */ | |
598 | ||
599 | /** | |
600 | * cpu_single_step: | |
601 | * @cpu: CPU to the flags for. | |
602 | * @enabled: Flags to enable. | |
603 | * | |
604 | * Enables or disables single-stepping for @cpu. | |
605 | */ | |
606 | void cpu_single_step(CPUState *cpu, int enabled); | |
607 | ||
b3310ab3 AF |
608 | /* Breakpoint/watchpoint flags */ |
609 | #define BP_MEM_READ 0x01 | |
610 | #define BP_MEM_WRITE 0x02 | |
611 | #define BP_MEM_ACCESS (BP_MEM_READ | BP_MEM_WRITE) | |
612 | #define BP_STOP_BEFORE_ACCESS 0x04 | |
613 | #define BP_WATCHPOINT_HIT 0x08 | |
614 | #define BP_GDB 0x10 | |
615 | #define BP_CPU 0x20 | |
616 | ||
617 | int cpu_breakpoint_insert(CPUState *cpu, vaddr pc, int flags, | |
618 | CPUBreakpoint **breakpoint); | |
619 | int cpu_breakpoint_remove(CPUState *cpu, vaddr pc, int flags); | |
620 | void cpu_breakpoint_remove_by_ref(CPUState *cpu, CPUBreakpoint *breakpoint); | |
621 | void cpu_breakpoint_remove_all(CPUState *cpu, int mask); | |
622 | ||
75a34036 AF |
623 | int cpu_watchpoint_insert(CPUState *cpu, vaddr addr, vaddr len, |
624 | int flags, CPUWatchpoint **watchpoint); | |
625 | int cpu_watchpoint_remove(CPUState *cpu, vaddr addr, | |
626 | vaddr len, int flags); | |
627 | void cpu_watchpoint_remove_by_ref(CPUState *cpu, CPUWatchpoint *watchpoint); | |
628 | void cpu_watchpoint_remove_all(CPUState *cpu, int mask); | |
629 | ||
a47dddd7 AF |
630 | void QEMU_NORETURN cpu_abort(CPUState *cpu, const char *fmt, ...) |
631 | GCC_FMT_ATTR(2, 3); | |
632 | ||
1a1562f5 AF |
633 | #ifdef CONFIG_SOFTMMU |
634 | extern const struct VMStateDescription vmstate_cpu_common; | |
635 | #else | |
636 | #define vmstate_cpu_common vmstate_dummy | |
637 | #endif | |
638 | ||
639 | #define VMSTATE_CPU() { \ | |
640 | .name = "parent_obj", \ | |
641 | .size = sizeof(CPUState), \ | |
642 | .vmsd = &vmstate_cpu_common, \ | |
643 | .flags = VMS_STRUCT, \ | |
644 | .offset = 0, \ | |
645 | } | |
646 | ||
dd83b06a | 647 | #endif |