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dd83b06a AF |
1 | /* |
2 | * QEMU CPU model | |
3 | * | |
4 | * Copyright (c) 2012 SUSE LINUX Products GmbH | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or | |
7 | * modify it under the terms of the GNU General Public License | |
8 | * as published by the Free Software Foundation; either version 2 | |
9 | * of the License, or (at your option) any later version. | |
10 | * | |
11 | * This program is distributed in the hope that it will be useful, | |
12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
14 | * GNU General Public License for more details. | |
15 | * | |
16 | * You should have received a copy of the GNU General Public License | |
17 | * along with this program; if not, see | |
18 | * <http://www.gnu.org/licenses/gpl-2.0.html> | |
19 | */ | |
20 | #ifndef QEMU_CPU_H | |
21 | #define QEMU_CPU_H | |
22 | ||
961f8395 | 23 | #include "hw/qdev-core.h" |
37b9de46 | 24 | #include "disas/bfd.h" |
c658b94f | 25 | #include "exec/hwaddr.h" |
66b9b43c | 26 | #include "exec/memattrs.h" |
bdc44640 | 27 | #include "qemu/queue.h" |
1de7afc9 | 28 | #include "qemu/thread.h" |
dd83b06a | 29 | |
b5ba1cc6 QN |
30 | typedef int (*WriteCoreDumpFunction)(const void *buf, size_t size, |
31 | void *opaque); | |
c72bf468 | 32 | |
577f42c0 AF |
33 | /** |
34 | * vaddr: | |
35 | * Type wide enough to contain any #target_ulong virtual address. | |
36 | */ | |
37 | typedef uint64_t vaddr; | |
38 | #define VADDR_PRId PRId64 | |
39 | #define VADDR_PRIu PRIu64 | |
40 | #define VADDR_PRIo PRIo64 | |
41 | #define VADDR_PRIx PRIx64 | |
42 | #define VADDR_PRIX PRIX64 | |
43 | #define VADDR_MAX UINT64_MAX | |
44 | ||
dd83b06a AF |
45 | /** |
46 | * SECTION:cpu | |
47 | * @section_id: QEMU-cpu | |
48 | * @title: CPU Class | |
49 | * @short_description: Base class for all CPUs | |
50 | */ | |
51 | ||
52 | #define TYPE_CPU "cpu" | |
53 | ||
0d6d1ab4 AF |
54 | /* Since this macro is used a lot in hot code paths and in conjunction with |
55 | * FooCPU *foo_env_get_cpu(), we deviate from usual QOM practice by using | |
56 | * an unchecked cast. | |
57 | */ | |
58 | #define CPU(obj) ((CPUState *)(obj)) | |
59 | ||
dd83b06a AF |
60 | #define CPU_CLASS(class) OBJECT_CLASS_CHECK(CPUClass, (class), TYPE_CPU) |
61 | #define CPU_GET_CLASS(obj) OBJECT_GET_CLASS(CPUClass, (obj), TYPE_CPU) | |
62 | ||
b35399bb SS |
63 | typedef enum MMUAccessType { |
64 | MMU_DATA_LOAD = 0, | |
65 | MMU_DATA_STORE = 1, | |
66 | MMU_INST_FETCH = 2 | |
67 | } MMUAccessType; | |
68 | ||
568496c0 | 69 | typedef struct CPUWatchpoint CPUWatchpoint; |
dd83b06a | 70 | |
c658b94f AF |
71 | typedef void (*CPUUnassignedAccess)(CPUState *cpu, hwaddr addr, |
72 | bool is_write, bool is_exec, int opaque, | |
73 | unsigned size); | |
74 | ||
bdf7ae5b AF |
75 | struct TranslationBlock; |
76 | ||
dd83b06a AF |
77 | /** |
78 | * CPUClass: | |
2b8c2754 AF |
79 | * @class_by_name: Callback to map -cpu command line model name to an |
80 | * instantiatable CPU type. | |
94a444b2 | 81 | * @parse_features: Callback to parse command line arguments. |
f5df5baf | 82 | * @reset: Callback to reset the #CPUState to its initial state. |
91b1df8c | 83 | * @reset_dump_flags: #CPUDumpFlags to use for reset logging. |
8c2e1b00 | 84 | * @has_work: Callback for checking if there is work to do. |
97a8ea5a | 85 | * @do_interrupt: Callback for interrupt handling. |
c658b94f | 86 | * @do_unassigned_access: Callback for unassigned access handling. |
93e22326 PB |
87 | * @do_unaligned_access: Callback for unaligned access handling, if |
88 | * the target defines #ALIGNED_ONLY. | |
c08295d4 PM |
89 | * @virtio_is_big_endian: Callback to return %true if a CPU which supports |
90 | * runtime configurable endianness is currently big-endian. Non-configurable | |
91 | * CPUs can use the default implementation of this method. This method should | |
92 | * not be used by any callers other than the pre-1.0 virtio devices. | |
f3659eee | 93 | * @memory_rw_debug: Callback for GDB memory access. |
878096ee AF |
94 | * @dump_state: Callback for dumping state. |
95 | * @dump_statistics: Callback for dumping statistics. | |
997395d3 | 96 | * @get_arch_id: Callback for getting architecture-dependent CPU ID. |
444d5590 | 97 | * @get_paging_enabled: Callback for inquiring whether paging is enabled. |
a23bbfda | 98 | * @get_memory_mapping: Callback for obtaining the memory mappings. |
f45748f1 | 99 | * @set_pc: Callback for setting the Program Counter register. |
bdf7ae5b AF |
100 | * @synchronize_from_tb: Callback for synchronizing state from a TCG |
101 | * #TranslationBlock. | |
7510454e | 102 | * @handle_mmu_fault: Callback for handling an MMU fault. |
00b941e5 | 103 | * @get_phys_page_debug: Callback for obtaining a physical address. |
1dc6fb1f PM |
104 | * @get_phys_page_attrs_debug: Callback for obtaining a physical address and the |
105 | * associated memory transaction attributes to use for the access. | |
106 | * CPUs which use memory transaction attributes should implement this | |
107 | * instead of get_phys_page_debug. | |
d7f25a9e PM |
108 | * @asidx_from_attrs: Callback to return the CPU AddressSpace to use for |
109 | * a memory access with the specified memory transaction attributes. | |
5b50e790 AF |
110 | * @gdb_read_register: Callback for letting GDB read a register. |
111 | * @gdb_write_register: Callback for letting GDB write a register. | |
568496c0 SF |
112 | * @debug_check_watchpoint: Callback: return true if the architectural |
113 | * watchpoint whose address has matched should really fire. | |
86025ee4 | 114 | * @debug_excp_handler: Callback for handling debug exceptions. |
c08295d4 PM |
115 | * @write_elf64_note: Callback for writing a CPU-specific ELF note to a |
116 | * 64-bit VM coredump. | |
117 | * @write_elf32_qemunote: Callback for writing a CPU- and QEMU-specific ELF | |
118 | * note to a 32-bit VM coredump. | |
119 | * @write_elf32_note: Callback for writing a CPU-specific ELF note to a | |
120 | * 32-bit VM coredump. | |
121 | * @write_elf32_qemunote: Callback for writing a CPU- and QEMU-specific ELF | |
122 | * note to a 32-bit VM coredump. | |
b170fce3 | 123 | * @vmsd: State description for migration. |
a0e372f0 | 124 | * @gdb_num_core_regs: Number of core registers accessible to GDB. |
5b24c641 | 125 | * @gdb_core_xml_file: File name for core registers GDB XML description. |
2472b6c0 PM |
126 | * @gdb_stop_before_watchpoint: Indicates whether GDB expects the CPU to stop |
127 | * before the insn which triggers a watchpoint rather than after it. | |
b3820e6c DH |
128 | * @gdb_arch_name: Optional callback that returns the architecture name known |
129 | * to GDB. The caller must free the returned string with g_free. | |
cffe7b32 RH |
130 | * @cpu_exec_enter: Callback for cpu_exec preparation. |
131 | * @cpu_exec_exit: Callback for cpu_exec cleanup. | |
9585db68 | 132 | * @cpu_exec_interrupt: Callback for processing interrupts in cpu_exec. |
37b9de46 | 133 | * @disas_set_info: Setup architecture specific components of disassembly info |
dd83b06a AF |
134 | * |
135 | * Represents a CPU family or model. | |
136 | */ | |
137 | typedef struct CPUClass { | |
138 | /*< private >*/ | |
961f8395 | 139 | DeviceClass parent_class; |
dd83b06a AF |
140 | /*< public >*/ |
141 | ||
2b8c2754 | 142 | ObjectClass *(*class_by_name)(const char *cpu_model); |
62a48a2a | 143 | void (*parse_features)(const char *typename, char *str, Error **errp); |
2b8c2754 | 144 | |
dd83b06a | 145 | void (*reset)(CPUState *cpu); |
91b1df8c | 146 | int reset_dump_flags; |
8c2e1b00 | 147 | bool (*has_work)(CPUState *cpu); |
97a8ea5a | 148 | void (*do_interrupt)(CPUState *cpu); |
c658b94f | 149 | CPUUnassignedAccess do_unassigned_access; |
93e22326 | 150 | void (*do_unaligned_access)(CPUState *cpu, vaddr addr, |
b35399bb SS |
151 | MMUAccessType access_type, |
152 | int mmu_idx, uintptr_t retaddr); | |
bf7663c4 | 153 | bool (*virtio_is_big_endian)(CPUState *cpu); |
f3659eee AF |
154 | int (*memory_rw_debug)(CPUState *cpu, vaddr addr, |
155 | uint8_t *buf, int len, bool is_write); | |
878096ee AF |
156 | void (*dump_state)(CPUState *cpu, FILE *f, fprintf_function cpu_fprintf, |
157 | int flags); | |
158 | void (*dump_statistics)(CPUState *cpu, FILE *f, | |
159 | fprintf_function cpu_fprintf, int flags); | |
997395d3 | 160 | int64_t (*get_arch_id)(CPUState *cpu); |
444d5590 | 161 | bool (*get_paging_enabled)(const CPUState *cpu); |
a23bbfda AF |
162 | void (*get_memory_mapping)(CPUState *cpu, MemoryMappingList *list, |
163 | Error **errp); | |
f45748f1 | 164 | void (*set_pc)(CPUState *cpu, vaddr value); |
bdf7ae5b | 165 | void (*synchronize_from_tb)(CPUState *cpu, struct TranslationBlock *tb); |
7510454e AF |
166 | int (*handle_mmu_fault)(CPUState *cpu, vaddr address, int rw, |
167 | int mmu_index); | |
00b941e5 | 168 | hwaddr (*get_phys_page_debug)(CPUState *cpu, vaddr addr); |
1dc6fb1f PM |
169 | hwaddr (*get_phys_page_attrs_debug)(CPUState *cpu, vaddr addr, |
170 | MemTxAttrs *attrs); | |
d7f25a9e | 171 | int (*asidx_from_attrs)(CPUState *cpu, MemTxAttrs attrs); |
5b50e790 AF |
172 | int (*gdb_read_register)(CPUState *cpu, uint8_t *buf, int reg); |
173 | int (*gdb_write_register)(CPUState *cpu, uint8_t *buf, int reg); | |
568496c0 | 174 | bool (*debug_check_watchpoint)(CPUState *cpu, CPUWatchpoint *wp); |
86025ee4 | 175 | void (*debug_excp_handler)(CPUState *cpu); |
b170fce3 | 176 | |
c72bf468 JF |
177 | int (*write_elf64_note)(WriteCoreDumpFunction f, CPUState *cpu, |
178 | int cpuid, void *opaque); | |
179 | int (*write_elf64_qemunote)(WriteCoreDumpFunction f, CPUState *cpu, | |
180 | void *opaque); | |
181 | int (*write_elf32_note)(WriteCoreDumpFunction f, CPUState *cpu, | |
182 | int cpuid, void *opaque); | |
183 | int (*write_elf32_qemunote)(WriteCoreDumpFunction f, CPUState *cpu, | |
184 | void *opaque); | |
a0e372f0 AF |
185 | |
186 | const struct VMStateDescription *vmsd; | |
187 | int gdb_num_core_regs; | |
5b24c641 | 188 | const char *gdb_core_xml_file; |
b3820e6c | 189 | gchar * (*gdb_arch_name)(CPUState *cpu); |
2472b6c0 | 190 | bool gdb_stop_before_watchpoint; |
cffe7b32 RH |
191 | |
192 | void (*cpu_exec_enter)(CPUState *cpu); | |
193 | void (*cpu_exec_exit)(CPUState *cpu); | |
9585db68 | 194 | bool (*cpu_exec_interrupt)(CPUState *cpu, int interrupt_request); |
37b9de46 PC |
195 | |
196 | void (*disas_set_info)(CPUState *cpu, disassemble_info *info); | |
dd83b06a AF |
197 | } CPUClass; |
198 | ||
28ecfd7a AF |
199 | #ifdef HOST_WORDS_BIGENDIAN |
200 | typedef struct icount_decr_u16 { | |
201 | uint16_t high; | |
202 | uint16_t low; | |
203 | } icount_decr_u16; | |
204 | #else | |
205 | typedef struct icount_decr_u16 { | |
206 | uint16_t low; | |
207 | uint16_t high; | |
208 | } icount_decr_u16; | |
209 | #endif | |
210 | ||
f0c3c505 AF |
211 | typedef struct CPUBreakpoint { |
212 | vaddr pc; | |
213 | int flags; /* BP_* */ | |
214 | QTAILQ_ENTRY(CPUBreakpoint) entry; | |
215 | } CPUBreakpoint; | |
216 | ||
568496c0 | 217 | struct CPUWatchpoint { |
ff4700b0 | 218 | vaddr vaddr; |
05068c0d | 219 | vaddr len; |
08225676 | 220 | vaddr hitaddr; |
66b9b43c | 221 | MemTxAttrs hitattrs; |
ff4700b0 AF |
222 | int flags; /* BP_* */ |
223 | QTAILQ_ENTRY(CPUWatchpoint) entry; | |
568496c0 | 224 | }; |
ff4700b0 | 225 | |
a60f24b5 | 226 | struct KVMState; |
f7575c96 | 227 | struct kvm_run; |
a60f24b5 | 228 | |
8cd70437 AF |
229 | #define TB_JMP_CACHE_BITS 12 |
230 | #define TB_JMP_CACHE_SIZE (1 << TB_JMP_CACHE_BITS) | |
231 | ||
4b4629d9 PB |
232 | /* work queue */ |
233 | struct qemu_work_item { | |
234 | struct qemu_work_item *next; | |
235 | void (*func)(void *data); | |
236 | void *data; | |
237 | int done; | |
238 | bool free; | |
239 | }; | |
240 | ||
dd83b06a AF |
241 | /** |
242 | * CPUState: | |
55e5c285 | 243 | * @cpu_index: CPU index (informative). |
ce3960eb AF |
244 | * @nr_cores: Number of cores within this CPU package. |
245 | * @nr_threads: Number of threads within this CPU. | |
1b1ed8dc | 246 | * @numa_node: NUMA node this CPU is belonging to. |
0d34282f | 247 | * @host_tid: Host thread ID. |
0315c31c | 248 | * @running: #true if CPU is currently running (usermode). |
61a46217 | 249 | * @created: Indicates whether the CPU thread has been successfully created. |
259186a7 AF |
250 | * @interrupt_request: Indicates a pending interrupt request. |
251 | * @halted: Nonzero if the CPU is in suspended state. | |
4fdeee7c | 252 | * @stop: Indicates a pending stop request. |
f324e766 | 253 | * @stopped: Indicates the CPU has been artificially stopped. |
4c055ab5 | 254 | * @unplug: Indicates a pending CPU unplug request. |
bac05aa9 | 255 | * @crash_occurred: Indicates the OS reported a crash (panic) for this CPU |
378df4b2 PM |
256 | * @tcg_exit_req: Set to force TCG to stop executing linked TBs for this |
257 | * CPU and return to its top level loop. | |
6f789be5 | 258 | * @tb_flushed: Indicates the translation buffer has been flushed. |
ed2803da | 259 | * @singlestep_enabled: Flags for single-stepping. |
efee7340 | 260 | * @icount_extra: Instructions until next timer event. |
28ecfd7a AF |
261 | * @icount_decr: Number of cycles left, with interrupt flag in high bit. |
262 | * This allows a single read-compare-cbranch-write sequence to test | |
263 | * for both decrementer underflow and exceptions. | |
414b15c9 PB |
264 | * @can_do_io: Nonzero if memory-mapped IO is safe. Deterministic execution |
265 | * requires that IO only be performed on the last instruction of a TB | |
266 | * so that interrupts take effect immediately. | |
32857f4d PM |
267 | * @cpu_ases: Pointer to array of CPUAddressSpaces (which define the |
268 | * AddressSpaces this CPU has) | |
12ebc9a7 | 269 | * @num_ases: number of CPUAddressSpaces in @cpu_ases |
32857f4d PM |
270 | * @as: Pointer to the first AddressSpace, for the convenience of targets which |
271 | * only have a single AddressSpace | |
c05efcb1 | 272 | * @env_ptr: Pointer to subclass-specific CPUArchState field. |
eac8b355 | 273 | * @gdb_regs: Additional GDB registers. |
a0e372f0 | 274 | * @gdb_num_regs: Number of total registers accessible to GDB. |
35143f01 | 275 | * @gdb_num_g_regs: Number of registers in GDB 'g' packets. |
182735ef | 276 | * @next_cpu: Next CPU sharing TB cache. |
0429a971 | 277 | * @opaque: User data. |
93afeade AF |
278 | * @mem_io_pc: Host Program Counter at which the memory was accessed. |
279 | * @mem_io_vaddr: Target virtual address at which the memory was accessed. | |
8737c51c | 280 | * @kvm_fd: vCPU file descriptor for KVM. |
376692b9 PB |
281 | * @work_mutex: Lock to prevent multiple access to queued_work_*. |
282 | * @queued_work_first: First asynchronous work pending. | |
dd83b06a AF |
283 | * |
284 | * State of one CPU core or thread. | |
285 | */ | |
286 | struct CPUState { | |
287 | /*< private >*/ | |
961f8395 | 288 | DeviceState parent_obj; |
dd83b06a AF |
289 | /*< public >*/ |
290 | ||
ce3960eb AF |
291 | int nr_cores; |
292 | int nr_threads; | |
1b1ed8dc | 293 | int numa_node; |
ce3960eb | 294 | |
814e612e | 295 | struct QemuThread *thread; |
bcba2a72 AF |
296 | #ifdef _WIN32 |
297 | HANDLE hThread; | |
298 | #endif | |
9f09e18a | 299 | int thread_id; |
0d34282f | 300 | uint32_t host_tid; |
0315c31c | 301 | bool running; |
f5c121b8 | 302 | struct QemuCond *halt_cond; |
216fc9a4 | 303 | bool thread_kicked; |
61a46217 | 304 | bool created; |
4fdeee7c | 305 | bool stop; |
f324e766 | 306 | bool stopped; |
4c055ab5 | 307 | bool unplug; |
bac05aa9 | 308 | bool crash_occurred; |
e0c38211 | 309 | bool exit_request; |
6f789be5 | 310 | bool tb_flushed; |
259186a7 | 311 | uint32_t interrupt_request; |
ed2803da | 312 | int singlestep_enabled; |
efee7340 | 313 | int64_t icount_extra; |
6f03bef0 | 314 | sigjmp_buf jmp_env; |
bcba2a72 | 315 | |
376692b9 PB |
316 | QemuMutex work_mutex; |
317 | struct qemu_work_item *queued_work_first, *queued_work_last; | |
318 | ||
32857f4d | 319 | CPUAddressSpace *cpu_ases; |
12ebc9a7 | 320 | int num_ases; |
09daed84 | 321 | AddressSpace *as; |
6731d864 | 322 | MemoryRegion *memory; |
09daed84 | 323 | |
c05efcb1 | 324 | void *env_ptr; /* CPUArchState */ |
8cd70437 | 325 | struct TranslationBlock *tb_jmp_cache[TB_JMP_CACHE_SIZE]; |
eac8b355 | 326 | struct GDBRegisterState *gdb_regs; |
a0e372f0 | 327 | int gdb_num_regs; |
35143f01 | 328 | int gdb_num_g_regs; |
bdc44640 | 329 | QTAILQ_ENTRY(CPUState) node; |
d77953b9 | 330 | |
f0c3c505 AF |
331 | /* ice debug support */ |
332 | QTAILQ_HEAD(breakpoints_head, CPUBreakpoint) breakpoints; | |
333 | ||
ff4700b0 AF |
334 | QTAILQ_HEAD(watchpoints_head, CPUWatchpoint) watchpoints; |
335 | CPUWatchpoint *watchpoint_hit; | |
336 | ||
0429a971 AF |
337 | void *opaque; |
338 | ||
93afeade AF |
339 | /* In order to avoid passing too many arguments to the MMIO helpers, |
340 | * we store some rarely used information in the CPU context. | |
341 | */ | |
342 | uintptr_t mem_io_pc; | |
343 | vaddr mem_io_vaddr; | |
344 | ||
8737c51c | 345 | int kvm_fd; |
20d695a9 | 346 | bool kvm_vcpu_dirty; |
a60f24b5 | 347 | struct KVMState *kvm_state; |
f7575c96 | 348 | struct kvm_run *kvm_run; |
8737c51c | 349 | |
f5df5baf | 350 | /* TODO Move common fields from CPUArchState here. */ |
55e5c285 | 351 | int cpu_index; /* used by alpha TCG */ |
259186a7 | 352 | uint32_t halted; /* used by alpha, cris, ppc TCG */ |
28ecfd7a AF |
353 | union { |
354 | uint32_t u32; | |
355 | icount_decr_u16 u16; | |
356 | } icount_decr; | |
99df7dce | 357 | uint32_t can_do_io; |
27103424 | 358 | int32_t exception_index; /* used by m68k TCG */ |
7e4fb26d | 359 | |
2adcc85d JH |
360 | /* Used to keep track of an outstanding cpu throttle thread for migration |
361 | * autoconverge | |
362 | */ | |
363 | bool throttle_thread_scheduled; | |
364 | ||
7e4fb26d RH |
365 | /* Note that this is accessed at the start of every TB via a negative |
366 | offset from AREG0. Leave this field at the end so as to make the | |
367 | (absolute value) offset as small as possible. This reduces code | |
368 | size, especially for hosts without large memory offsets. */ | |
e0c38211 | 369 | uint32_t tcg_exit_req; |
dd83b06a AF |
370 | }; |
371 | ||
bdc44640 AF |
372 | QTAILQ_HEAD(CPUTailQ, CPUState); |
373 | extern struct CPUTailQ cpus; | |
374 | #define CPU_NEXT(cpu) QTAILQ_NEXT(cpu, node) | |
375 | #define CPU_FOREACH(cpu) QTAILQ_FOREACH(cpu, &cpus, node) | |
376 | #define CPU_FOREACH_SAFE(cpu, next_cpu) \ | |
377 | QTAILQ_FOREACH_SAFE(cpu, &cpus, node, next_cpu) | |
8487d123 BR |
378 | #define CPU_FOREACH_REVERSE(cpu) \ |
379 | QTAILQ_FOREACH_REVERSE(cpu, &cpus, CPUTailQ, node) | |
bdc44640 | 380 | #define first_cpu QTAILQ_FIRST(&cpus) |
182735ef | 381 | |
f240eb6f | 382 | extern __thread CPUState *current_cpu; |
4917cf44 | 383 | |
444d5590 AF |
384 | /** |
385 | * cpu_paging_enabled: | |
386 | * @cpu: The CPU whose state is to be inspected. | |
387 | * | |
388 | * Returns: %true if paging is enabled, %false otherwise. | |
389 | */ | |
390 | bool cpu_paging_enabled(const CPUState *cpu); | |
391 | ||
a23bbfda AF |
392 | /** |
393 | * cpu_get_memory_mapping: | |
394 | * @cpu: The CPU whose memory mappings are to be obtained. | |
395 | * @list: Where to write the memory mappings to. | |
396 | * @errp: Pointer for reporting an #Error. | |
397 | */ | |
398 | void cpu_get_memory_mapping(CPUState *cpu, MemoryMappingList *list, | |
399 | Error **errp); | |
400 | ||
c72bf468 JF |
401 | /** |
402 | * cpu_write_elf64_note: | |
403 | * @f: pointer to a function that writes memory to a file | |
404 | * @cpu: The CPU whose memory is to be dumped | |
405 | * @cpuid: ID number of the CPU | |
406 | * @opaque: pointer to the CPUState struct | |
407 | */ | |
408 | int cpu_write_elf64_note(WriteCoreDumpFunction f, CPUState *cpu, | |
409 | int cpuid, void *opaque); | |
410 | ||
411 | /** | |
412 | * cpu_write_elf64_qemunote: | |
413 | * @f: pointer to a function that writes memory to a file | |
414 | * @cpu: The CPU whose memory is to be dumped | |
415 | * @cpuid: ID number of the CPU | |
416 | * @opaque: pointer to the CPUState struct | |
417 | */ | |
418 | int cpu_write_elf64_qemunote(WriteCoreDumpFunction f, CPUState *cpu, | |
419 | void *opaque); | |
420 | ||
421 | /** | |
422 | * cpu_write_elf32_note: | |
423 | * @f: pointer to a function that writes memory to a file | |
424 | * @cpu: The CPU whose memory is to be dumped | |
425 | * @cpuid: ID number of the CPU | |
426 | * @opaque: pointer to the CPUState struct | |
427 | */ | |
428 | int cpu_write_elf32_note(WriteCoreDumpFunction f, CPUState *cpu, | |
429 | int cpuid, void *opaque); | |
430 | ||
431 | /** | |
432 | * cpu_write_elf32_qemunote: | |
433 | * @f: pointer to a function that writes memory to a file | |
434 | * @cpu: The CPU whose memory is to be dumped | |
435 | * @cpuid: ID number of the CPU | |
436 | * @opaque: pointer to the CPUState struct | |
437 | */ | |
438 | int cpu_write_elf32_qemunote(WriteCoreDumpFunction f, CPUState *cpu, | |
439 | void *opaque); | |
dd83b06a | 440 | |
878096ee AF |
441 | /** |
442 | * CPUDumpFlags: | |
443 | * @CPU_DUMP_CODE: | |
444 | * @CPU_DUMP_FPU: dump FPU register state, not just integer | |
445 | * @CPU_DUMP_CCOP: dump info about TCG QEMU's condition code optimization state | |
446 | */ | |
447 | enum CPUDumpFlags { | |
448 | CPU_DUMP_CODE = 0x00010000, | |
449 | CPU_DUMP_FPU = 0x00020000, | |
450 | CPU_DUMP_CCOP = 0x00040000, | |
451 | }; | |
452 | ||
453 | /** | |
454 | * cpu_dump_state: | |
455 | * @cpu: The CPU whose state is to be dumped. | |
456 | * @f: File to dump to. | |
457 | * @cpu_fprintf: Function to dump with. | |
458 | * @flags: Flags what to dump. | |
459 | * | |
460 | * Dumps CPU state. | |
461 | */ | |
462 | void cpu_dump_state(CPUState *cpu, FILE *f, fprintf_function cpu_fprintf, | |
463 | int flags); | |
464 | ||
465 | /** | |
466 | * cpu_dump_statistics: | |
467 | * @cpu: The CPU whose state is to be dumped. | |
468 | * @f: File to dump to. | |
469 | * @cpu_fprintf: Function to dump with. | |
470 | * @flags: Flags what to dump. | |
471 | * | |
472 | * Dumps CPU statistics. | |
473 | */ | |
474 | void cpu_dump_statistics(CPUState *cpu, FILE *f, fprintf_function cpu_fprintf, | |
475 | int flags); | |
476 | ||
00b941e5 | 477 | #ifndef CONFIG_USER_ONLY |
1dc6fb1f PM |
478 | /** |
479 | * cpu_get_phys_page_attrs_debug: | |
480 | * @cpu: The CPU to obtain the physical page address for. | |
481 | * @addr: The virtual address. | |
482 | * @attrs: Updated on return with the memory transaction attributes to use | |
483 | * for this access. | |
484 | * | |
485 | * Obtains the physical page corresponding to a virtual one, together | |
486 | * with the corresponding memory transaction attributes to use for the access. | |
487 | * Use it only for debugging because no protection checks are done. | |
488 | * | |
489 | * Returns: Corresponding physical page address or -1 if no page found. | |
490 | */ | |
491 | static inline hwaddr cpu_get_phys_page_attrs_debug(CPUState *cpu, vaddr addr, | |
492 | MemTxAttrs *attrs) | |
493 | { | |
494 | CPUClass *cc = CPU_GET_CLASS(cpu); | |
495 | ||
496 | if (cc->get_phys_page_attrs_debug) { | |
497 | return cc->get_phys_page_attrs_debug(cpu, addr, attrs); | |
498 | } | |
499 | /* Fallback for CPUs which don't implement the _attrs_ hook */ | |
500 | *attrs = MEMTXATTRS_UNSPECIFIED; | |
501 | return cc->get_phys_page_debug(cpu, addr); | |
502 | } | |
503 | ||
00b941e5 AF |
504 | /** |
505 | * cpu_get_phys_page_debug: | |
506 | * @cpu: The CPU to obtain the physical page address for. | |
507 | * @addr: The virtual address. | |
508 | * | |
509 | * Obtains the physical page corresponding to a virtual one. | |
510 | * Use it only for debugging because no protection checks are done. | |
511 | * | |
512 | * Returns: Corresponding physical page address or -1 if no page found. | |
513 | */ | |
514 | static inline hwaddr cpu_get_phys_page_debug(CPUState *cpu, vaddr addr) | |
515 | { | |
1dc6fb1f | 516 | MemTxAttrs attrs = {}; |
00b941e5 | 517 | |
1dc6fb1f | 518 | return cpu_get_phys_page_attrs_debug(cpu, addr, &attrs); |
00b941e5 | 519 | } |
d7f25a9e PM |
520 | |
521 | /** cpu_asidx_from_attrs: | |
522 | * @cpu: CPU | |
523 | * @attrs: memory transaction attributes | |
524 | * | |
525 | * Returns the address space index specifying the CPU AddressSpace | |
526 | * to use for a memory access with the given transaction attributes. | |
527 | */ | |
528 | static inline int cpu_asidx_from_attrs(CPUState *cpu, MemTxAttrs attrs) | |
529 | { | |
530 | CPUClass *cc = CPU_GET_CLASS(cpu); | |
531 | ||
532 | if (cc->asidx_from_attrs) { | |
533 | return cc->asidx_from_attrs(cpu, attrs); | |
534 | } | |
535 | return 0; | |
536 | } | |
00b941e5 AF |
537 | #endif |
538 | ||
dd83b06a AF |
539 | /** |
540 | * cpu_reset: | |
541 | * @cpu: The CPU whose state is to be reset. | |
542 | */ | |
543 | void cpu_reset(CPUState *cpu); | |
544 | ||
2b8c2754 AF |
545 | /** |
546 | * cpu_class_by_name: | |
547 | * @typename: The CPU base type. | |
548 | * @cpu_model: The model string without any parameters. | |
549 | * | |
550 | * Looks up a CPU #ObjectClass matching name @cpu_model. | |
551 | * | |
552 | * Returns: A #CPUClass or %NULL if not matching class is found. | |
553 | */ | |
554 | ObjectClass *cpu_class_by_name(const char *typename, const char *cpu_model); | |
555 | ||
9262685b AF |
556 | /** |
557 | * cpu_generic_init: | |
558 | * @typename: The CPU base type. | |
559 | * @cpu_model: The model string including optional parameters. | |
560 | * | |
561 | * Instantiates a CPU, processes optional parameters and realizes the CPU. | |
562 | * | |
563 | * Returns: A #CPUState or %NULL if an error occurred. | |
564 | */ | |
565 | CPUState *cpu_generic_init(const char *typename, const char *cpu_model); | |
566 | ||
3993c6bd | 567 | /** |
8c2e1b00 | 568 | * cpu_has_work: |
3993c6bd AF |
569 | * @cpu: The vCPU to check. |
570 | * | |
571 | * Checks whether the CPU has work to do. | |
572 | * | |
573 | * Returns: %true if the CPU has work, %false otherwise. | |
574 | */ | |
8c2e1b00 AF |
575 | static inline bool cpu_has_work(CPUState *cpu) |
576 | { | |
577 | CPUClass *cc = CPU_GET_CLASS(cpu); | |
578 | ||
579 | g_assert(cc->has_work); | |
580 | return cc->has_work(cpu); | |
581 | } | |
3993c6bd | 582 | |
60e82579 AF |
583 | /** |
584 | * qemu_cpu_is_self: | |
585 | * @cpu: The vCPU to check against. | |
586 | * | |
587 | * Checks whether the caller is executing on the vCPU thread. | |
588 | * | |
589 | * Returns: %true if called from @cpu's thread, %false otherwise. | |
590 | */ | |
591 | bool qemu_cpu_is_self(CPUState *cpu); | |
592 | ||
c08d7424 AF |
593 | /** |
594 | * qemu_cpu_kick: | |
595 | * @cpu: The vCPU to kick. | |
596 | * | |
597 | * Kicks @cpu's thread. | |
598 | */ | |
599 | void qemu_cpu_kick(CPUState *cpu); | |
600 | ||
2fa45344 AF |
601 | /** |
602 | * cpu_is_stopped: | |
603 | * @cpu: The CPU to check. | |
604 | * | |
605 | * Checks whether the CPU is stopped. | |
606 | * | |
607 | * Returns: %true if run state is not running or if artificially stopped; | |
608 | * %false otherwise. | |
609 | */ | |
610 | bool cpu_is_stopped(CPUState *cpu); | |
611 | ||
f100f0b3 AF |
612 | /** |
613 | * run_on_cpu: | |
614 | * @cpu: The vCPU to run on. | |
615 | * @func: The function to be executed. | |
616 | * @data: Data to pass to the function. | |
617 | * | |
618 | * Schedules the function @func for execution on the vCPU @cpu. | |
619 | */ | |
620 | void run_on_cpu(CPUState *cpu, void (*func)(void *data), void *data); | |
621 | ||
3c02270d CV |
622 | /** |
623 | * async_run_on_cpu: | |
624 | * @cpu: The vCPU to run on. | |
625 | * @func: The function to be executed. | |
626 | * @data: Data to pass to the function. | |
627 | * | |
628 | * Schedules the function @func for execution on the vCPU @cpu asynchronously. | |
629 | */ | |
630 | void async_run_on_cpu(CPUState *cpu, void (*func)(void *data), void *data); | |
631 | ||
38d8f5c8 AF |
632 | /** |
633 | * qemu_get_cpu: | |
634 | * @index: The CPUState@cpu_index value of the CPU to obtain. | |
635 | * | |
636 | * Gets a CPU matching @index. | |
637 | * | |
638 | * Returns: The CPU or %NULL if there is no matching CPU. | |
639 | */ | |
640 | CPUState *qemu_get_cpu(int index); | |
641 | ||
69e5ff06 IM |
642 | /** |
643 | * cpu_exists: | |
644 | * @id: Guest-exposed CPU ID to lookup. | |
645 | * | |
646 | * Search for CPU with specified ID. | |
647 | * | |
648 | * Returns: %true - CPU is found, %false - CPU isn't found. | |
649 | */ | |
650 | bool cpu_exists(int64_t id); | |
651 | ||
2adcc85d JH |
652 | /** |
653 | * cpu_throttle_set: | |
654 | * @new_throttle_pct: Percent of sleep time. Valid range is 1 to 99. | |
655 | * | |
656 | * Throttles all vcpus by forcing them to sleep for the given percentage of | |
657 | * time. A throttle_percentage of 25 corresponds to a 75% duty cycle roughly. | |
658 | * (example: 10ms sleep for every 30ms awake). | |
659 | * | |
660 | * cpu_throttle_set can be called as needed to adjust new_throttle_pct. | |
661 | * Once the throttling starts, it will remain in effect until cpu_throttle_stop | |
662 | * is called. | |
663 | */ | |
664 | void cpu_throttle_set(int new_throttle_pct); | |
665 | ||
666 | /** | |
667 | * cpu_throttle_stop: | |
668 | * | |
669 | * Stops the vcpu throttling started by cpu_throttle_set. | |
670 | */ | |
671 | void cpu_throttle_stop(void); | |
672 | ||
673 | /** | |
674 | * cpu_throttle_active: | |
675 | * | |
676 | * Returns: %true if the vcpus are currently being throttled, %false otherwise. | |
677 | */ | |
678 | bool cpu_throttle_active(void); | |
679 | ||
680 | /** | |
681 | * cpu_throttle_get_percentage: | |
682 | * | |
683 | * Returns the vcpu throttle percentage. See cpu_throttle_set for details. | |
684 | * | |
685 | * Returns: The throttle percentage in range 1 to 99. | |
686 | */ | |
687 | int cpu_throttle_get_percentage(void); | |
688 | ||
c3affe56 AF |
689 | #ifndef CONFIG_USER_ONLY |
690 | ||
691 | typedef void (*CPUInterruptHandler)(CPUState *, int); | |
692 | ||
693 | extern CPUInterruptHandler cpu_interrupt_handler; | |
694 | ||
695 | /** | |
696 | * cpu_interrupt: | |
697 | * @cpu: The CPU to set an interrupt on. | |
698 | * @mask: The interupts to set. | |
699 | * | |
700 | * Invokes the interrupt handler. | |
701 | */ | |
702 | static inline void cpu_interrupt(CPUState *cpu, int mask) | |
703 | { | |
704 | cpu_interrupt_handler(cpu, mask); | |
705 | } | |
706 | ||
707 | #else /* USER_ONLY */ | |
708 | ||
709 | void cpu_interrupt(CPUState *cpu, int mask); | |
710 | ||
711 | #endif /* USER_ONLY */ | |
712 | ||
93e22326 | 713 | #ifdef CONFIG_SOFTMMU |
c658b94f AF |
714 | static inline void cpu_unassigned_access(CPUState *cpu, hwaddr addr, |
715 | bool is_write, bool is_exec, | |
716 | int opaque, unsigned size) | |
717 | { | |
718 | CPUClass *cc = CPU_GET_CLASS(cpu); | |
719 | ||
720 | if (cc->do_unassigned_access) { | |
721 | cc->do_unassigned_access(cpu, addr, is_write, is_exec, opaque, size); | |
722 | } | |
723 | } | |
724 | ||
93e22326 | 725 | static inline void cpu_unaligned_access(CPUState *cpu, vaddr addr, |
b35399bb SS |
726 | MMUAccessType access_type, |
727 | int mmu_idx, uintptr_t retaddr) | |
93e22326 PB |
728 | { |
729 | CPUClass *cc = CPU_GET_CLASS(cpu); | |
730 | ||
b35399bb | 731 | cc->do_unaligned_access(cpu, addr, access_type, mmu_idx, retaddr); |
93e22326 | 732 | } |
c658b94f AF |
733 | #endif |
734 | ||
2991b890 PC |
735 | /** |
736 | * cpu_set_pc: | |
737 | * @cpu: The CPU to set the program counter for. | |
738 | * @addr: Program counter value. | |
739 | * | |
740 | * Sets the program counter for a CPU. | |
741 | */ | |
742 | static inline void cpu_set_pc(CPUState *cpu, vaddr addr) | |
743 | { | |
744 | CPUClass *cc = CPU_GET_CLASS(cpu); | |
745 | ||
746 | cc->set_pc(cpu, addr); | |
747 | } | |
748 | ||
d8ed887b AF |
749 | /** |
750 | * cpu_reset_interrupt: | |
751 | * @cpu: The CPU to clear the interrupt on. | |
752 | * @mask: The interrupt mask to clear. | |
753 | * | |
754 | * Resets interrupts on the vCPU @cpu. | |
755 | */ | |
756 | void cpu_reset_interrupt(CPUState *cpu, int mask); | |
757 | ||
60a3e17a AF |
758 | /** |
759 | * cpu_exit: | |
760 | * @cpu: The CPU to exit. | |
761 | * | |
762 | * Requests the CPU @cpu to exit execution. | |
763 | */ | |
764 | void cpu_exit(CPUState *cpu); | |
765 | ||
2993683b IM |
766 | /** |
767 | * cpu_resume: | |
768 | * @cpu: The CPU to resume. | |
769 | * | |
770 | * Resumes CPU, i.e. puts CPU into runnable state. | |
771 | */ | |
772 | void cpu_resume(CPUState *cpu); | |
dd83b06a | 773 | |
4c055ab5 GZ |
774 | /** |
775 | * cpu_remove: | |
776 | * @cpu: The CPU to remove. | |
777 | * | |
778 | * Requests the CPU to be removed. | |
779 | */ | |
780 | void cpu_remove(CPUState *cpu); | |
781 | ||
2c579042 BR |
782 | /** |
783 | * cpu_remove_sync: | |
784 | * @cpu: The CPU to remove. | |
785 | * | |
786 | * Requests the CPU to be removed and waits till it is removed. | |
787 | */ | |
788 | void cpu_remove_sync(CPUState *cpu); | |
789 | ||
c643bed9 AF |
790 | /** |
791 | * qemu_init_vcpu: | |
792 | * @cpu: The vCPU to initialize. | |
793 | * | |
794 | * Initializes a vCPU. | |
795 | */ | |
796 | void qemu_init_vcpu(CPUState *cpu); | |
797 | ||
3825b28f AF |
798 | #define SSTEP_ENABLE 0x1 /* Enable simulated HW single stepping */ |
799 | #define SSTEP_NOIRQ 0x2 /* Do not use IRQ while single stepping */ | |
800 | #define SSTEP_NOTIMER 0x4 /* Do not Timers while single stepping */ | |
801 | ||
802 | /** | |
803 | * cpu_single_step: | |
804 | * @cpu: CPU to the flags for. | |
805 | * @enabled: Flags to enable. | |
806 | * | |
807 | * Enables or disables single-stepping for @cpu. | |
808 | */ | |
809 | void cpu_single_step(CPUState *cpu, int enabled); | |
810 | ||
b3310ab3 AF |
811 | /* Breakpoint/watchpoint flags */ |
812 | #define BP_MEM_READ 0x01 | |
813 | #define BP_MEM_WRITE 0x02 | |
814 | #define BP_MEM_ACCESS (BP_MEM_READ | BP_MEM_WRITE) | |
815 | #define BP_STOP_BEFORE_ACCESS 0x04 | |
08225676 | 816 | /* 0x08 currently unused */ |
b3310ab3 AF |
817 | #define BP_GDB 0x10 |
818 | #define BP_CPU 0x20 | |
b933066a | 819 | #define BP_ANY (BP_GDB | BP_CPU) |
08225676 PM |
820 | #define BP_WATCHPOINT_HIT_READ 0x40 |
821 | #define BP_WATCHPOINT_HIT_WRITE 0x80 | |
822 | #define BP_WATCHPOINT_HIT (BP_WATCHPOINT_HIT_READ | BP_WATCHPOINT_HIT_WRITE) | |
b3310ab3 AF |
823 | |
824 | int cpu_breakpoint_insert(CPUState *cpu, vaddr pc, int flags, | |
825 | CPUBreakpoint **breakpoint); | |
826 | int cpu_breakpoint_remove(CPUState *cpu, vaddr pc, int flags); | |
827 | void cpu_breakpoint_remove_by_ref(CPUState *cpu, CPUBreakpoint *breakpoint); | |
828 | void cpu_breakpoint_remove_all(CPUState *cpu, int mask); | |
829 | ||
b933066a RH |
830 | /* Return true if PC matches an installed breakpoint. */ |
831 | static inline bool cpu_breakpoint_test(CPUState *cpu, vaddr pc, int mask) | |
832 | { | |
833 | CPUBreakpoint *bp; | |
834 | ||
835 | if (unlikely(!QTAILQ_EMPTY(&cpu->breakpoints))) { | |
836 | QTAILQ_FOREACH(bp, &cpu->breakpoints, entry) { | |
837 | if (bp->pc == pc && (bp->flags & mask)) { | |
838 | return true; | |
839 | } | |
840 | } | |
841 | } | |
842 | return false; | |
843 | } | |
844 | ||
75a34036 AF |
845 | int cpu_watchpoint_insert(CPUState *cpu, vaddr addr, vaddr len, |
846 | int flags, CPUWatchpoint **watchpoint); | |
847 | int cpu_watchpoint_remove(CPUState *cpu, vaddr addr, | |
848 | vaddr len, int flags); | |
849 | void cpu_watchpoint_remove_by_ref(CPUState *cpu, CPUWatchpoint *watchpoint); | |
850 | void cpu_watchpoint_remove_all(CPUState *cpu, int mask); | |
851 | ||
63c91552 PB |
852 | /** |
853 | * cpu_get_address_space: | |
854 | * @cpu: CPU to get address space from | |
855 | * @asidx: index identifying which address space to get | |
856 | * | |
857 | * Return the requested address space of this CPU. @asidx | |
858 | * specifies which address space to read. | |
859 | */ | |
860 | AddressSpace *cpu_get_address_space(CPUState *cpu, int asidx); | |
861 | ||
a47dddd7 AF |
862 | void QEMU_NORETURN cpu_abort(CPUState *cpu, const char *fmt, ...) |
863 | GCC_FMT_ATTR(2, 3); | |
b7bca733 | 864 | void cpu_exec_exit(CPUState *cpu); |
a47dddd7 | 865 | |
1a1562f5 AF |
866 | #ifdef CONFIG_SOFTMMU |
867 | extern const struct VMStateDescription vmstate_cpu_common; | |
868 | #else | |
869 | #define vmstate_cpu_common vmstate_dummy | |
870 | #endif | |
871 | ||
872 | #define VMSTATE_CPU() { \ | |
873 | .name = "parent_obj", \ | |
874 | .size = sizeof(CPUState), \ | |
875 | .vmsd = &vmstate_cpu_common, \ | |
876 | .flags = VMS_STRUCT, \ | |
877 | .offset = 0, \ | |
878 | } | |
879 | ||
dd83b06a | 880 | #endif |