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d4ab3470 DD |
1 | /* |
2 | * Copyright (c) 2014 Intel Corporation. All rights reserved. | |
3 | * | |
4 | * This software is available to you under a choice of one of two | |
5 | * licenses. You may choose to be licensed under the terms of the GNU | |
6 | * General Public License (GPL) Version 2, available from the file | |
7 | * COPYING in the main directory of this source tree, or the | |
8 | * OpenIB.org BSD license below: | |
9 | * | |
10 | * Redistribution and use in source and binary forms, with or | |
11 | * without modification, are permitted provided that the following | |
12 | * conditions are met: | |
13 | * | |
14 | * - Redistributions of source code must retain the above | |
15 | * copyright notice, this list of conditions and the following | |
16 | * disclaimer. | |
17 | * | |
18 | * - Redistributions in binary form must reproduce the above | |
19 | * copyright notice, this list of conditions and the following | |
20 | * disclaimer in the documentation and/or other materials | |
21 | * provided with the distribution. | |
22 | * | |
23 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, | |
24 | * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF | |
25 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND | |
26 | * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS | |
27 | * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN | |
28 | * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN | |
29 | * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE | |
30 | * SOFTWARE. | |
31 | */ | |
32 | ||
33 | #if !defined(OPA_PORT_INFO_H) | |
34 | #define OPA_PORT_INFO_H | |
35 | ||
d4ab3470 DD |
36 | #define OPA_PORT_LINK_MODE_NOP 0 /* No change */ |
37 | #define OPA_PORT_LINK_MODE_OPA 4 /* Port mode is OPA */ | |
38 | ||
39 | #define OPA_PORT_PACKET_FORMAT_NOP 0 /* No change */ | |
40 | #define OPA_PORT_PACKET_FORMAT_8B 1 /* Format 8B */ | |
41 | #define OPA_PORT_PACKET_FORMAT_9B 2 /* Format 9B */ | |
42 | #define OPA_PORT_PACKET_FORMAT_10B 4 /* Format 10B */ | |
43 | #define OPA_PORT_PACKET_FORMAT_16B 8 /* Format 16B */ | |
44 | ||
45 | #define OPA_PORT_LTP_CRC_MODE_NONE 0 /* No change */ | |
46 | #define OPA_PORT_LTP_CRC_MODE_14 1 /* 14-bit LTP CRC mode (optional) */ | |
47 | #define OPA_PORT_LTP_CRC_MODE_16 2 /* 16-bit LTP CRC mode */ | |
48 | #define OPA_PORT_LTP_CRC_MODE_48 4 /* 48-bit LTP CRC mode (optional) */ | |
49 | #define OPA_PORT_LTP_CRC_MODE_PER_LANE 8 /* 12/16-bit per lane LTP CRC mode */ | |
50 | ||
51 | /* Link Down / Neighbor Link Down Reason; indicated as follows: */ | |
52 | #define OPA_LINKDOWN_REASON_NONE 0 /* No specified reason */ | |
53 | #define OPA_LINKDOWN_REASON_RCV_ERROR_0 1 | |
54 | #define OPA_LINKDOWN_REASON_BAD_PKT_LEN 2 | |
55 | #define OPA_LINKDOWN_REASON_PKT_TOO_LONG 3 | |
56 | #define OPA_LINKDOWN_REASON_PKT_TOO_SHORT 4 | |
57 | #define OPA_LINKDOWN_REASON_BAD_SLID 5 | |
58 | #define OPA_LINKDOWN_REASON_BAD_DLID 6 | |
59 | #define OPA_LINKDOWN_REASON_BAD_L2 7 | |
60 | #define OPA_LINKDOWN_REASON_BAD_SC 8 | |
61 | #define OPA_LINKDOWN_REASON_RCV_ERROR_8 9 | |
62 | #define OPA_LINKDOWN_REASON_BAD_MID_TAIL 10 | |
63 | #define OPA_LINKDOWN_REASON_RCV_ERROR_10 11 | |
64 | #define OPA_LINKDOWN_REASON_PREEMPT_ERROR 12 | |
65 | #define OPA_LINKDOWN_REASON_PREEMPT_VL15 13 | |
66 | #define OPA_LINKDOWN_REASON_BAD_VL_MARKER 14 | |
67 | #define OPA_LINKDOWN_REASON_RCV_ERROR_14 15 | |
68 | #define OPA_LINKDOWN_REASON_RCV_ERROR_15 16 | |
69 | #define OPA_LINKDOWN_REASON_BAD_HEAD_DIST 17 | |
70 | #define OPA_LINKDOWN_REASON_BAD_TAIL_DIST 18 | |
71 | #define OPA_LINKDOWN_REASON_BAD_CTRL_DIST 19 | |
72 | #define OPA_LINKDOWN_REASON_BAD_CREDIT_ACK 20 | |
73 | #define OPA_LINKDOWN_REASON_UNSUPPORTED_VL_MARKER 21 | |
74 | #define OPA_LINKDOWN_REASON_BAD_PREEMPT 22 | |
75 | #define OPA_LINKDOWN_REASON_BAD_CONTROL_FLIT 23 | |
76 | #define OPA_LINKDOWN_REASON_EXCEED_MULTICAST_LIMIT 24 | |
77 | #define OPA_LINKDOWN_REASON_RCV_ERROR_24 25 | |
78 | #define OPA_LINKDOWN_REASON_RCV_ERROR_25 26 | |
79 | #define OPA_LINKDOWN_REASON_RCV_ERROR_26 27 | |
80 | #define OPA_LINKDOWN_REASON_RCV_ERROR_27 28 | |
81 | #define OPA_LINKDOWN_REASON_RCV_ERROR_28 29 | |
82 | #define OPA_LINKDOWN_REASON_RCV_ERROR_29 30 | |
83 | #define OPA_LINKDOWN_REASON_RCV_ERROR_30 31 | |
84 | #define OPA_LINKDOWN_REASON_EXCESSIVE_BUFFER_OVERRUN 32 | |
85 | #define OPA_LINKDOWN_REASON_UNKNOWN 33 | |
86 | /* 34 -reserved */ | |
87 | #define OPA_LINKDOWN_REASON_REBOOT 35 | |
88 | #define OPA_LINKDOWN_REASON_NEIGHBOR_UNKNOWN 36 | |
89 | /* 37-38 reserved */ | |
90 | #define OPA_LINKDOWN_REASON_FM_BOUNCE 39 | |
91 | #define OPA_LINKDOWN_REASON_SPEED_POLICY 40 | |
92 | #define OPA_LINKDOWN_REASON_WIDTH_POLICY 41 | |
93 | /* 42-48 reserved */ | |
94 | #define OPA_LINKDOWN_REASON_DISCONNECTED 49 | |
e1bf0d5e | 95 | #define OPA_LINKDOWN_REASON_LOCAL_MEDIA_NOT_INSTALLED 50 |
d4ab3470 DD |
96 | #define OPA_LINKDOWN_REASON_NOT_INSTALLED 51 |
97 | #define OPA_LINKDOWN_REASON_CHASSIS_CONFIG 52 | |
98 | /* 53 reserved */ | |
99 | #define OPA_LINKDOWN_REASON_END_TO_END_NOT_INSTALLED 54 | |
100 | /* 55 reserved */ | |
101 | #define OPA_LINKDOWN_REASON_POWER_POLICY 56 | |
102 | #define OPA_LINKDOWN_REASON_LINKSPEED_POLICY 57 | |
103 | #define OPA_LINKDOWN_REASON_LINKWIDTH_POLICY 58 | |
104 | /* 59 reserved */ | |
105 | #define OPA_LINKDOWN_REASON_SWITCH_MGMT 60 | |
106 | #define OPA_LINKDOWN_REASON_SMA_DISABLED 61 | |
107 | /* 62 reserved */ | |
108 | #define OPA_LINKDOWN_REASON_TRANSIENT 63 | |
109 | /* 64-255 reserved */ | |
110 | ||
111 | /* OPA Link Init reason; indicated as follows: */ | |
112 | /* 3-7; 11-15 reserved; 8-15 cleared on Polling->LinkUp */ | |
113 | #define OPA_LINKINIT_REASON_NOP 0 | |
114 | #define OPA_LINKINIT_REASON_LINKUP (1 << 4) | |
115 | #define OPA_LINKINIT_REASON_FLAPPING (2 << 4) | |
116 | #define OPA_LINKINIT_REASON_CLEAR (8 << 4) | |
117 | #define OPA_LINKINIT_OUTSIDE_POLICY (8 << 4) | |
118 | #define OPA_LINKINIT_QUARANTINED (9 << 4) | |
119 | #define OPA_LINKINIT_INSUFIC_CAPABILITY (10 << 4) | |
120 | ||
121 | #define OPA_LINK_SPEED_NOP 0x0000 /* Reserved (1-5 Gbps) */ | |
122 | #define OPA_LINK_SPEED_12_5G 0x0001 /* 12.5 Gbps */ | |
123 | #define OPA_LINK_SPEED_25G 0x0002 /* 25.78125? Gbps (EDR) */ | |
124 | ||
125 | #define OPA_LINK_WIDTH_1X 0x0001 | |
126 | #define OPA_LINK_WIDTH_2X 0x0002 | |
127 | #define OPA_LINK_WIDTH_3X 0x0004 | |
128 | #define OPA_LINK_WIDTH_4X 0x0008 | |
129 | ||
130 | #define OPA_CAP_MASK3_IsSnoopSupported (1 << 7) | |
131 | #define OPA_CAP_MASK3_IsAsyncSC2VLSupported (1 << 6) | |
132 | #define OPA_CAP_MASK3_IsAddrRangeConfigSupported (1 << 5) | |
133 | #define OPA_CAP_MASK3_IsPassThroughSupported (1 << 4) | |
134 | #define OPA_CAP_MASK3_IsSharedSpaceSupported (1 << 3) | |
135 | /* reserved (1 << 2) */ | |
136 | #define OPA_CAP_MASK3_IsVLMarkerSupported (1 << 1) | |
137 | #define OPA_CAP_MASK3_IsVLrSupported (1 << 0) | |
138 | ||
139 | /** | |
140 | * new MTU values | |
141 | */ | |
142 | enum { | |
143 | OPA_MTU_8192 = 6, | |
144 | OPA_MTU_10240 = 7, | |
145 | }; | |
146 | ||
147 | enum { | |
148 | OPA_PORT_PHYS_CONF_DISCONNECTED = 0, | |
149 | OPA_PORT_PHYS_CONF_STANDARD = 1, | |
150 | OPA_PORT_PHYS_CONF_FIXED = 2, | |
151 | OPA_PORT_PHYS_CONF_VARIABLE = 3, | |
152 | OPA_PORT_PHYS_CONF_SI_PHOTO = 4 | |
153 | }; | |
154 | ||
155 | enum port_info_field_masks { | |
156 | /* vl.cap */ | |
157 | OPA_PI_MASK_VL_CAP = 0x1F, | |
158 | /* port_states.ledenable_offlinereason */ | |
159 | OPA_PI_MASK_OFFLINE_REASON = 0x0F, | |
160 | OPA_PI_MASK_LED_ENABLE = 0x40, | |
161 | /* port_states.unsleepstate_downdefstate */ | |
162 | OPA_PI_MASK_UNSLEEP_STATE = 0xF0, | |
163 | OPA_PI_MASK_DOWNDEF_STATE = 0x0F, | |
164 | /* port_states.portphysstate_portstate */ | |
165 | OPA_PI_MASK_PORT_PHYSICAL_STATE = 0xF0, | |
166 | OPA_PI_MASK_PORT_STATE = 0x0F, | |
167 | /* port_phys_conf */ | |
168 | OPA_PI_MASK_PORT_PHYSICAL_CONF = 0x0F, | |
169 | /* collectivemask_multicastmask */ | |
170 | OPA_PI_MASK_COLLECT_MASK = 0x38, | |
171 | OPA_PI_MASK_MULTICAST_MASK = 0x07, | |
172 | /* mkeyprotect_lmc */ | |
173 | OPA_PI_MASK_MKEY_PROT_BIT = 0xC0, | |
174 | OPA_PI_MASK_LMC = 0x0F, | |
175 | /* smsl */ | |
176 | OPA_PI_MASK_SMSL = 0x1F, | |
177 | /* partenforce_filterraw */ | |
178 | /* Filter Raw In/Out bits 1 and 2 were removed */ | |
179 | OPA_PI_MASK_LINKINIT_REASON = 0xF0, | |
180 | OPA_PI_MASK_PARTITION_ENFORCE_IN = 0x08, | |
181 | OPA_PI_MASK_PARTITION_ENFORCE_OUT = 0x04, | |
182 | /* operational_vls */ | |
183 | OPA_PI_MASK_OPERATIONAL_VL = 0x1F, | |
184 | /* sa_qp */ | |
185 | OPA_PI_MASK_SA_QP = 0x00FFFFFF, | |
186 | /* sm_trap_qp */ | |
187 | OPA_PI_MASK_SM_TRAP_QP = 0x00FFFFFF, | |
188 | /* localphy_overrun_errors */ | |
189 | OPA_PI_MASK_LOCAL_PHY_ERRORS = 0xF0, | |
190 | OPA_PI_MASK_OVERRUN_ERRORS = 0x0F, | |
191 | /* clientrereg_subnettimeout */ | |
192 | OPA_PI_MASK_CLIENT_REREGISTER = 0x80, | |
193 | OPA_PI_MASK_SUBNET_TIMEOUT = 0x1F, | |
194 | /* port_link_mode */ | |
195 | OPA_PI_MASK_PORT_LINK_SUPPORTED = (0x001F << 10), | |
196 | OPA_PI_MASK_PORT_LINK_ENABLED = (0x001F << 5), | |
197 | OPA_PI_MASK_PORT_LINK_ACTIVE = (0x001F << 0), | |
198 | /* port_link_crc_mode */ | |
199 | OPA_PI_MASK_PORT_LINK_CRC_SUPPORTED = 0x0F00, | |
200 | OPA_PI_MASK_PORT_LINK_CRC_ENABLED = 0x00F0, | |
201 | OPA_PI_MASK_PORT_LINK_CRC_ACTIVE = 0x000F, | |
202 | /* port_mode */ | |
203 | OPA_PI_MASK_PORT_MODE_SECURITY_CHECK = 0x0001, | |
204 | OPA_PI_MASK_PORT_MODE_16B_TRAP_QUERY = 0x0002, | |
205 | OPA_PI_MASK_PORT_MODE_PKEY_CONVERT = 0x0004, | |
206 | OPA_PI_MASK_PORT_MODE_SC2SC_MAPPING = 0x0008, | |
207 | OPA_PI_MASK_PORT_MODE_VL_MARKER = 0x0010, | |
208 | OPA_PI_MASK_PORT_PASS_THROUGH = 0x0020, | |
209 | OPA_PI_MASK_PORT_ACTIVE_OPTOMIZE = 0x0040, | |
210 | /* flit_control.interleave */ | |
211 | OPA_PI_MASK_INTERLEAVE_DIST_SUP = (0x0003 << 12), | |
212 | OPA_PI_MASK_INTERLEAVE_DIST_ENABLE = (0x0003 << 10), | |
213 | OPA_PI_MASK_INTERLEAVE_MAX_NEST_TX = (0x001F << 5), | |
214 | OPA_PI_MASK_INTERLEAVE_MAX_NEST_RX = (0x001F << 0), | |
215 | ||
216 | /* port_error_action */ | |
217 | OPA_PI_MASK_EX_BUFFER_OVERRUN = 0x80000000, | |
218 | /* 7 bits reserved */ | |
219 | OPA_PI_MASK_FM_CFG_ERR_EXCEED_MULTICAST_LIMIT = 0x00800000, | |
220 | OPA_PI_MASK_FM_CFG_BAD_CONTROL_FLIT = 0x00400000, | |
221 | OPA_PI_MASK_FM_CFG_BAD_PREEMPT = 0x00200000, | |
222 | OPA_PI_MASK_FM_CFG_UNSUPPORTED_VL_MARKER = 0x00100000, | |
223 | OPA_PI_MASK_FM_CFG_BAD_CRDT_ACK = 0x00080000, | |
224 | OPA_PI_MASK_FM_CFG_BAD_CTRL_DIST = 0x00040000, | |
225 | OPA_PI_MASK_FM_CFG_BAD_TAIL_DIST = 0x00020000, | |
226 | OPA_PI_MASK_FM_CFG_BAD_HEAD_DIST = 0x00010000, | |
227 | /* 2 bits reserved */ | |
228 | OPA_PI_MASK_PORT_RCV_BAD_VL_MARKER = 0x00002000, | |
229 | OPA_PI_MASK_PORT_RCV_PREEMPT_VL15 = 0x00001000, | |
230 | OPA_PI_MASK_PORT_RCV_PREEMPT_ERROR = 0x00000800, | |
231 | /* 1 bit reserved */ | |
232 | OPA_PI_MASK_PORT_RCV_BAD_MidTail = 0x00000200, | |
233 | /* 1 bit reserved */ | |
234 | OPA_PI_MASK_PORT_RCV_BAD_SC = 0x00000080, | |
235 | OPA_PI_MASK_PORT_RCV_BAD_L2 = 0x00000040, | |
236 | OPA_PI_MASK_PORT_RCV_BAD_DLID = 0x00000020, | |
237 | OPA_PI_MASK_PORT_RCV_BAD_SLID = 0x00000010, | |
238 | OPA_PI_MASK_PORT_RCV_PKTLEN_TOOSHORT = 0x00000008, | |
239 | OPA_PI_MASK_PORT_RCV_PKTLEN_TOOLONG = 0x00000004, | |
240 | OPA_PI_MASK_PORT_RCV_BAD_PKTLEN = 0x00000002, | |
241 | OPA_PI_MASK_PORT_RCV_BAD_LT = 0x00000001, | |
242 | ||
243 | /* pass_through.res_drctl */ | |
244 | OPA_PI_MASK_PASS_THROUGH_DR_CONTROL = 0x01, | |
245 | ||
246 | /* buffer_units */ | |
247 | OPA_PI_MASK_BUF_UNIT_VL15_INIT = (0x00000FFF << 11), | |
248 | OPA_PI_MASK_BUF_UNIT_VL15_CREDIT_RATE = (0x0000001F << 6), | |
249 | OPA_PI_MASK_BUF_UNIT_CREDIT_ACK = (0x00000003 << 3), | |
250 | OPA_PI_MASK_BUF_UNIT_BUF_ALLOC = (0x00000003 << 0), | |
251 | ||
252 | /* neigh_mtu.pvlx_to_mtu */ | |
253 | OPA_PI_MASK_NEIGH_MTU_PVL0 = 0xF0, | |
254 | OPA_PI_MASK_NEIGH_MTU_PVL1 = 0x0F, | |
255 | ||
256 | /* neigh_mtu.vlstall_hoq_life */ | |
257 | OPA_PI_MASK_VL_STALL = (0x03 << 5), | |
258 | OPA_PI_MASK_HOQ_LIFE = (0x1F << 0), | |
259 | ||
260 | /* port_neigh_mode */ | |
261 | OPA_PI_MASK_NEIGH_MGMT_ALLOWED = (0x01 << 3), | |
262 | OPA_PI_MASK_NEIGH_FW_AUTH_BYPASS = (0x01 << 2), | |
263 | OPA_PI_MASK_NEIGH_NODE_TYPE = (0x03 << 0), | |
264 | ||
265 | /* resptime_value */ | |
266 | OPA_PI_MASK_RESPONSE_TIME_VALUE = 0x1F, | |
267 | ||
268 | /* mtucap */ | |
269 | OPA_PI_MASK_MTU_CAP = 0x0F, | |
270 | }; | |
271 | ||
d4ab3470 DD |
272 | struct opa_port_states { |
273 | u8 reserved; | |
274 | u8 ledenable_offlinereason; /* 1 res, 1 bit, 6 bits */ | |
275 | u8 reserved2; | |
276 | u8 portphysstate_portstate; /* 4 bits, 4 bits */ | |
277 | }; | |
d4ab3470 DD |
278 | |
279 | struct opa_port_state_info { | |
280 | struct opa_port_states port_states; | |
aadfc3b2 IW |
281 | __be16 link_width_downgrade_tx_active; |
282 | __be16 link_width_downgrade_rx_active; | |
d4ab3470 DD |
283 | }; |
284 | ||
285 | struct opa_port_info { | |
286 | __be32 lid; | |
287 | __be32 flow_control_mask; | |
288 | ||
289 | struct { | |
290 | u8 res; /* was inittype */ | |
291 | u8 cap; /* 3 res, 5 bits */ | |
292 | __be16 high_limit; | |
293 | __be16 preempt_limit; | |
294 | u8 arb_high_cap; | |
295 | u8 arb_low_cap; | |
296 | } vl; | |
297 | ||
298 | struct opa_port_states port_states; | |
299 | u8 port_phys_conf; /* 4 res, 4 bits */ | |
300 | u8 collectivemask_multicastmask; /* 2 res, 3, 3 */ | |
301 | u8 mkeyprotect_lmc; /* 2 bits, 2 res, 4 bits */ | |
302 | u8 smsl; /* 3 res, 5 bits */ | |
303 | ||
304 | u8 partenforce_filterraw; /* bit fields */ | |
305 | u8 operational_vls; /* 3 res, 5 bits */ | |
306 | __be16 pkey_8b; | |
307 | __be16 pkey_10b; | |
308 | __be16 mkey_violations; | |
309 | ||
310 | __be16 pkey_violations; | |
311 | __be16 qkey_violations; | |
312 | __be32 sm_trap_qp; /* 8 bits, 24 bits */ | |
313 | ||
314 | __be32 sa_qp; /* 8 bits, 24 bits */ | |
315 | u8 neigh_port_num; | |
316 | u8 link_down_reason; | |
317 | u8 neigh_link_down_reason; | |
318 | u8 clientrereg_subnettimeout; /* 1 bit, 2 bits, 5 */ | |
319 | ||
320 | struct { | |
321 | __be16 supported; | |
322 | __be16 enabled; | |
323 | __be16 active; | |
324 | } link_speed; | |
325 | struct { | |
326 | __be16 supported; | |
327 | __be16 enabled; | |
328 | __be16 active; | |
329 | } link_width; | |
330 | struct { | |
331 | __be16 supported; | |
332 | __be16 enabled; | |
333 | __be16 tx_active; | |
334 | __be16 rx_active; | |
335 | } link_width_downgrade; | |
336 | __be16 port_link_mode; /* 1 res, 5 bits, 5 bits, 5 bits */ | |
337 | __be16 port_ltp_crc_mode; /* 4 res, 4 bits, 4 bits, 4 bits */ | |
338 | ||
339 | __be16 port_mode; /* 9 res, bit fields */ | |
340 | struct { | |
341 | __be16 supported; | |
342 | __be16 enabled; | |
343 | } port_packet_format; | |
344 | struct { | |
345 | __be16 interleave; /* 2 res, 2,2,5,5 */ | |
346 | struct { | |
347 | __be16 min_initial; | |
348 | __be16 min_tail; | |
349 | u8 large_pkt_limit; | |
350 | u8 small_pkt_limit; | |
351 | u8 max_small_pkt_limit; | |
352 | u8 preemption_limit; | |
353 | } preemption; | |
354 | } flit_control; | |
355 | ||
356 | __be32 reserved4; | |
357 | __be32 port_error_action; /* bit field */ | |
358 | ||
359 | struct { | |
360 | u8 egress_port; | |
361 | u8 res_drctl; /* 7 res, 1 */ | |
362 | } pass_through; | |
363 | __be16 mkey_lease_period; | |
364 | __be32 buffer_units; /* 9 res, 12, 5, 3, 3 */ | |
365 | ||
366 | __be32 reserved5; | |
367 | __be32 sm_lid; | |
368 | ||
369 | __be64 mkey; | |
370 | ||
371 | __be64 subnet_prefix; | |
372 | ||
373 | struct { | |
374 | u8 pvlx_to_mtu[OPA_MAX_VLS/2]; /* 4 bits, 4 bits */ | |
375 | } neigh_mtu; | |
376 | ||
377 | struct { | |
378 | u8 vlstall_hoqlife; /* 3 bits, 5 bits */ | |
379 | } xmit_q[OPA_MAX_VLS]; | |
380 | ||
381 | struct { | |
382 | u8 addr[16]; | |
383 | } ipaddr_ipv6; | |
384 | ||
385 | struct { | |
386 | u8 addr[4]; | |
387 | } ipaddr_ipv4; | |
388 | ||
389 | u32 reserved6; | |
390 | u32 reserved7; | |
391 | u32 reserved8; | |
392 | ||
393 | __be64 neigh_node_guid; | |
394 | ||
395 | __be32 ib_cap_mask; | |
396 | __be16 reserved9; /* was ib_cap_mask2 */ | |
397 | __be16 opa_cap_mask; | |
398 | ||
399 | __be32 reserved10; /* was link_roundtrip_latency */ | |
400 | __be16 overall_buffer_space; | |
401 | __be16 reserved11; /* was max_credit_hint */ | |
402 | ||
403 | __be16 diag_code; | |
404 | struct { | |
405 | u8 buffer; | |
406 | u8 wire; | |
407 | } replay_depth; | |
408 | u8 port_neigh_mode; | |
409 | u8 mtucap; /* 4 res, 4 bits */ | |
410 | ||
411 | u8 resptimevalue; /* 3 res, 5 bits */ | |
412 | u8 local_port_num; | |
413 | u8 reserved12; | |
414 | u8 reserved13; /* was guid_cap */ | |
415 | } __attribute__ ((packed)); | |
416 | ||
417 | #endif /* OPA_PORT_INFO_H */ |