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82fea5a1 VG |
1 | /* |
2 | * ARConnect IP Support (Multi core enabler: Cross core IPI, RTC ...) | |
3 | * | |
4 | * Copyright (C) 2014-15 Synopsys, Inc. (www.synopsys.com) | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or modify | |
7 | * it under the terms of the GNU General Public License version 2 as | |
8 | * published by the Free Software Foundation. | |
9 | */ | |
10 | ||
2d7f5c48 VG |
11 | #ifndef __SOC_ARC_MCIP_H |
12 | #define __SOC_ARC_MCIP_H | |
82fea5a1 | 13 | |
c33a605d | 14 | #include <soc/arc/aux.h> |
82fea5a1 VG |
15 | |
16 | #define ARC_REG_MCIP_BCR 0x0d0 | |
6f0310a1 | 17 | #define ARC_REG_MCIP_IDU_BCR 0x0D5 |
4cac9376 | 18 | #define ARC_REG_GFRC_BUILD 0x0D6 |
82fea5a1 VG |
19 | #define ARC_REG_MCIP_CMD 0x600 |
20 | #define ARC_REG_MCIP_WDATA 0x601 | |
21 | #define ARC_REG_MCIP_READBACK 0x602 | |
22 | ||
23 | struct mcip_cmd { | |
24 | #ifdef CONFIG_CPU_BIG_ENDIAN | |
25 | unsigned int pad:8, param:16, cmd:8; | |
26 | #else | |
27 | unsigned int cmd:8, param:16, pad:8; | |
28 | #endif | |
29 | ||
30 | #define CMD_INTRPT_GENERATE_IRQ 0x01 | |
31 | #define CMD_INTRPT_GENERATE_ACK 0x02 | |
32 | #define CMD_INTRPT_READ_STATUS 0x03 | |
33 | #define CMD_INTRPT_CHECK_SOURCE 0x04 | |
34 | ||
35 | /* Semaphore Commands */ | |
36 | #define CMD_SEMA_CLAIM_AND_READ 0x11 | |
37 | #define CMD_SEMA_RELEASE 0x12 | |
38 | ||
39 | #define CMD_DEBUG_SET_MASK 0x34 | |
5813a960 | 40 | #define CMD_DEBUG_READ_MASK 0x35 |
82fea5a1 | 41 | #define CMD_DEBUG_SET_SELECT 0x36 |
5813a960 | 42 | #define CMD_DEBUG_READ_SELECT 0x37 |
82fea5a1 | 43 | |
d584f0fb VG |
44 | #define CMD_GFRC_READ_LO 0x42 |
45 | #define CMD_GFRC_READ_HI 0x43 | |
4cac9376 EP |
46 | #define CMD_GFRC_SET_CORE 0x47 |
47 | #define CMD_GFRC_READ_CORE 0x48 | |
72d72880 | 48 | |
82fea5a1 VG |
49 | #define CMD_IDU_ENABLE 0x71 |
50 | #define CMD_IDU_DISABLE 0x72 | |
51 | #define CMD_IDU_SET_MODE 0x74 | |
52 | #define CMD_IDU_SET_DEST 0x76 | |
53 | #define CMD_IDU_SET_MASK 0x7C | |
54 | ||
55 | #define IDU_M_TRIG_LEVEL 0x0 | |
56 | #define IDU_M_TRIG_EDGE 0x1 | |
57 | ||
58 | #define IDU_M_DISTRI_RR 0x0 | |
59 | #define IDU_M_DISTRI_DEST 0x2 | |
60 | }; | |
61 | ||
3ce0fefc VG |
62 | struct mcip_bcr { |
63 | #ifdef CONFIG_CPU_BIG_ENDIAN | |
517e7610 VG |
64 | unsigned int pad4:6, pw_dom:1, pad3:1, |
65 | idu:1, pad2:1, num_cores:6, | |
66 | pad:1, gfrc:1, dbg:1, pw:1, | |
67 | msg:1, sem:1, ipi:1, slv:1, | |
3ce0fefc VG |
68 | ver:8; |
69 | #else | |
70 | unsigned int ver:8, | |
517e7610 VG |
71 | slv:1, ipi:1, sem:1, msg:1, |
72 | pw:1, dbg:1, gfrc:1, pad:1, | |
73 | num_cores:6, pad2:1, idu:1, | |
74 | pad3:1, pw_dom:1, pad4:6; | |
3ce0fefc VG |
75 | #endif |
76 | }; | |
77 | ||
6f0310a1 YK |
78 | struct mcip_idu_bcr { |
79 | #ifdef CONFIG_CPU_BIG_ENDIAN | |
80 | unsigned int pad:21, cirqnum:3, ver:8; | |
81 | #else | |
82 | unsigned int ver:8, cirqnum:3, pad:21; | |
83 | #endif | |
84 | }; | |
85 | ||
86 | ||
87 | /* | |
88 | * Build register for IDU contains not an actual number of supported common | |
89 | * interrupts but an exponent of 2 which must be multiplied by 4 to | |
90 | * get a number of supported common interrupts. | |
91 | */ | |
92 | #define mcip_idu_bcr_to_nr_irqs(bcr) (4 * (1 << (bcr).cirqnum)) | |
93 | ||
82fea5a1 VG |
94 | /* |
95 | * MCIP programming model | |
96 | * | |
97 | * - Simple commands write {cmd:8,param:16} to MCIP_CMD aux reg | |
98 | * (param could be irq, common_irq, core_id ...) | |
99 | * - More involved commands setup MCIP_WDATA with cmd specific data | |
100 | * before invoking the simple command | |
101 | */ | |
102 | static inline void __mcip_cmd(unsigned int cmd, unsigned int param) | |
103 | { | |
104 | struct mcip_cmd buf; | |
105 | ||
106 | buf.pad = 0; | |
107 | buf.cmd = cmd; | |
108 | buf.param = param; | |
109 | ||
110 | WRITE_AUX(ARC_REG_MCIP_CMD, buf); | |
111 | } | |
112 | ||
113 | /* | |
114 | * Setup additional data for a cmd | |
115 | * Callers need to lock to ensure atomicity | |
116 | */ | |
117 | static inline void __mcip_cmd_data(unsigned int cmd, unsigned int param, | |
118 | unsigned int data) | |
119 | { | |
120 | write_aux_reg(ARC_REG_MCIP_WDATA, data); | |
121 | ||
122 | __mcip_cmd(cmd, param); | |
123 | } | |
124 | ||
82fea5a1 | 125 | #endif |