[mirror_ubuntu-artful-kernel.git] / include / soc / at91 / at91sam9_sdramc.h

/*
 * arch/arm/mach-at91/include/mach/at91sam9_sdramc.h
 *
 * Copyright (C) 2007 Andrew Victor
 * Copyright (C) 2007 Atmel Corporation.
 *
 * SDRAM Controllers (SDRAMC) - System peripherals registers.
 * Based on AT91SAM9261 datasheet revision D.
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; either version 2 of the License, or
 * (at your option) any later version.
 */

#ifndef AT91SAM9_SDRAMC_H
#define AT91SAM9_SDRAMC_H

/* SDRAM Controller (SDRAMC) registers */
#define AT91_SDRAMC_MR		0x00	/* SDRAM Controller Mode Register */
#define		AT91_SDRAMC_MODE	(0xf << 0)		/* Command Mode */
#define			AT91_SDRAMC_MODE_NORMAL		0
#define			AT91_SDRAMC_MODE_NOP		1
#define			AT91_SDRAMC_MODE_PRECHARGE	2
#define			AT91_SDRAMC_MODE_LMR		3
#define			AT91_SDRAMC_MODE_REFRESH	4
#define			AT91_SDRAMC_MODE_EXT_LMR	5
#define			AT91_SDRAMC_MODE_DEEP		6

#define AT91_SDRAMC_TR		0x04	/* SDRAM Controller Refresh Timer Register */
#define		AT91_SDRAMC_COUNT	(0xfff << 0)		/* Refresh Timer Counter */

#define AT91_SDRAMC_CR		0x08	/* SDRAM Controller Configuration Register */
#define		AT91_SDRAMC_NC		(3 << 0)		/* Number of Column Bits */
#define			AT91_SDRAMC_NC_8	(0 << 0)
#define			AT91_SDRAMC_NC_9	(1 << 0)
#define			AT91_SDRAMC_NC_10	(2 << 0)
#define			AT91_SDRAMC_NC_11	(3 << 0)
#define		AT91_SDRAMC_NR		(3 << 2)		/* Number of Row Bits */
#define			AT91_SDRAMC_NR_11	(0 << 2)
#define			AT91_SDRAMC_NR_12	(1 << 2)
#define			AT91_SDRAMC_NR_13	(2 << 2)
#define		AT91_SDRAMC_NB		(1 << 4)		/* Number of Banks */
#define			AT91_SDRAMC_NB_2	(0 << 4)
#define			AT91_SDRAMC_NB_4	(1 << 4)
#define		AT91_SDRAMC_CAS		(3 << 5)		/* CAS Latency */
#define			AT91_SDRAMC_CAS_1	(1 << 5)
#define			AT91_SDRAMC_CAS_2	(2 << 5)
#define			AT91_SDRAMC_CAS_3	(3 << 5)
#define		AT91_SDRAMC_DBW		(1 << 7)		/* Data Bus Width */
#define			AT91_SDRAMC_DBW_32	(0 << 7)
#define			AT91_SDRAMC_DBW_16	(1 << 7)
#define		AT91_SDRAMC_TWR		(0xf <<  8)		/* Write Recovery Delay */
#define		AT91_SDRAMC_TRC		(0xf << 12)		/* Row Cycle Delay */
#define		AT91_SDRAMC_TRP		(0xf << 16)		/* Row Precharge Delay */
#define		AT91_SDRAMC_TRCD	(0xf << 20)		/* Row to Column Delay */
#define		AT91_SDRAMC_TRAS	(0xf << 24)		/* Active to Precharge Delay */
#define		AT91_SDRAMC_TXSR	(0xf << 28)		/* Exit Self Refresh to Active Delay */

#define AT91_SDRAMC_LPR		0x10	/* SDRAM Controller Low Power Register */
#define		AT91_SDRAMC_LPCB		(3 << 0)	/* Low-power Configurations */
#define			AT91_SDRAMC_LPCB_DISABLE		0
#define			AT91_SDRAMC_LPCB_SELF_REFRESH		1
#define			AT91_SDRAMC_LPCB_POWER_DOWN		2
#define			AT91_SDRAMC_LPCB_DEEP_POWER_DOWN	3
#define		AT91_SDRAMC_PASR		(7 << 4)	/* Partial Array Self Refresh */
#define		AT91_SDRAMC_TCSR		(3 << 8)	/* Temperature Compensated Self Refresh */
#define		AT91_SDRAMC_DS			(3 << 10)	/* Drive Strength */
#define		AT91_SDRAMC_TIMEOUT		(3 << 12)	/* Time to define when Low Power Mode is enabled */
#define			AT91_SDRAMC_TIMEOUT_0_CLK_CYCLES	(0 << 12)
#define			AT91_SDRAMC_TIMEOUT_64_CLK_CYCLES	(1 << 12)
#define			AT91_SDRAMC_TIMEOUT_128_CLK_CYCLES	(2 << 12)

#define AT91_SDRAMC_IER		0x14	/* SDRAM Controller Interrupt Enable Register */
#define AT91_SDRAMC_IDR		0x18	/* SDRAM Controller Interrupt Disable Register */
#define AT91_SDRAMC_IMR		0x1C	/* SDRAM Controller Interrupt Mask Register */
#define AT91_SDRAMC_ISR		0x20	/* SDRAM Controller Interrupt Status Register */
#define		AT91_SDRAMC_RES		(1 << 0)		/* Refresh Error Status */

#define AT91_SDRAMC_MDR		0x24	/* SDRAM Memory Device Register */
#define		AT91_SDRAMC_MD		(3 << 0)		/* Memory Device Type */
#define			AT91_SDRAMC_MD_SDRAM		0
#define			AT91_SDRAMC_MD_LOW_POWER_SDRAM	1

#endif
Commit	Line	Data
eaa595cb	1	/*
a09e64fb	2	* arch/arm/mach-at91/include/mach/at91sam9_sdramc.h
eaa595cb	3	*
3d73e893 AV	4	* Copyright (C) 2007 Andrew Victor
	5	* Copyright (C) 2007 Atmel Corporation.
	6	*
b78eabde	7	* SDRAM Controllers (SDRAMC) - System peripherals registers.
eaa595cb AV	8	* Based on AT91SAM9261 datasheet revision D.
	9	*
	10	* This program is free software; you can redistribute it and/or modify
	11	* it under the terms of the GNU General Public License as published by
	12	* the Free Software Foundation; either version 2 of the License, or
	13	* (at your option) any later version.
	14	*/
	15
b78eabde AV	16	#ifndef AT91SAM9_SDRAMC_H
b78eabde AV	17	#define AT91SAM9_SDRAMC_H
eaa595cb AV	18
eaa595cb AV	19	/* SDRAM Controller (SDRAMC) registers */
7dca3343	20	#define AT91_SDRAMC_MR 0x00 /* SDRAM Controller Mode Register */
eaa595cb AV	21	#define AT91_SDRAMC_MODE (0xf << 0) /* Command Mode */
	22	#define AT91_SDRAMC_MODE_NORMAL 0
	23	#define AT91_SDRAMC_MODE_NOP 1
	24	#define AT91_SDRAMC_MODE_PRECHARGE 2
	25	#define AT91_SDRAMC_MODE_LMR 3
	26	#define AT91_SDRAMC_MODE_REFRESH 4
	27	#define AT91_SDRAMC_MODE_EXT_LMR 5
	28	#define AT91_SDRAMC_MODE_DEEP 6
	29
7dca3343	30	#define AT91_SDRAMC_TR 0x04 /* SDRAM Controller Refresh Timer Register */
eaa595cb AV	31	#define AT91_SDRAMC_COUNT (0xfff << 0) /* Refresh Timer Counter */
eaa595cb AV	32
7dca3343	33	#define AT91_SDRAMC_CR 0x08 /* SDRAM Controller Configuration Register */
eaa595cb AV	34	#define AT91_SDRAMC_NC (3 << 0) /* Number of Column Bits */
	35	#define AT91_SDRAMC_NC_8 (0 << 0)
	36	#define AT91_SDRAMC_NC_9 (1 << 0)
	37	#define AT91_SDRAMC_NC_10 (2 << 0)
	38	#define AT91_SDRAMC_NC_11 (3 << 0)
a14d5273	39	#define AT91_SDRAMC_NR (3 << 2) /* Number of Row Bits */
eaa595cb AV	40	#define AT91_SDRAMC_NR_11 (0 << 2)
	41	#define AT91_SDRAMC_NR_12 (1 << 2)
	42	#define AT91_SDRAMC_NR_13 (2 << 2)
a14d5273	43	#define AT91_SDRAMC_NB (1 << 4) /* Number of Banks */
eaa595cb	44	#define AT91_SDRAMC_NB_2 (0 << 4)
a14d5273 AV	45	#define AT91_SDRAMC_NB_4 (1 << 4)
a14d5273 AV	46	#define AT91_SDRAMC_CAS (3 << 5) /* CAS Latency */
eaa595cb AV	47	#define AT91_SDRAMC_CAS_1 (1 << 5)
	48	#define AT91_SDRAMC_CAS_2 (2 << 5)
	49	#define AT91_SDRAMC_CAS_3 (3 << 5)
	50	#define AT91_SDRAMC_DBW (1 << 7) /* Data Bus Width */
	51	#define AT91_SDRAMC_DBW_32 (0 << 7)
	52	#define AT91_SDRAMC_DBW_16 (1 << 7)
	53	#define AT91_SDRAMC_TWR (0xf << 8) /* Write Recovery Delay */
	54	#define AT91_SDRAMC_TRC (0xf << 12) /* Row Cycle Delay */
	55	#define AT91_SDRAMC_TRP (0xf << 16) /* Row Precharge Delay */
	56	#define AT91_SDRAMC_TRCD (0xf << 20) /* Row to Column Delay */
	57	#define AT91_SDRAMC_TRAS (0xf << 24) /* Active to Precharge Delay */
	58	#define AT91_SDRAMC_TXSR (0xf << 28) /* Exit Self Refresh to Active Delay */
	59
7dca3343	60	#define AT91_SDRAMC_LPR 0x10 /* SDRAM Controller Low Power Register */
eaa595cb AV	61	#define AT91_SDRAMC_LPCB (3 << 0) /* Low-power Configurations */
	62	#define AT91_SDRAMC_LPCB_DISABLE 0
	63	#define AT91_SDRAMC_LPCB_SELF_REFRESH 1
	64	#define AT91_SDRAMC_LPCB_POWER_DOWN 2
	65	#define AT91_SDRAMC_LPCB_DEEP_POWER_DOWN 3
	66	#define AT91_SDRAMC_PASR (7 << 4) /* Partial Array Self Refresh */
	67	#define AT91_SDRAMC_TCSR (3 << 8) /* Temperature Compensated Self Refresh */
b78eabde	68	#define AT91_SDRAMC_DS (3 << 10) /* Drive Strength */
eaa595cb AV	69	#define AT91_SDRAMC_TIMEOUT (3 << 12) /* Time to define when Low Power Mode is enabled */
	70	#define AT91_SDRAMC_TIMEOUT_0_CLK_CYCLES (0 << 12)
	71	#define AT91_SDRAMC_TIMEOUT_64_CLK_CYCLES (1 << 12)
	72	#define AT91_SDRAMC_TIMEOUT_128_CLK_CYCLES (2 << 12)
	73
7dca3343 NF	74	#define AT91_SDRAMC_IER 0x14 /* SDRAM Controller Interrupt Enable Register */
	75	#define AT91_SDRAMC_IDR 0x18 /* SDRAM Controller Interrupt Disable Register */
	76	#define AT91_SDRAMC_IMR 0x1C /* SDRAM Controller Interrupt Mask Register */
	77	#define AT91_SDRAMC_ISR 0x20 /* SDRAM Controller Interrupt Status Register */
eaa595cb AV	78	#define AT91_SDRAMC_RES (1 << 0) /* Refresh Error Status */
eaa595cb AV	79
7dca3343	80	#define AT91_SDRAMC_MDR 0x24 /* SDRAM Memory Device Register */
eaa595cb AV	81	#define AT91_SDRAMC_MD (3 << 0) /* Memory Device Type */
	82	#define AT91_SDRAMC_MD_SDRAM 0
	83	#define AT91_SDRAMC_MD_LOW_POWER_SDRAM 1
	84
eaa595cb	85	#endif