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98658538 1/*
8a56e1ee 2 * Copyright (C) 2006 Freescale Semiconductor, Inc. All rights reserved.
98658538
LY		 3 *
4 * Authors: Shlomi Gridish <gridish@freescale.com>
5 * Li Yang <leoli@freescale.com>
6 *
7 * Description:
8 * QUICC Engine (QE) external definitions and structure.
9 *
10 * This program is free software; you can redistribute it and/or modify it
11 * under the terms of the GNU General Public License as published by the
12 * Free Software Foundation; either version 2 of the License, or (at your
13 * option) any later version.
14 */
15#ifndef _ASM_POWERPC_QE_H
16#define _ASM_POWERPC_QE_H
17#ifdef __KERNEL__
18
1291e49e
ZQ		 19#include <linux/compiler.h>
20#include <linux/genalloc.h>
5e41486c 21#include <linux/spinlock.h>
1b9e8904
AV		 22#include <linux/errno.h>
23#include <linux/err.h>
5093bb96 24#include <asm/cpm.h>
7aa1aa6e 25#include <soc/fsl/qe/immap_qe.h>
1291e49e
ZQ		 26#include <linux/of.h>
27#include <linux/of_address.h>
28#include <linux/types.h>
98658538 29
98ca77af 30#define QE_NUM_OF_SNUM 256 /* There are 256 serial number in QE */
98658538
LY		 31#define QE_NUM_OF_BRGS 16
32#define QE_NUM_OF_PORTS 1024
33
34/* Memory partitions
35*/
36#define MEM_PART_SYSTEM 0
37#define MEM_PART_SECONDARY 1
38#define MEM_PART_MURAM 2
39
7264ec44
TT		 40/* Clocks and BRGs */
41enum qe_clock {
42 QE_CLK_NONE = 0,
43 QE_BRG1, /* Baud Rate Generator 1 */
44 QE_BRG2, /* Baud Rate Generator 2 */
45 QE_BRG3, /* Baud Rate Generator 3 */
46 QE_BRG4, /* Baud Rate Generator 4 */
47 QE_BRG5, /* Baud Rate Generator 5 */
48 QE_BRG6, /* Baud Rate Generator 6 */
49 QE_BRG7, /* Baud Rate Generator 7 */
50 QE_BRG8, /* Baud Rate Generator 8 */
51 QE_BRG9, /* Baud Rate Generator 9 */
52 QE_BRG10, /* Baud Rate Generator 10 */
53 QE_BRG11, /* Baud Rate Generator 11 */
54 QE_BRG12, /* Baud Rate Generator 12 */
55 QE_BRG13, /* Baud Rate Generator 13 */
56 QE_BRG14, /* Baud Rate Generator 14 */
57 QE_BRG15, /* Baud Rate Generator 15 */
58 QE_BRG16, /* Baud Rate Generator 16 */
59 QE_CLK1, /* Clock 1 */
60 QE_CLK2, /* Clock 2 */
61 QE_CLK3, /* Clock 3 */
62 QE_CLK4, /* Clock 4 */
63 QE_CLK5, /* Clock 5 */
64 QE_CLK6, /* Clock 6 */
65 QE_CLK7, /* Clock 7 */
66 QE_CLK8, /* Clock 8 */
67 QE_CLK9, /* Clock 9 */
68 QE_CLK10, /* Clock 10 */
69 QE_CLK11, /* Clock 11 */
70 QE_CLK12, /* Clock 12 */
71 QE_CLK13, /* Clock 13 */
72 QE_CLK14, /* Clock 14 */
73 QE_CLK15, /* Clock 15 */
74 QE_CLK16, /* Clock 16 */
75 QE_CLK17, /* Clock 17 */
76 QE_CLK18, /* Clock 18 */
77 QE_CLK19, /* Clock 19 */
78 QE_CLK20, /* Clock 20 */
79 QE_CLK21, /* Clock 21 */
80 QE_CLK22, /* Clock 22 */
81 QE_CLK23, /* Clock 23 */
82 QE_CLK24, /* Clock 24 */
68f047e3
ZQ		 83 QE_RSYNC_PIN, /* RSYNC from pin */
84 QE_TSYNC_PIN, /* TSYNC from pin */
7264ec44
TT		 85 QE_CLK_DUMMY
86};
87
5e41486c
AV		 88static inline bool qe_clock_is_brg(enum qe_clock clk)
89{
90 return clk >= QE_BRG1 && clk <= QE_BRG16;
91}
92
93extern spinlock_t cmxgcr_lock;
94
98658538 95/* Export QE common operations */
be11d3b3 96#ifdef CONFIG_QUICC_ENGINE
0c7b87b0 97extern void qe_reset(void);
be11d3b3
AV		 98#else
99static inline void qe_reset(void) {}
100#endif
9572653e 101
1291e49e
ZQ		 102int cpm_muram_init(void);
103
104#if defined(CONFIG_CPM) || defined(CONFIG_QUICC_ENGINE)
105unsigned long cpm_muram_alloc(unsigned long size, unsigned long align);
106int cpm_muram_free(unsigned long offset);
107unsigned long cpm_muram_alloc_fixed(unsigned long offset, unsigned long size);
1291e49e
ZQ		 108void __iomem *cpm_muram_addr(unsigned long offset);
109unsigned long cpm_muram_offset(void __iomem *addr);
110dma_addr_t cpm_muram_dma(void __iomem *addr);
111#else
112static inline unsigned long cpm_muram_alloc(unsigned long size,
113 unsigned long align)
114{
115 return -ENOSYS;
116}
117
118static inline int cpm_muram_free(unsigned long offset)
119{
120 return -ENOSYS;
121}
122
123static inline unsigned long cpm_muram_alloc_fixed(unsigned long offset,
124 unsigned long size)
125{
126 return -ENOSYS;
127}
128
129static inline void __iomem *cpm_muram_addr(unsigned long offset)
130{
131 return NULL;
132}
133
134static inline unsigned long cpm_muram_offset(void __iomem *addr)
135{
136 return -ENOSYS;
137}
138
139static inline dma_addr_t cpm_muram_dma(void __iomem *addr)
140{
141 return 0;
142}
143#endif /* defined(CONFIG_CPM) || defined(CONFIG_QUICC_ENGINE) */
144
9572653e
AV		 145/* QE PIO */
146#define QE_PIO_PINS 32
147
148struct qe_pio_regs {
149 __be32 cpodr; /* Open drain register */
150 __be32 cpdata; /* Data register */
151 __be32 cpdir1; /* Direction register */
152 __be32 cpdir2; /* Direction register */
153 __be32 cppar1; /* Pin assignment register */
154 __be32 cppar2; /* Pin assignment register */
155#ifdef CONFIG_PPC_85xx
156 u8 pad[8];
157#endif
158};
159
32def337
AV		 160#define QE_PIO_DIR_IN 2
161#define QE_PIO_DIR_OUT 1
9572653e
AV		 162extern void __par_io_config_pin(struct qe_pio_regs __iomem *par_io, u8 pin,
163 int dir, int open_drain, int assignment,
164 int has_irq);
be11d3b3
AV		 165#ifdef CONFIG_QUICC_ENGINE
166extern int par_io_init(struct device_node *np);
167extern int par_io_of_config(struct device_node *np);
364f8ffc
AV		 168extern int par_io_config_pin(u8 port, u8 pin, int dir, int open_drain,
169 int assignment, int has_irq);
170extern int par_io_data_set(u8 port, u8 pin, u8 val);
be11d3b3
AV		 171#else
172static inline int par_io_init(struct device_node *np) { return -ENOSYS; }
173static inline int par_io_of_config(struct device_node *np) { return -ENOSYS; }
174static inline int par_io_config_pin(u8 port, u8 pin, int dir, int open_drain,
175 int assignment, int has_irq) { return -ENOSYS; }
176static inline int par_io_data_set(u8 port, u8 pin, u8 val) { return -ENOSYS; }
177#endif /* CONFIG_QUICC_ENGINE */
98658538 178
1b9e8904
AV		 179/*
180 * Pin multiplexing functions.
181 */
182struct qe_pin;
183#ifdef CONFIG_QE_GPIO
184extern struct qe_pin *qe_pin_request(struct device_node *np, int index);
185extern void qe_pin_free(struct qe_pin *qe_pin);
186extern void qe_pin_set_gpio(struct qe_pin *qe_pin);
187extern void qe_pin_set_dedicated(struct qe_pin *pin);
188#else
189static inline struct qe_pin *qe_pin_request(struct device_node *np, int index)
190{
191 return ERR_PTR(-ENOSYS);
192}
193static inline void qe_pin_free(struct qe_pin *qe_pin) {}
194static inline void qe_pin_set_gpio(struct qe_pin *qe_pin) {}
195static inline void qe_pin_set_dedicated(struct qe_pin *pin) {}
196#endif /* CONFIG_QE_GPIO */
197
58c12bdc 198#ifdef CONFIG_QUICC_ENGINE
98658538 199int qe_issue_cmd(u32 cmd, u32 device, u8 mcn_protocol, u32 cmd_input);
58c12bdc
AV		 200#else
201static inline int qe_issue_cmd(u32 cmd, u32 device, u8 mcn_protocol,
202 u32 cmd_input)
203{
204 return -ENOSYS;
205}
206#endif /* CONFIG_QUICC_ENGINE */
207
208/* QE internal API */
174b0da2 209enum qe_clock qe_clock_source(const char *source);
7f0a6fc8 210unsigned int qe_get_brg_clk(void);
7264ec44 211int qe_setbrg(enum qe_clock brg, unsigned int rate, unsigned int multiplier);
98658538
LY		 212int qe_get_snum(void);
213void qe_put_snum(u8 snum);
06c44350 214unsigned int qe_get_num_of_risc(void);
98ca77af 215unsigned int qe_get_num_of_snums(void);
46d22934
AV		 216
217static inline int qe_alive_during_sleep(void)
218{
219 /*
220 * MPC8568E reference manual says:
221 *
222 * "...power down sequence waits for all I/O interfaces to become idle.
223 * In some applications this may happen eventually without actively
224 * shutting down interfaces, but most likely, software will have to
225 * take steps to shut down the eTSEC, QUICC Engine Block, and PCI
226 * interfaces before issuing the command (either the write to the core
227 * MSR[WE] as described above or writing to POWMGTCSR) to put the
228 * device into sleep state."
229 *
230 * MPC8569E reference manual has a similar paragraph.
231 */
232#ifdef CONFIG_PPC_85xx
233 return 0;
234#else
235 return 1;
236#endif
237}
06c44350 238
5093bb96
AV		 239/* we actually use cpm_muram implementation, define this for convenience */
240#define qe_muram_init cpm_muram_init
241#define qe_muram_alloc cpm_muram_alloc
242#define qe_muram_alloc_fixed cpm_muram_alloc_fixed
243#define qe_muram_free cpm_muram_free
244#define qe_muram_addr cpm_muram_addr
245#define qe_muram_offset cpm_muram_offset
8b8642af 246#define qe_muram_dma cpm_muram_dma
98658538 247
bb8b2062
ZQ		 248#define qe_setbits32(_addr, _v) iowrite32be(ioread32be(_addr) | (_v), (_addr))
249#define qe_clrbits32(_addr, _v) iowrite32be(ioread32be(_addr) & ~(_v), (_addr))
250
251#define qe_setbits16(_addr, _v) iowrite16be(ioread16be(_addr) | (_v), (_addr))
252#define qe_clrbits16(_addr, _v) iowrite16be(ioread16be(_addr) & ~(_v), (_addr))
253
254#define qe_setbits8(_addr, _v) iowrite8(ioread8(_addr) | (_v), (_addr))
255#define qe_clrbits8(_addr, _v) iowrite8(ioread8(_addr) & ~(_v), (_addr))
256
257#define qe_clrsetbits32(addr, clear, set) \
258 iowrite32be((ioread32be(addr) & ~(clear)) | (set), (addr))
259#define qe_clrsetbits16(addr, clear, set) \
260 iowrite16be((ioread16be(addr) & ~(clear)) | (set), (addr))
261#define qe_clrsetbits8(addr, clear, set) \
262 iowrite8((ioread8(addr) & ~(clear)) | (set), (addr))
263
bc556ba9
TT		 264/* Structure that defines QE firmware binary files.
265 *
395cf969 266 * See Documentation/powerpc/qe_firmware.txt for a description of these
bc556ba9
TT		 267 * fields.
268 */
269struct qe_firmware {
270 struct qe_header {
271 __be32 length; /* Length of the entire structure, in bytes */
272 u8 magic[3]; /* Set to { 'Q', 'E', 'F' } */
273 u8 version; /* Version of this layout. First ver is '1' */
274 } header;
275 u8 id[62]; /* Null-terminated identifier string */
276 u8 split; /* 0 = shared I-RAM, 1 = split I-RAM */
277 u8 count; /* Number of microcode[] structures */
278 struct {
279 __be16 model; /* The SOC model */
280 u8 major; /* The SOC revision major */
281 u8 minor; /* The SOC revision minor */
282 } __attribute__ ((packed)) soc;
283 u8 padding[4]; /* Reserved, for alignment */
284 __be64 extended_modes; /* Extended modes */
285 __be32 vtraps[8]; /* Virtual trap addresses */
286 u8 reserved[4]; /* Reserved, for future expansion */
287 struct qe_microcode {
288 u8 id[32]; /* Null-terminated identifier */
289 __be32 traps[16]; /* Trap addresses, 0 == ignore */
290 __be32 eccr; /* The value for the ECCR register */
291 __be32 iram_offset; /* Offset into I-RAM for the code */
292 __be32 count; /* Number of 32-bit words of the code */
293 __be32 code_offset; /* Offset of the actual microcode */
294 u8 major; /* The microcode version major */
295 u8 minor; /* The microcode version minor */
296 u8 revision; /* The microcode version revision */
297 u8 padding; /* Reserved, for alignment */
298 u8 reserved[4]; /* Reserved, for future expansion */
299 } __attribute__ ((packed)) microcode[1];
300 /* All microcode binaries should be located here */
301 /* CRC32 should be located here, after the microcode binaries */
302} __attribute__ ((packed));
303
304struct qe_firmware_info {
305 char id[64]; /* Firmware name */
306 u32 vtraps[8]; /* Virtual trap addresses */
307 u64 extended_modes; /* Extended modes */
308};
309
b79ddf2c 310#ifdef CONFIG_QUICC_ENGINE
bc556ba9
TT		 311/* Upload a firmware to the QE */
312int qe_upload_firmware(const struct qe_firmware *firmware);
b79ddf2c
AV		 313#else
314static inline int qe_upload_firmware(const struct qe_firmware *firmware)
315{
316 return -ENOSYS;
317}
318#endif /* CONFIG_QUICC_ENGINE */
bc556ba9
TT		 319
320/* Obtain information on the uploaded firmware */
321struct qe_firmware_info *qe_get_firmware_info(void);
322
5e41486c
AV		 323/* QE USB */
324int qe_usb_clock_set(enum qe_clock clk, int rate);
325
98658538
LY		 326/* Buffer descriptors */
327struct qe_bd {
6b0b594b
TT		 328 __be16 status;
329 __be16 length;
330 __be32 buf;
98658538
LY		 331} __attribute__ ((packed));
332
333#define BD_STATUS_MASK 0xffff0000
334#define BD_LENGTH_MASK 0x0000ffff
335
336/* Alignment */
337#define QE_INTR_TABLE_ALIGN 16 /* ??? */
338#define QE_ALIGNMENT_OF_BD 8
339#define QE_ALIGNMENT_OF_PRAM 64
340
341/* RISC allocation */
06c44350
HW		 342#define QE_RISC_ALLOCATION_RISC1 0x1 /* RISC 1 */
343#define QE_RISC_ALLOCATION_RISC2 0x2 /* RISC 2 */
344#define QE_RISC_ALLOCATION_RISC3 0x4 /* RISC 3 */
345#define QE_RISC_ALLOCATION_RISC4 0x8 /* RISC 4 */
346#define QE_RISC_ALLOCATION_RISC1_AND_RISC2 (QE_RISC_ALLOCATION_RISC1 | \
347 QE_RISC_ALLOCATION_RISC2)
348#define QE_RISC_ALLOCATION_FOUR_RISCS (QE_RISC_ALLOCATION_RISC1 | \
349 QE_RISC_ALLOCATION_RISC2 | \
350 QE_RISC_ALLOCATION_RISC3 | \
351 QE_RISC_ALLOCATION_RISC4)
98658538
LY		 352
353/* QE extended filtering Table Lookup Key Size */
354enum qe_fltr_tbl_lookup_key_size {
355 QE_FLTR_TABLE_LOOKUP_KEY_SIZE_8_BYTES
356 = 0x3f, /* LookupKey parsed by the Generate LookupKey
357 CMD is truncated to 8 bytes */
358 QE_FLTR_TABLE_LOOKUP_KEY_SIZE_16_BYTES
359 = 0x5f, /* LookupKey parsed by the Generate LookupKey
360 CMD is truncated to 16 bytes */
361};
362
363/* QE FLTR extended filtering Largest External Table Lookup Key Size */
364enum qe_fltr_largest_external_tbl_lookup_key_size {
365 QE_FLTR_LARGEST_EXTERNAL_TABLE_LOOKUP_KEY_SIZE_NONE
366 = 0x0,/* not used */
367 QE_FLTR_LARGEST_EXTERNAL_TABLE_LOOKUP_KEY_SIZE_8_BYTES
368 = QE_FLTR_TABLE_LOOKUP_KEY_SIZE_8_BYTES, /* 8 bytes */
369 QE_FLTR_LARGEST_EXTERNAL_TABLE_LOOKUP_KEY_SIZE_16_BYTES
370 = QE_FLTR_TABLE_LOOKUP_KEY_SIZE_16_BYTES, /* 16 bytes */
371};
372
373/* structure representing QE parameter RAM */
374struct qe_timer_tables {
375 u16 tm_base; /* QE timer table base adr */
376 u16 tm_ptr; /* QE timer table pointer */
377 u16 r_tmr; /* QE timer mode register */
378 u16 r_tmv; /* QE timer valid register */
379 u32 tm_cmd; /* QE timer cmd register */
380 u32 tm_cnt; /* QE timer internal cnt */
381} __attribute__ ((packed));
382
383#define QE_FLTR_TAD_SIZE 8
384
385/* QE extended filtering Termination Action Descriptor (TAD) */
386struct qe_fltr_tad {
387 u8 serialized[QE_FLTR_TAD_SIZE];
388} __attribute__ ((packed));
389
390/* Communication Direction */
391enum comm_dir {
392 COMM_DIR_NONE = 0,
393 COMM_DIR_RX = 1,
394 COMM_DIR_TX = 2,
395 COMM_DIR_RX_AND_TX = 3
396};
397
98658538
LY		 398/* QE CMXUCR Registers.
399 * There are two UCCs represented in each of the four CMXUCR registers.
400 * These values are for the UCC in the LSBs
401 */
402#define QE_CMXUCR_MII_ENET_MNG 0x00007000
403#define QE_CMXUCR_MII_ENET_MNG_SHIFT 12
404#define QE_CMXUCR_GRANT 0x00008000
405#define QE_CMXUCR_TSA 0x00004000
406#define QE_CMXUCR_BKPT 0x00000100
407#define QE_CMXUCR_TX_CLK_SRC_MASK 0x0000000F
408
409/* QE CMXGCR Registers.
410*/
411#define QE_CMXGCR_MII_ENET_MNG 0x00007000
412#define QE_CMXGCR_MII_ENET_MNG_SHIFT 12
413#define QE_CMXGCR_USBCS 0x0000000f
5e41486c
AV		 414#define QE_CMXGCR_USBCS_CLK3 0x1
415#define QE_CMXGCR_USBCS_CLK5 0x2
416#define QE_CMXGCR_USBCS_CLK7 0x3
417#define QE_CMXGCR_USBCS_CLK9 0x4
418#define QE_CMXGCR_USBCS_CLK13 0x5
419#define QE_CMXGCR_USBCS_CLK17 0x6
420#define QE_CMXGCR_USBCS_CLK19 0x7
421#define QE_CMXGCR_USBCS_CLK21 0x8
422#define QE_CMXGCR_USBCS_BRG9 0x9
423#define QE_CMXGCR_USBCS_BRG10 0xa
98658538
LY		 424
425/* QE CECR Commands.
426*/
427#define QE_CR_FLG 0x00010000
428#define QE_RESET 0x80000000
429#define QE_INIT_TX_RX 0x00000000
430#define QE_INIT_RX 0x00000001
431#define QE_INIT_TX 0x00000002
432#define QE_ENTER_HUNT_MODE 0x00000003
433#define QE_STOP_TX 0x00000004
434#define QE_GRACEFUL_STOP_TX 0x00000005
435#define QE_RESTART_TX 0x00000006
436#define QE_CLOSE_RX_BD 0x00000007
437#define QE_SWITCH_COMMAND 0x00000007
438#define QE_SET_GROUP_ADDRESS 0x00000008
439#define QE_START_IDMA 0x00000009
440#define QE_MCC_STOP_RX 0x00000009
441#define QE_ATM_TRANSMIT 0x0000000a
442#define QE_HPAC_CLEAR_ALL 0x0000000b
443#define QE_GRACEFUL_STOP_RX 0x0000001a
444#define QE_RESTART_RX 0x0000001b
445#define QE_HPAC_SET_PRIORITY 0x0000010b
446#define QE_HPAC_STOP_TX 0x0000020b
447#define QE_HPAC_STOP_RX 0x0000030b
448#define QE_HPAC_GRACEFUL_STOP_TX 0x0000040b
449#define QE_HPAC_GRACEFUL_STOP_RX 0x0000050b
450#define QE_HPAC_START_TX 0x0000060b
451#define QE_HPAC_START_RX 0x0000070b
452#define QE_USB_STOP_TX 0x0000000a
5e41486c 453#define QE_USB_RESTART_TX 0x0000000c
98658538
LY		 454#define QE_QMC_STOP_TX 0x0000000c
455#define QE_QMC_STOP_RX 0x0000000d
456#define QE_SS7_SU_FIL_RESET 0x0000000e
457/* jonathbr added from here down for 83xx */
458#define QE_RESET_BCS 0x0000000a
459#define QE_MCC_INIT_TX_RX_16 0x00000003
460#define QE_MCC_STOP_TX 0x00000004
461#define QE_MCC_INIT_TX_1 0x00000005
462#define QE_MCC_INIT_RX_1 0x00000006
463#define QE_MCC_RESET 0x00000007
464#define QE_SET_TIMER 0x00000008
465#define QE_RANDOM_NUMBER 0x0000000c
466#define QE_ATM_MULTI_THREAD_INIT 0x00000011
467#define QE_ASSIGN_PAGE 0x00000012
468#define QE_ADD_REMOVE_HASH_ENTRY 0x00000013
469#define QE_START_FLOW_CONTROL 0x00000014
470#define QE_STOP_FLOW_CONTROL 0x00000015
471#define QE_ASSIGN_PAGE_TO_DEVICE 0x00000016
472
473#define QE_ASSIGN_RISC 0x00000010
474#define QE_CR_MCN_NORMAL_SHIFT 6
475#define QE_CR_MCN_USB_SHIFT 4
476#define QE_CR_MCN_RISC_ASSIGN_SHIFT 8
477#define QE_CR_SNUM_SHIFT 17
478
479/* QE CECR Sub Block - sub block of QE command.
480*/
481#define QE_CR_SUBBLOCK_INVALID 0x00000000
482#define QE_CR_SUBBLOCK_USB 0x03200000
483#define QE_CR_SUBBLOCK_UCCFAST1 0x02000000
484#define QE_CR_SUBBLOCK_UCCFAST2 0x02200000
485#define QE_CR_SUBBLOCK_UCCFAST3 0x02400000
486#define QE_CR_SUBBLOCK_UCCFAST4 0x02600000
487#define QE_CR_SUBBLOCK_UCCFAST5 0x02800000
488#define QE_CR_SUBBLOCK_UCCFAST6 0x02a00000
489#define QE_CR_SUBBLOCK_UCCFAST7 0x02c00000
490#define QE_CR_SUBBLOCK_UCCFAST8 0x02e00000
491#define QE_CR_SUBBLOCK_UCCSLOW1 0x00000000
492#define QE_CR_SUBBLOCK_UCCSLOW2 0x00200000
493#define QE_CR_SUBBLOCK_UCCSLOW3 0x00400000
494#define QE_CR_SUBBLOCK_UCCSLOW4 0x00600000
495#define QE_CR_SUBBLOCK_UCCSLOW5 0x00800000
496#define QE_CR_SUBBLOCK_UCCSLOW6 0x00a00000
497#define QE_CR_SUBBLOCK_UCCSLOW7 0x00c00000
498#define QE_CR_SUBBLOCK_UCCSLOW8 0x00e00000
499#define QE_CR_SUBBLOCK_MCC1 0x03800000
500#define QE_CR_SUBBLOCK_MCC2 0x03a00000
501#define QE_CR_SUBBLOCK_MCC3 0x03000000
502#define QE_CR_SUBBLOCK_IDMA1 0x02800000
503#define QE_CR_SUBBLOCK_IDMA2 0x02a00000
504#define QE_CR_SUBBLOCK_IDMA3 0x02c00000
505#define QE_CR_SUBBLOCK_IDMA4 0x02e00000
506#define QE_CR_SUBBLOCK_HPAC 0x01e00000
507#define QE_CR_SUBBLOCK_SPI1 0x01400000
508#define QE_CR_SUBBLOCK_SPI2 0x01600000
509#define QE_CR_SUBBLOCK_RAND 0x01c00000
510#define QE_CR_SUBBLOCK_TIMER 0x01e00000
511#define QE_CR_SUBBLOCK_GENERAL 0x03c00000
512
513/* QE CECR Protocol - For non-MCC, specifies mode for QE CECR command */
514#define QE_CR_PROTOCOL_UNSPECIFIED 0x00 /* For all other protocols */
515#define QE_CR_PROTOCOL_HDLC_TRANSPARENT 0x00
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TT		 516#define QE_CR_PROTOCOL_QMC 0x02
517#define QE_CR_PROTOCOL_UART 0x04
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LY		 518#define QE_CR_PROTOCOL_ATM_POS 0x0A
519#define QE_CR_PROTOCOL_ETHERNET 0x0C
520#define QE_CR_PROTOCOL_L2_SWITCH 0x0D
521
98658538
LY		 522/* BRG configuration register */
523#define QE_BRGC_ENABLE 0x00010000
524#define QE_BRGC_DIVISOR_SHIFT 1
525#define QE_BRGC_DIVISOR_MAX 0xFFF
526#define QE_BRGC_DIV16 1
527
528/* QE Timers registers */
529#define QE_GTCFR1_PCAS 0x80
530#define QE_GTCFR1_STP2 0x20
531#define QE_GTCFR1_RST2 0x10
532#define QE_GTCFR1_GM2 0x08
533#define QE_GTCFR1_GM1 0x04
534#define QE_GTCFR1_STP1 0x02
535#define QE_GTCFR1_RST1 0x01
536
537/* SDMA registers */
538#define QE_SDSR_BER1 0x02000000
539#define QE_SDSR_BER2 0x01000000
540
541#define QE_SDMR_GLB_1_MSK 0x80000000
542#define QE_SDMR_ADR_SEL 0x20000000
543#define QE_SDMR_BER1_MSK 0x02000000
544#define QE_SDMR_BER2_MSK 0x01000000
545#define QE_SDMR_EB1_MSK 0x00800000
546#define QE_SDMR_ER1_MSK 0x00080000
547#define QE_SDMR_ER2_MSK 0x00040000
548#define QE_SDMR_CEN_MASK 0x0000E000
549#define QE_SDMR_SBER_1 0x00000200
550#define QE_SDMR_SBER_2 0x00000200
551#define QE_SDMR_EB1_PR_MASK 0x000000C0
552#define QE_SDMR_ER1_PR 0x00000008
553
554#define QE_SDMR_CEN_SHIFT 13
555#define QE_SDMR_EB1_PR_SHIFT 6
556
557#define QE_SDTM_MSNUM_SHIFT 24
558
559#define QE_SDEBCR_BA_MASK 0x01FFFFFF
560
bc556ba9
TT		 561/* Communication Processor */
562#define QE_CP_CERCR_MEE 0x8000 /* Multi-user RAM ECC enable */
563#define QE_CP_CERCR_IEE 0x4000 /* Instruction RAM ECC enable */
564#define QE_CP_CERCR_CIR 0x0800 /* Common instruction RAM */
565
566/* I-RAM */
567#define QE_IRAM_IADD_AIE 0x80000000 /* Auto Increment Enable */
568#define QE_IRAM_IADD_BADDR 0x00080000 /* Base Address */
e65650e6 569#define QE_IRAM_READY 0x80000000 /* Ready */
bc556ba9 570
98658538
LY		 571/* UPC */
572#define UPGCR_PROTOCOL 0x80000000 /* protocol ul2 or pl2 */
573#define UPGCR_TMS 0x40000000 /* Transmit master/slave mode */
574#define UPGCR_RMS 0x20000000 /* Receive master/slave mode */
575#define UPGCR_ADDR 0x10000000 /* Master MPHY Addr multiplexing */
576#define UPGCR_DIAG 0x01000000 /* Diagnostic mode */
577
6b0b594b 578/* UCC GUEMR register */
98658538 579#define UCC_GUEMR_MODE_MASK_RX 0x02
98658538 580#define UCC_GUEMR_MODE_FAST_RX 0x02
98658538 581#define UCC_GUEMR_MODE_SLOW_RX 0x00
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TT		 582#define UCC_GUEMR_MODE_MASK_TX 0x01
583#define UCC_GUEMR_MODE_FAST_TX 0x01
98658538 584#define UCC_GUEMR_MODE_SLOW_TX 0x00
6b0b594b 585#define UCC_GUEMR_MODE_MASK (UCC_GUEMR_MODE_MASK_RX | UCC_GUEMR_MODE_MASK_TX)
98658538
LY		 586#define UCC_GUEMR_SET_RESERVED3 0x10 /* Bit 3 in the guemr is reserved but
587 must be set 1 */
588
589/* structure representing UCC SLOW parameter RAM */
590struct ucc_slow_pram {
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TT		 591 __be16 rbase; /* RX BD base address */
592 __be16 tbase; /* TX BD base address */
593 u8 rbmr; /* RX bus mode register (same as CPM's RFCR) */
594 u8 tbmr; /* TX bus mode register (same as CPM's TFCR) */
595 __be16 mrblr; /* Rx buffer length */
596 __be32 rstate; /* Rx internal state */
597 __be32 rptr; /* Rx internal data pointer */
598 __be16 rbptr; /* rb BD Pointer */
599 __be16 rcount; /* Rx internal byte count */
600 __be32 rtemp; /* Rx temp */
601 __be32 tstate; /* Tx internal state */
602 __be32 tptr; /* Tx internal data pointer */
603 __be16 tbptr; /* Tx BD pointer */
604 __be16 tcount; /* Tx byte count */
605 __be32 ttemp; /* Tx temp */
606 __be32 rcrc; /* temp receive CRC */
607 __be32 tcrc; /* temp transmit CRC */
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LY		 608} __attribute__ ((packed));
609
610/* General UCC SLOW Mode Register (GUMRH & GUMRL) */
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TT		 611#define UCC_SLOW_GUMR_H_SAM_QMC 0x00000000
612#define UCC_SLOW_GUMR_H_SAM_SATM 0x00008000
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LY		 613#define UCC_SLOW_GUMR_H_REVD 0x00002000
614#define UCC_SLOW_GUMR_H_TRX 0x00001000
615#define UCC_SLOW_GUMR_H_TTX 0x00000800
616#define UCC_SLOW_GUMR_H_CDP 0x00000400
617#define UCC_SLOW_GUMR_H_CTSP 0x00000200
618#define UCC_SLOW_GUMR_H_CDS 0x00000100
619#define UCC_SLOW_GUMR_H_CTSS 0x00000080
620#define UCC_SLOW_GUMR_H_TFL 0x00000040
621#define UCC_SLOW_GUMR_H_RFW 0x00000020
622#define UCC_SLOW_GUMR_H_TXSY 0x00000010
623#define UCC_SLOW_GUMR_H_4SYNC 0x00000004
624#define UCC_SLOW_GUMR_H_8SYNC 0x00000008
625#define UCC_SLOW_GUMR_H_16SYNC 0x0000000c
626#define UCC_SLOW_GUMR_H_RTSM 0x00000002
627#define UCC_SLOW_GUMR_H_RSYN 0x00000001
628
629#define UCC_SLOW_GUMR_L_TCI 0x10000000
630#define UCC_SLOW_GUMR_L_RINV 0x02000000
631#define UCC_SLOW_GUMR_L_TINV 0x01000000
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TT		 632#define UCC_SLOW_GUMR_L_TEND 0x00040000
633#define UCC_SLOW_GUMR_L_TDCR_MASK 0x00030000
634#define UCC_SLOW_GUMR_L_TDCR_32 0x00030000
635#define UCC_SLOW_GUMR_L_TDCR_16 0x00020000
636#define UCC_SLOW_GUMR_L_TDCR_8 0x00010000
637#define UCC_SLOW_GUMR_L_TDCR_1 0x00000000
638#define UCC_SLOW_GUMR_L_RDCR_MASK 0x0000c000
639#define UCC_SLOW_GUMR_L_RDCR_32 0x0000c000
640#define UCC_SLOW_GUMR_L_RDCR_16 0x00008000
641#define UCC_SLOW_GUMR_L_RDCR_8 0x00004000
642#define UCC_SLOW_GUMR_L_RDCR_1 0x00000000
643#define UCC_SLOW_GUMR_L_RENC_NRZI 0x00000800
644#define UCC_SLOW_GUMR_L_RENC_NRZ 0x00000000
645#define UCC_SLOW_GUMR_L_TENC_NRZI 0x00000100
646#define UCC_SLOW_GUMR_L_TENC_NRZ 0x00000000
647#define UCC_SLOW_GUMR_L_DIAG_MASK 0x000000c0
648#define UCC_SLOW_GUMR_L_DIAG_LE 0x000000c0
649#define UCC_SLOW_GUMR_L_DIAG_ECHO 0x00000080
650#define UCC_SLOW_GUMR_L_DIAG_LOOP 0x00000040
651#define UCC_SLOW_GUMR_L_DIAG_NORM 0x00000000
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LY		 652#define UCC_SLOW_GUMR_L_ENR 0x00000020
653#define UCC_SLOW_GUMR_L_ENT 0x00000010
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TT		 654#define UCC_SLOW_GUMR_L_MODE_MASK 0x0000000F
655#define UCC_SLOW_GUMR_L_MODE_BISYNC 0x00000008
656#define UCC_SLOW_GUMR_L_MODE_AHDLC 0x00000006
657#define UCC_SLOW_GUMR_L_MODE_UART 0x00000004
658#define UCC_SLOW_GUMR_L_MODE_QMC 0x00000002
98658538
LY		 659
660/* General UCC FAST Mode Register */
c19b6d24 661#define UCC_FAST_GUMR_LOOPBACK 0x40000000
98658538
LY		 662#define UCC_FAST_GUMR_TCI 0x20000000
663#define UCC_FAST_GUMR_TRX 0x10000000
664#define UCC_FAST_GUMR_TTX 0x08000000
665#define UCC_FAST_GUMR_CDP 0x04000000
666#define UCC_FAST_GUMR_CTSP 0x02000000
667#define UCC_FAST_GUMR_CDS 0x01000000
668#define UCC_FAST_GUMR_CTSS 0x00800000
669#define UCC_FAST_GUMR_TXSY 0x00020000
670#define UCC_FAST_GUMR_RSYN 0x00010000
c7f235a7
HB		 671#define UCC_FAST_GUMR_SYNL_MASK 0x0000C000
672#define UCC_FAST_GUMR_SYNL_16 0x0000C000
673#define UCC_FAST_GUMR_SYNL_8 0x00008000
674#define UCC_FAST_GUMR_SYNL_AUTO 0x00004000
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LY		 675#define UCC_FAST_GUMR_RTSM 0x00002000
676#define UCC_FAST_GUMR_REVD 0x00000400
677#define UCC_FAST_GUMR_ENR 0x00000020
678#define UCC_FAST_GUMR_ENT 0x00000010
679
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TT		 680/* UART Slow UCC Event Register (UCCE) */
681#define UCC_UART_UCCE_AB 0x0200
682#define UCC_UART_UCCE_IDLE 0x0100
683#define UCC_UART_UCCE_GRA 0x0080
684#define UCC_UART_UCCE_BRKE 0x0040
685#define UCC_UART_UCCE_BRKS 0x0020
686#define UCC_UART_UCCE_CCR 0x0008
687#define UCC_UART_UCCE_BSY 0x0004
688#define UCC_UART_UCCE_TX 0x0002
689#define UCC_UART_UCCE_RX 0x0001
690
691/* HDLC Slow UCC Event Register (UCCE) */
692#define UCC_HDLC_UCCE_GLR 0x1000
693#define UCC_HDLC_UCCE_GLT 0x0800
694#define UCC_HDLC_UCCE_IDLE 0x0100
695#define UCC_HDLC_UCCE_BRKE 0x0040
696#define UCC_HDLC_UCCE_BRKS 0x0020
697#define UCC_HDLC_UCCE_TXE 0x0010
698#define UCC_HDLC_UCCE_RXF 0x0008
699#define UCC_HDLC_UCCE_BSY 0x0004
700#define UCC_HDLC_UCCE_TXB 0x0002
701#define UCC_HDLC_UCCE_RXB 0x0001
702
703/* BISYNC Slow UCC Event Register (UCCE) */
704#define UCC_BISYNC_UCCE_GRA 0x0080
705#define UCC_BISYNC_UCCE_TXE 0x0010
706#define UCC_BISYNC_UCCE_RCH 0x0008
707#define UCC_BISYNC_UCCE_BSY 0x0004
708#define UCC_BISYNC_UCCE_TXB 0x0002
709#define UCC_BISYNC_UCCE_RXB 0x0001
710
711/* Gigabit Ethernet Fast UCC Event Register (UCCE) */
712#define UCC_GETH_UCCE_MPD 0x80000000
713#define UCC_GETH_UCCE_SCAR 0x40000000
714#define UCC_GETH_UCCE_GRA 0x20000000
715#define UCC_GETH_UCCE_CBPR 0x10000000
716#define UCC_GETH_UCCE_BSY 0x08000000
717#define UCC_GETH_UCCE_RXC 0x04000000
718#define UCC_GETH_UCCE_TXC 0x02000000
719#define UCC_GETH_UCCE_TXE 0x01000000
720#define UCC_GETH_UCCE_TXB7 0x00800000
721#define UCC_GETH_UCCE_TXB6 0x00400000
722#define UCC_GETH_UCCE_TXB5 0x00200000
723#define UCC_GETH_UCCE_TXB4 0x00100000
724#define UCC_GETH_UCCE_TXB3 0x00080000
725#define UCC_GETH_UCCE_TXB2 0x00040000
726#define UCC_GETH_UCCE_TXB1 0x00020000
727#define UCC_GETH_UCCE_TXB0 0x00010000
728#define UCC_GETH_UCCE_RXB7 0x00008000
729#define UCC_GETH_UCCE_RXB6 0x00004000
730#define UCC_GETH_UCCE_RXB5 0x00002000
731#define UCC_GETH_UCCE_RXB4 0x00001000
732#define UCC_GETH_UCCE_RXB3 0x00000800
733#define UCC_GETH_UCCE_RXB2 0x00000400
734#define UCC_GETH_UCCE_RXB1 0x00000200
735#define UCC_GETH_UCCE_RXB0 0x00000100
736#define UCC_GETH_UCCE_RXF7 0x00000080
737#define UCC_GETH_UCCE_RXF6 0x00000040
738#define UCC_GETH_UCCE_RXF5 0x00000020
739#define UCC_GETH_UCCE_RXF4 0x00000010
740#define UCC_GETH_UCCE_RXF3 0x00000008
741#define UCC_GETH_UCCE_RXF2 0x00000004
742#define UCC_GETH_UCCE_RXF1 0x00000002
743#define UCC_GETH_UCCE_RXF0 0x00000001
744
fdd4e815 745/* UCC Protocol Specific Mode Register (UPSMR), when used for UART */
6b0b594b
TT		 746#define UCC_UART_UPSMR_FLC 0x8000
747#define UCC_UART_UPSMR_SL 0x4000
748#define UCC_UART_UPSMR_CL_MASK 0x3000
749#define UCC_UART_UPSMR_CL_8 0x3000
750#define UCC_UART_UPSMR_CL_7 0x2000
751#define UCC_UART_UPSMR_CL_6 0x1000
752#define UCC_UART_UPSMR_CL_5 0x0000
753#define UCC_UART_UPSMR_UM_MASK 0x0c00
754#define UCC_UART_UPSMR_UM_NORMAL 0x0000
755#define UCC_UART_UPSMR_UM_MAN_MULTI 0x0400
756#define UCC_UART_UPSMR_UM_AUTO_MULTI 0x0c00
757#define UCC_UART_UPSMR_FRZ 0x0200
758#define UCC_UART_UPSMR_RZS 0x0100
759#define UCC_UART_UPSMR_SYN 0x0080
760#define UCC_UART_UPSMR_DRT 0x0040
761#define UCC_UART_UPSMR_PEN 0x0010
762#define UCC_UART_UPSMR_RPM_MASK 0x000c
763#define UCC_UART_UPSMR_RPM_ODD 0x0000
764#define UCC_UART_UPSMR_RPM_LOW 0x0004
765#define UCC_UART_UPSMR_RPM_EVEN 0x0008
766#define UCC_UART_UPSMR_RPM_HIGH 0x000C
767#define UCC_UART_UPSMR_TPM_MASK 0x0003
768#define UCC_UART_UPSMR_TPM_ODD 0x0000
769#define UCC_UART_UPSMR_TPM_LOW 0x0001
770#define UCC_UART_UPSMR_TPM_EVEN 0x0002
771#define UCC_UART_UPSMR_TPM_HIGH 0x0003
98658538 772
fdd4e815
TT		 773/* UCC Protocol Specific Mode Register (UPSMR), when used for Ethernet */
774#define UCC_GETH_UPSMR_FTFE 0x80000000
775#define UCC_GETH_UPSMR_PTPE 0x40000000
776#define UCC_GETH_UPSMR_ECM 0x04000000
777#define UCC_GETH_UPSMR_HSE 0x02000000
778#define UCC_GETH_UPSMR_PRO 0x00400000
779#define UCC_GETH_UPSMR_CAP 0x00200000
780#define UCC_GETH_UPSMR_RSH 0x00100000
781#define UCC_GETH_UPSMR_RPM 0x00080000
782#define UCC_GETH_UPSMR_R10M 0x00040000
783#define UCC_GETH_UPSMR_RLPB 0x00020000
784#define UCC_GETH_UPSMR_TBIM 0x00010000
785#define UCC_GETH_UPSMR_RES1 0x00002000
786#define UCC_GETH_UPSMR_RMM 0x00001000
787#define UCC_GETH_UPSMR_CAM 0x00000400
788#define UCC_GETH_UPSMR_BRO 0x00000200
047584ce
HW		 789#define UCC_GETH_UPSMR_SMM 0x00000080
790#define UCC_GETH_UPSMR_SGMM 0x00000020
fdd4e815 791
067bb938
HB		 792/* UCC Protocol Specific Mode Register (UPSMR), when used for HDLC */
793#define UCC_HDLC_UPSMR_RTE 0x02000000
794#define UCC_HDLC_UPSMR_BUS 0x00200000
795#define UCC_HDLC_UPSMR_CW8 0x00007000
796
98658538
LY		 797/* UCC Transmit On Demand Register (UTODR) */
798#define UCC_SLOW_TOD 0x8000
799#define UCC_FAST_TOD 0x8000
800
6b0b594b
TT		 801/* UCC Bus Mode Register masks */
802/* Not to be confused with the Bundle Mode Register */
803#define UCC_BMR_GBL 0x20
804#define UCC_BMR_BO_BE 0x10
805#define UCC_BMR_CETM 0x04
806#define UCC_BMR_DTB 0x02
807#define UCC_BMR_BDB 0x01
808
98658538
LY		 809/* Function code masks */
810#define FC_GBL 0x20
811#define FC_DTB_LCL 0x02
812#define UCC_FAST_FUNCTION_CODE_GBL 0x20
813#define UCC_FAST_FUNCTION_CODE_DTB_LCL 0x02
814#define UCC_FAST_FUNCTION_CODE_BDB_LCL 0x01
815
98658538
LY		 816#endif /* __KERNEL__ */
817#endif /* _ASM_POWERPC_QE_H */
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