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2874c5fd | 1 | /* SPDX-License-Identifier: GPL-2.0-or-later */ |
98658538 | 2 | /* |
8a56e1ee | 3 | * Copyright (C) 2006 Freescale Semiconductor, Inc. All rights reserved. |
98658538 LY |
4 | * |
5 | * Authors: Shlomi Gridish <gridish@freescale.com> | |
6 | * Li Yang <leoli@freescale.com> | |
7 | * | |
8 | * Description: | |
9 | * QUICC Engine (QE) external definitions and structure. | |
98658538 LY |
10 | */ |
11 | #ifndef _ASM_POWERPC_QE_H | |
12 | #define _ASM_POWERPC_QE_H | |
13 | #ifdef __KERNEL__ | |
14 | ||
1291e49e ZQ |
15 | #include <linux/compiler.h> |
16 | #include <linux/genalloc.h> | |
5e41486c | 17 | #include <linux/spinlock.h> |
1b9e8904 AV |
18 | #include <linux/errno.h> |
19 | #include <linux/err.h> | |
5093bb96 | 20 | #include <asm/cpm.h> |
7aa1aa6e | 21 | #include <soc/fsl/qe/immap_qe.h> |
1291e49e ZQ |
22 | #include <linux/of.h> |
23 | #include <linux/of_address.h> | |
24 | #include <linux/types.h> | |
98658538 | 25 | |
98ca77af | 26 | #define QE_NUM_OF_SNUM 256 /* There are 256 serial number in QE */ |
98658538 LY |
27 | #define QE_NUM_OF_BRGS 16 |
28 | #define QE_NUM_OF_PORTS 1024 | |
29 | ||
30 | /* Memory partitions | |
31 | */ | |
32 | #define MEM_PART_SYSTEM 0 | |
33 | #define MEM_PART_SECONDARY 1 | |
34 | #define MEM_PART_MURAM 2 | |
35 | ||
7264ec44 TT |
36 | /* Clocks and BRGs */ |
37 | enum qe_clock { | |
38 | QE_CLK_NONE = 0, | |
39 | QE_BRG1, /* Baud Rate Generator 1 */ | |
40 | QE_BRG2, /* Baud Rate Generator 2 */ | |
41 | QE_BRG3, /* Baud Rate Generator 3 */ | |
42 | QE_BRG4, /* Baud Rate Generator 4 */ | |
43 | QE_BRG5, /* Baud Rate Generator 5 */ | |
44 | QE_BRG6, /* Baud Rate Generator 6 */ | |
45 | QE_BRG7, /* Baud Rate Generator 7 */ | |
46 | QE_BRG8, /* Baud Rate Generator 8 */ | |
47 | QE_BRG9, /* Baud Rate Generator 9 */ | |
48 | QE_BRG10, /* Baud Rate Generator 10 */ | |
49 | QE_BRG11, /* Baud Rate Generator 11 */ | |
50 | QE_BRG12, /* Baud Rate Generator 12 */ | |
51 | QE_BRG13, /* Baud Rate Generator 13 */ | |
52 | QE_BRG14, /* Baud Rate Generator 14 */ | |
53 | QE_BRG15, /* Baud Rate Generator 15 */ | |
54 | QE_BRG16, /* Baud Rate Generator 16 */ | |
55 | QE_CLK1, /* Clock 1 */ | |
56 | QE_CLK2, /* Clock 2 */ | |
57 | QE_CLK3, /* Clock 3 */ | |
58 | QE_CLK4, /* Clock 4 */ | |
59 | QE_CLK5, /* Clock 5 */ | |
60 | QE_CLK6, /* Clock 6 */ | |
61 | QE_CLK7, /* Clock 7 */ | |
62 | QE_CLK8, /* Clock 8 */ | |
63 | QE_CLK9, /* Clock 9 */ | |
64 | QE_CLK10, /* Clock 10 */ | |
65 | QE_CLK11, /* Clock 11 */ | |
66 | QE_CLK12, /* Clock 12 */ | |
67 | QE_CLK13, /* Clock 13 */ | |
68 | QE_CLK14, /* Clock 14 */ | |
69 | QE_CLK15, /* Clock 15 */ | |
70 | QE_CLK16, /* Clock 16 */ | |
71 | QE_CLK17, /* Clock 17 */ | |
72 | QE_CLK18, /* Clock 18 */ | |
73 | QE_CLK19, /* Clock 19 */ | |
74 | QE_CLK20, /* Clock 20 */ | |
75 | QE_CLK21, /* Clock 21 */ | |
76 | QE_CLK22, /* Clock 22 */ | |
77 | QE_CLK23, /* Clock 23 */ | |
78 | QE_CLK24, /* Clock 24 */ | |
68f047e3 ZQ |
79 | QE_RSYNC_PIN, /* RSYNC from pin */ |
80 | QE_TSYNC_PIN, /* TSYNC from pin */ | |
7264ec44 TT |
81 | QE_CLK_DUMMY |
82 | }; | |
83 | ||
5e41486c AV |
84 | static inline bool qe_clock_is_brg(enum qe_clock clk) |
85 | { | |
86 | return clk >= QE_BRG1 && clk <= QE_BRG16; | |
87 | } | |
88 | ||
89 | extern spinlock_t cmxgcr_lock; | |
90 | ||
98658538 | 91 | /* Export QE common operations */ |
be11d3b3 | 92 | #ifdef CONFIG_QUICC_ENGINE |
0c7b87b0 | 93 | extern void qe_reset(void); |
be11d3b3 AV |
94 | #else |
95 | static inline void qe_reset(void) {} | |
96 | #endif | |
9572653e | 97 | |
1291e49e ZQ |
98 | int cpm_muram_init(void); |
99 | ||
100 | #if defined(CONFIG_CPM) || defined(CONFIG_QUICC_ENGINE) | |
101 | unsigned long cpm_muram_alloc(unsigned long size, unsigned long align); | |
102 | int cpm_muram_free(unsigned long offset); | |
103 | unsigned long cpm_muram_alloc_fixed(unsigned long offset, unsigned long size); | |
1291e49e ZQ |
104 | void __iomem *cpm_muram_addr(unsigned long offset); |
105 | unsigned long cpm_muram_offset(void __iomem *addr); | |
106 | dma_addr_t cpm_muram_dma(void __iomem *addr); | |
107 | #else | |
108 | static inline unsigned long cpm_muram_alloc(unsigned long size, | |
109 | unsigned long align) | |
110 | { | |
111 | return -ENOSYS; | |
112 | } | |
113 | ||
114 | static inline int cpm_muram_free(unsigned long offset) | |
115 | { | |
116 | return -ENOSYS; | |
117 | } | |
118 | ||
119 | static inline unsigned long cpm_muram_alloc_fixed(unsigned long offset, | |
120 | unsigned long size) | |
121 | { | |
122 | return -ENOSYS; | |
123 | } | |
124 | ||
125 | static inline void __iomem *cpm_muram_addr(unsigned long offset) | |
126 | { | |
127 | return NULL; | |
128 | } | |
129 | ||
130 | static inline unsigned long cpm_muram_offset(void __iomem *addr) | |
131 | { | |
132 | return -ENOSYS; | |
133 | } | |
134 | ||
135 | static inline dma_addr_t cpm_muram_dma(void __iomem *addr) | |
136 | { | |
137 | return 0; | |
138 | } | |
139 | #endif /* defined(CONFIG_CPM) || defined(CONFIG_QUICC_ENGINE) */ | |
140 | ||
9572653e AV |
141 | /* QE PIO */ |
142 | #define QE_PIO_PINS 32 | |
143 | ||
144 | struct qe_pio_regs { | |
145 | __be32 cpodr; /* Open drain register */ | |
146 | __be32 cpdata; /* Data register */ | |
147 | __be32 cpdir1; /* Direction register */ | |
148 | __be32 cpdir2; /* Direction register */ | |
149 | __be32 cppar1; /* Pin assignment register */ | |
150 | __be32 cppar2; /* Pin assignment register */ | |
151 | #ifdef CONFIG_PPC_85xx | |
152 | u8 pad[8]; | |
153 | #endif | |
154 | }; | |
155 | ||
32def337 AV |
156 | #define QE_PIO_DIR_IN 2 |
157 | #define QE_PIO_DIR_OUT 1 | |
9572653e AV |
158 | extern void __par_io_config_pin(struct qe_pio_regs __iomem *par_io, u8 pin, |
159 | int dir, int open_drain, int assignment, | |
160 | int has_irq); | |
be11d3b3 AV |
161 | #ifdef CONFIG_QUICC_ENGINE |
162 | extern int par_io_init(struct device_node *np); | |
163 | extern int par_io_of_config(struct device_node *np); | |
364f8ffc AV |
164 | extern int par_io_config_pin(u8 port, u8 pin, int dir, int open_drain, |
165 | int assignment, int has_irq); | |
166 | extern int par_io_data_set(u8 port, u8 pin, u8 val); | |
be11d3b3 AV |
167 | #else |
168 | static inline int par_io_init(struct device_node *np) { return -ENOSYS; } | |
169 | static inline int par_io_of_config(struct device_node *np) { return -ENOSYS; } | |
170 | static inline int par_io_config_pin(u8 port, u8 pin, int dir, int open_drain, | |
171 | int assignment, int has_irq) { return -ENOSYS; } | |
172 | static inline int par_io_data_set(u8 port, u8 pin, u8 val) { return -ENOSYS; } | |
173 | #endif /* CONFIG_QUICC_ENGINE */ | |
98658538 | 174 | |
1b9e8904 AV |
175 | /* |
176 | * Pin multiplexing functions. | |
177 | */ | |
178 | struct qe_pin; | |
179 | #ifdef CONFIG_QE_GPIO | |
180 | extern struct qe_pin *qe_pin_request(struct device_node *np, int index); | |
181 | extern void qe_pin_free(struct qe_pin *qe_pin); | |
182 | extern void qe_pin_set_gpio(struct qe_pin *qe_pin); | |
183 | extern void qe_pin_set_dedicated(struct qe_pin *pin); | |
184 | #else | |
185 | static inline struct qe_pin *qe_pin_request(struct device_node *np, int index) | |
186 | { | |
187 | return ERR_PTR(-ENOSYS); | |
188 | } | |
189 | static inline void qe_pin_free(struct qe_pin *qe_pin) {} | |
190 | static inline void qe_pin_set_gpio(struct qe_pin *qe_pin) {} | |
191 | static inline void qe_pin_set_dedicated(struct qe_pin *pin) {} | |
192 | #endif /* CONFIG_QE_GPIO */ | |
193 | ||
58c12bdc | 194 | #ifdef CONFIG_QUICC_ENGINE |
98658538 | 195 | int qe_issue_cmd(u32 cmd, u32 device, u8 mcn_protocol, u32 cmd_input); |
58c12bdc AV |
196 | #else |
197 | static inline int qe_issue_cmd(u32 cmd, u32 device, u8 mcn_protocol, | |
198 | u32 cmd_input) | |
199 | { | |
200 | return -ENOSYS; | |
201 | } | |
202 | #endif /* CONFIG_QUICC_ENGINE */ | |
203 | ||
204 | /* QE internal API */ | |
174b0da2 | 205 | enum qe_clock qe_clock_source(const char *source); |
7f0a6fc8 | 206 | unsigned int qe_get_brg_clk(void); |
7264ec44 | 207 | int qe_setbrg(enum qe_clock brg, unsigned int rate, unsigned int multiplier); |
98658538 LY |
208 | int qe_get_snum(void); |
209 | void qe_put_snum(u8 snum); | |
06c44350 | 210 | unsigned int qe_get_num_of_risc(void); |
98ca77af | 211 | unsigned int qe_get_num_of_snums(void); |
46d22934 AV |
212 | |
213 | static inline int qe_alive_during_sleep(void) | |
214 | { | |
215 | /* | |
216 | * MPC8568E reference manual says: | |
217 | * | |
218 | * "...power down sequence waits for all I/O interfaces to become idle. | |
219 | * In some applications this may happen eventually without actively | |
220 | * shutting down interfaces, but most likely, software will have to | |
221 | * take steps to shut down the eTSEC, QUICC Engine Block, and PCI | |
222 | * interfaces before issuing the command (either the write to the core | |
223 | * MSR[WE] as described above or writing to POWMGTCSR) to put the | |
224 | * device into sleep state." | |
225 | * | |
226 | * MPC8569E reference manual has a similar paragraph. | |
227 | */ | |
228 | #ifdef CONFIG_PPC_85xx | |
229 | return 0; | |
230 | #else | |
231 | return 1; | |
232 | #endif | |
233 | } | |
06c44350 | 234 | |
5093bb96 AV |
235 | /* we actually use cpm_muram implementation, define this for convenience */ |
236 | #define qe_muram_init cpm_muram_init | |
237 | #define qe_muram_alloc cpm_muram_alloc | |
238 | #define qe_muram_alloc_fixed cpm_muram_alloc_fixed | |
239 | #define qe_muram_free cpm_muram_free | |
240 | #define qe_muram_addr cpm_muram_addr | |
241 | #define qe_muram_offset cpm_muram_offset | |
8b8642af | 242 | #define qe_muram_dma cpm_muram_dma |
98658538 | 243 | |
bb8b2062 ZQ |
244 | #define qe_setbits32(_addr, _v) iowrite32be(ioread32be(_addr) | (_v), (_addr)) |
245 | #define qe_clrbits32(_addr, _v) iowrite32be(ioread32be(_addr) & ~(_v), (_addr)) | |
246 | ||
247 | #define qe_setbits16(_addr, _v) iowrite16be(ioread16be(_addr) | (_v), (_addr)) | |
248 | #define qe_clrbits16(_addr, _v) iowrite16be(ioread16be(_addr) & ~(_v), (_addr)) | |
249 | ||
250 | #define qe_setbits8(_addr, _v) iowrite8(ioread8(_addr) | (_v), (_addr)) | |
251 | #define qe_clrbits8(_addr, _v) iowrite8(ioread8(_addr) & ~(_v), (_addr)) | |
252 | ||
253 | #define qe_clrsetbits32(addr, clear, set) \ | |
254 | iowrite32be((ioread32be(addr) & ~(clear)) | (set), (addr)) | |
255 | #define qe_clrsetbits16(addr, clear, set) \ | |
256 | iowrite16be((ioread16be(addr) & ~(clear)) | (set), (addr)) | |
257 | #define qe_clrsetbits8(addr, clear, set) \ | |
258 | iowrite8((ioread8(addr) & ~(clear)) | (set), (addr)) | |
259 | ||
bc556ba9 TT |
260 | /* Structure that defines QE firmware binary files. |
261 | * | |
395cf969 | 262 | * See Documentation/powerpc/qe_firmware.txt for a description of these |
bc556ba9 TT |
263 | * fields. |
264 | */ | |
265 | struct qe_firmware { | |
266 | struct qe_header { | |
267 | __be32 length; /* Length of the entire structure, in bytes */ | |
268 | u8 magic[3]; /* Set to { 'Q', 'E', 'F' } */ | |
269 | u8 version; /* Version of this layout. First ver is '1' */ | |
270 | } header; | |
271 | u8 id[62]; /* Null-terminated identifier string */ | |
272 | u8 split; /* 0 = shared I-RAM, 1 = split I-RAM */ | |
273 | u8 count; /* Number of microcode[] structures */ | |
274 | struct { | |
275 | __be16 model; /* The SOC model */ | |
276 | u8 major; /* The SOC revision major */ | |
277 | u8 minor; /* The SOC revision minor */ | |
278 | } __attribute__ ((packed)) soc; | |
279 | u8 padding[4]; /* Reserved, for alignment */ | |
280 | __be64 extended_modes; /* Extended modes */ | |
281 | __be32 vtraps[8]; /* Virtual trap addresses */ | |
282 | u8 reserved[4]; /* Reserved, for future expansion */ | |
283 | struct qe_microcode { | |
284 | u8 id[32]; /* Null-terminated identifier */ | |
285 | __be32 traps[16]; /* Trap addresses, 0 == ignore */ | |
286 | __be32 eccr; /* The value for the ECCR register */ | |
287 | __be32 iram_offset; /* Offset into I-RAM for the code */ | |
288 | __be32 count; /* Number of 32-bit words of the code */ | |
289 | __be32 code_offset; /* Offset of the actual microcode */ | |
290 | u8 major; /* The microcode version major */ | |
291 | u8 minor; /* The microcode version minor */ | |
292 | u8 revision; /* The microcode version revision */ | |
293 | u8 padding; /* Reserved, for alignment */ | |
294 | u8 reserved[4]; /* Reserved, for future expansion */ | |
295 | } __attribute__ ((packed)) microcode[1]; | |
296 | /* All microcode binaries should be located here */ | |
297 | /* CRC32 should be located here, after the microcode binaries */ | |
298 | } __attribute__ ((packed)); | |
299 | ||
300 | struct qe_firmware_info { | |
301 | char id[64]; /* Firmware name */ | |
302 | u32 vtraps[8]; /* Virtual trap addresses */ | |
303 | u64 extended_modes; /* Extended modes */ | |
304 | }; | |
305 | ||
b79ddf2c | 306 | #ifdef CONFIG_QUICC_ENGINE |
bc556ba9 TT |
307 | /* Upload a firmware to the QE */ |
308 | int qe_upload_firmware(const struct qe_firmware *firmware); | |
b79ddf2c AV |
309 | #else |
310 | static inline int qe_upload_firmware(const struct qe_firmware *firmware) | |
311 | { | |
312 | return -ENOSYS; | |
313 | } | |
314 | #endif /* CONFIG_QUICC_ENGINE */ | |
bc556ba9 TT |
315 | |
316 | /* Obtain information on the uploaded firmware */ | |
317 | struct qe_firmware_info *qe_get_firmware_info(void); | |
318 | ||
5e41486c AV |
319 | /* QE USB */ |
320 | int qe_usb_clock_set(enum qe_clock clk, int rate); | |
321 | ||
98658538 LY |
322 | /* Buffer descriptors */ |
323 | struct qe_bd { | |
6b0b594b TT |
324 | __be16 status; |
325 | __be16 length; | |
326 | __be32 buf; | |
98658538 LY |
327 | } __attribute__ ((packed)); |
328 | ||
329 | #define BD_STATUS_MASK 0xffff0000 | |
330 | #define BD_LENGTH_MASK 0x0000ffff | |
331 | ||
332 | /* Alignment */ | |
333 | #define QE_INTR_TABLE_ALIGN 16 /* ??? */ | |
334 | #define QE_ALIGNMENT_OF_BD 8 | |
335 | #define QE_ALIGNMENT_OF_PRAM 64 | |
336 | ||
337 | /* RISC allocation */ | |
06c44350 HW |
338 | #define QE_RISC_ALLOCATION_RISC1 0x1 /* RISC 1 */ |
339 | #define QE_RISC_ALLOCATION_RISC2 0x2 /* RISC 2 */ | |
340 | #define QE_RISC_ALLOCATION_RISC3 0x4 /* RISC 3 */ | |
341 | #define QE_RISC_ALLOCATION_RISC4 0x8 /* RISC 4 */ | |
342 | #define QE_RISC_ALLOCATION_RISC1_AND_RISC2 (QE_RISC_ALLOCATION_RISC1 | \ | |
343 | QE_RISC_ALLOCATION_RISC2) | |
344 | #define QE_RISC_ALLOCATION_FOUR_RISCS (QE_RISC_ALLOCATION_RISC1 | \ | |
345 | QE_RISC_ALLOCATION_RISC2 | \ | |
346 | QE_RISC_ALLOCATION_RISC3 | \ | |
347 | QE_RISC_ALLOCATION_RISC4) | |
98658538 LY |
348 | |
349 | /* QE extended filtering Table Lookup Key Size */ | |
350 | enum qe_fltr_tbl_lookup_key_size { | |
351 | QE_FLTR_TABLE_LOOKUP_KEY_SIZE_8_BYTES | |
352 | = 0x3f, /* LookupKey parsed by the Generate LookupKey | |
353 | CMD is truncated to 8 bytes */ | |
354 | QE_FLTR_TABLE_LOOKUP_KEY_SIZE_16_BYTES | |
355 | = 0x5f, /* LookupKey parsed by the Generate LookupKey | |
356 | CMD is truncated to 16 bytes */ | |
357 | }; | |
358 | ||
359 | /* QE FLTR extended filtering Largest External Table Lookup Key Size */ | |
360 | enum qe_fltr_largest_external_tbl_lookup_key_size { | |
361 | QE_FLTR_LARGEST_EXTERNAL_TABLE_LOOKUP_KEY_SIZE_NONE | |
362 | = 0x0,/* not used */ | |
363 | QE_FLTR_LARGEST_EXTERNAL_TABLE_LOOKUP_KEY_SIZE_8_BYTES | |
364 | = QE_FLTR_TABLE_LOOKUP_KEY_SIZE_8_BYTES, /* 8 bytes */ | |
365 | QE_FLTR_LARGEST_EXTERNAL_TABLE_LOOKUP_KEY_SIZE_16_BYTES | |
366 | = QE_FLTR_TABLE_LOOKUP_KEY_SIZE_16_BYTES, /* 16 bytes */ | |
367 | }; | |
368 | ||
369 | /* structure representing QE parameter RAM */ | |
370 | struct qe_timer_tables { | |
371 | u16 tm_base; /* QE timer table base adr */ | |
372 | u16 tm_ptr; /* QE timer table pointer */ | |
373 | u16 r_tmr; /* QE timer mode register */ | |
374 | u16 r_tmv; /* QE timer valid register */ | |
375 | u32 tm_cmd; /* QE timer cmd register */ | |
376 | u32 tm_cnt; /* QE timer internal cnt */ | |
377 | } __attribute__ ((packed)); | |
378 | ||
379 | #define QE_FLTR_TAD_SIZE 8 | |
380 | ||
381 | /* QE extended filtering Termination Action Descriptor (TAD) */ | |
382 | struct qe_fltr_tad { | |
383 | u8 serialized[QE_FLTR_TAD_SIZE]; | |
384 | } __attribute__ ((packed)); | |
385 | ||
386 | /* Communication Direction */ | |
387 | enum comm_dir { | |
388 | COMM_DIR_NONE = 0, | |
389 | COMM_DIR_RX = 1, | |
390 | COMM_DIR_TX = 2, | |
391 | COMM_DIR_RX_AND_TX = 3 | |
392 | }; | |
393 | ||
98658538 LY |
394 | /* QE CMXUCR Registers. |
395 | * There are two UCCs represented in each of the four CMXUCR registers. | |
396 | * These values are for the UCC in the LSBs | |
397 | */ | |
398 | #define QE_CMXUCR_MII_ENET_MNG 0x00007000 | |
399 | #define QE_CMXUCR_MII_ENET_MNG_SHIFT 12 | |
400 | #define QE_CMXUCR_GRANT 0x00008000 | |
401 | #define QE_CMXUCR_TSA 0x00004000 | |
402 | #define QE_CMXUCR_BKPT 0x00000100 | |
403 | #define QE_CMXUCR_TX_CLK_SRC_MASK 0x0000000F | |
404 | ||
405 | /* QE CMXGCR Registers. | |
406 | */ | |
407 | #define QE_CMXGCR_MII_ENET_MNG 0x00007000 | |
408 | #define QE_CMXGCR_MII_ENET_MNG_SHIFT 12 | |
409 | #define QE_CMXGCR_USBCS 0x0000000f | |
5e41486c AV |
410 | #define QE_CMXGCR_USBCS_CLK3 0x1 |
411 | #define QE_CMXGCR_USBCS_CLK5 0x2 | |
412 | #define QE_CMXGCR_USBCS_CLK7 0x3 | |
413 | #define QE_CMXGCR_USBCS_CLK9 0x4 | |
414 | #define QE_CMXGCR_USBCS_CLK13 0x5 | |
415 | #define QE_CMXGCR_USBCS_CLK17 0x6 | |
416 | #define QE_CMXGCR_USBCS_CLK19 0x7 | |
417 | #define QE_CMXGCR_USBCS_CLK21 0x8 | |
418 | #define QE_CMXGCR_USBCS_BRG9 0x9 | |
419 | #define QE_CMXGCR_USBCS_BRG10 0xa | |
98658538 LY |
420 | |
421 | /* QE CECR Commands. | |
422 | */ | |
423 | #define QE_CR_FLG 0x00010000 | |
424 | #define QE_RESET 0x80000000 | |
425 | #define QE_INIT_TX_RX 0x00000000 | |
426 | #define QE_INIT_RX 0x00000001 | |
427 | #define QE_INIT_TX 0x00000002 | |
428 | #define QE_ENTER_HUNT_MODE 0x00000003 | |
429 | #define QE_STOP_TX 0x00000004 | |
430 | #define QE_GRACEFUL_STOP_TX 0x00000005 | |
431 | #define QE_RESTART_TX 0x00000006 | |
432 | #define QE_CLOSE_RX_BD 0x00000007 | |
433 | #define QE_SWITCH_COMMAND 0x00000007 | |
434 | #define QE_SET_GROUP_ADDRESS 0x00000008 | |
435 | #define QE_START_IDMA 0x00000009 | |
436 | #define QE_MCC_STOP_RX 0x00000009 | |
437 | #define QE_ATM_TRANSMIT 0x0000000a | |
438 | #define QE_HPAC_CLEAR_ALL 0x0000000b | |
439 | #define QE_GRACEFUL_STOP_RX 0x0000001a | |
440 | #define QE_RESTART_RX 0x0000001b | |
441 | #define QE_HPAC_SET_PRIORITY 0x0000010b | |
442 | #define QE_HPAC_STOP_TX 0x0000020b | |
443 | #define QE_HPAC_STOP_RX 0x0000030b | |
444 | #define QE_HPAC_GRACEFUL_STOP_TX 0x0000040b | |
445 | #define QE_HPAC_GRACEFUL_STOP_RX 0x0000050b | |
446 | #define QE_HPAC_START_TX 0x0000060b | |
447 | #define QE_HPAC_START_RX 0x0000070b | |
448 | #define QE_USB_STOP_TX 0x0000000a | |
5e41486c | 449 | #define QE_USB_RESTART_TX 0x0000000c |
98658538 LY |
450 | #define QE_QMC_STOP_TX 0x0000000c |
451 | #define QE_QMC_STOP_RX 0x0000000d | |
452 | #define QE_SS7_SU_FIL_RESET 0x0000000e | |
453 | /* jonathbr added from here down for 83xx */ | |
454 | #define QE_RESET_BCS 0x0000000a | |
455 | #define QE_MCC_INIT_TX_RX_16 0x00000003 | |
456 | #define QE_MCC_STOP_TX 0x00000004 | |
457 | #define QE_MCC_INIT_TX_1 0x00000005 | |
458 | #define QE_MCC_INIT_RX_1 0x00000006 | |
459 | #define QE_MCC_RESET 0x00000007 | |
460 | #define QE_SET_TIMER 0x00000008 | |
461 | #define QE_RANDOM_NUMBER 0x0000000c | |
462 | #define QE_ATM_MULTI_THREAD_INIT 0x00000011 | |
463 | #define QE_ASSIGN_PAGE 0x00000012 | |
464 | #define QE_ADD_REMOVE_HASH_ENTRY 0x00000013 | |
465 | #define QE_START_FLOW_CONTROL 0x00000014 | |
466 | #define QE_STOP_FLOW_CONTROL 0x00000015 | |
467 | #define QE_ASSIGN_PAGE_TO_DEVICE 0x00000016 | |
468 | ||
469 | #define QE_ASSIGN_RISC 0x00000010 | |
470 | #define QE_CR_MCN_NORMAL_SHIFT 6 | |
471 | #define QE_CR_MCN_USB_SHIFT 4 | |
472 | #define QE_CR_MCN_RISC_ASSIGN_SHIFT 8 | |
473 | #define QE_CR_SNUM_SHIFT 17 | |
474 | ||
475 | /* QE CECR Sub Block - sub block of QE command. | |
476 | */ | |
477 | #define QE_CR_SUBBLOCK_INVALID 0x00000000 | |
478 | #define QE_CR_SUBBLOCK_USB 0x03200000 | |
479 | #define QE_CR_SUBBLOCK_UCCFAST1 0x02000000 | |
480 | #define QE_CR_SUBBLOCK_UCCFAST2 0x02200000 | |
481 | #define QE_CR_SUBBLOCK_UCCFAST3 0x02400000 | |
482 | #define QE_CR_SUBBLOCK_UCCFAST4 0x02600000 | |
483 | #define QE_CR_SUBBLOCK_UCCFAST5 0x02800000 | |
484 | #define QE_CR_SUBBLOCK_UCCFAST6 0x02a00000 | |
485 | #define QE_CR_SUBBLOCK_UCCFAST7 0x02c00000 | |
486 | #define QE_CR_SUBBLOCK_UCCFAST8 0x02e00000 | |
487 | #define QE_CR_SUBBLOCK_UCCSLOW1 0x00000000 | |
488 | #define QE_CR_SUBBLOCK_UCCSLOW2 0x00200000 | |
489 | #define QE_CR_SUBBLOCK_UCCSLOW3 0x00400000 | |
490 | #define QE_CR_SUBBLOCK_UCCSLOW4 0x00600000 | |
491 | #define QE_CR_SUBBLOCK_UCCSLOW5 0x00800000 | |
492 | #define QE_CR_SUBBLOCK_UCCSLOW6 0x00a00000 | |
493 | #define QE_CR_SUBBLOCK_UCCSLOW7 0x00c00000 | |
494 | #define QE_CR_SUBBLOCK_UCCSLOW8 0x00e00000 | |
495 | #define QE_CR_SUBBLOCK_MCC1 0x03800000 | |
496 | #define QE_CR_SUBBLOCK_MCC2 0x03a00000 | |
497 | #define QE_CR_SUBBLOCK_MCC3 0x03000000 | |
498 | #define QE_CR_SUBBLOCK_IDMA1 0x02800000 | |
499 | #define QE_CR_SUBBLOCK_IDMA2 0x02a00000 | |
500 | #define QE_CR_SUBBLOCK_IDMA3 0x02c00000 | |
501 | #define QE_CR_SUBBLOCK_IDMA4 0x02e00000 | |
502 | #define QE_CR_SUBBLOCK_HPAC 0x01e00000 | |
503 | #define QE_CR_SUBBLOCK_SPI1 0x01400000 | |
504 | #define QE_CR_SUBBLOCK_SPI2 0x01600000 | |
505 | #define QE_CR_SUBBLOCK_RAND 0x01c00000 | |
506 | #define QE_CR_SUBBLOCK_TIMER 0x01e00000 | |
507 | #define QE_CR_SUBBLOCK_GENERAL 0x03c00000 | |
508 | ||
509 | /* QE CECR Protocol - For non-MCC, specifies mode for QE CECR command */ | |
510 | #define QE_CR_PROTOCOL_UNSPECIFIED 0x00 /* For all other protocols */ | |
511 | #define QE_CR_PROTOCOL_HDLC_TRANSPARENT 0x00 | |
6b0b594b TT |
512 | #define QE_CR_PROTOCOL_QMC 0x02 |
513 | #define QE_CR_PROTOCOL_UART 0x04 | |
98658538 LY |
514 | #define QE_CR_PROTOCOL_ATM_POS 0x0A |
515 | #define QE_CR_PROTOCOL_ETHERNET 0x0C | |
516 | #define QE_CR_PROTOCOL_L2_SWITCH 0x0D | |
517 | ||
98658538 LY |
518 | /* BRG configuration register */ |
519 | #define QE_BRGC_ENABLE 0x00010000 | |
520 | #define QE_BRGC_DIVISOR_SHIFT 1 | |
521 | #define QE_BRGC_DIVISOR_MAX 0xFFF | |
522 | #define QE_BRGC_DIV16 1 | |
523 | ||
524 | /* QE Timers registers */ | |
525 | #define QE_GTCFR1_PCAS 0x80 | |
526 | #define QE_GTCFR1_STP2 0x20 | |
527 | #define QE_GTCFR1_RST2 0x10 | |
528 | #define QE_GTCFR1_GM2 0x08 | |
529 | #define QE_GTCFR1_GM1 0x04 | |
530 | #define QE_GTCFR1_STP1 0x02 | |
531 | #define QE_GTCFR1_RST1 0x01 | |
532 | ||
533 | /* SDMA registers */ | |
534 | #define QE_SDSR_BER1 0x02000000 | |
535 | #define QE_SDSR_BER2 0x01000000 | |
536 | ||
537 | #define QE_SDMR_GLB_1_MSK 0x80000000 | |
538 | #define QE_SDMR_ADR_SEL 0x20000000 | |
539 | #define QE_SDMR_BER1_MSK 0x02000000 | |
540 | #define QE_SDMR_BER2_MSK 0x01000000 | |
541 | #define QE_SDMR_EB1_MSK 0x00800000 | |
542 | #define QE_SDMR_ER1_MSK 0x00080000 | |
543 | #define QE_SDMR_ER2_MSK 0x00040000 | |
544 | #define QE_SDMR_CEN_MASK 0x0000E000 | |
545 | #define QE_SDMR_SBER_1 0x00000200 | |
546 | #define QE_SDMR_SBER_2 0x00000200 | |
547 | #define QE_SDMR_EB1_PR_MASK 0x000000C0 | |
548 | #define QE_SDMR_ER1_PR 0x00000008 | |
549 | ||
550 | #define QE_SDMR_CEN_SHIFT 13 | |
551 | #define QE_SDMR_EB1_PR_SHIFT 6 | |
552 | ||
553 | #define QE_SDTM_MSNUM_SHIFT 24 | |
554 | ||
555 | #define QE_SDEBCR_BA_MASK 0x01FFFFFF | |
556 | ||
bc556ba9 TT |
557 | /* Communication Processor */ |
558 | #define QE_CP_CERCR_MEE 0x8000 /* Multi-user RAM ECC enable */ | |
559 | #define QE_CP_CERCR_IEE 0x4000 /* Instruction RAM ECC enable */ | |
560 | #define QE_CP_CERCR_CIR 0x0800 /* Common instruction RAM */ | |
561 | ||
562 | /* I-RAM */ | |
563 | #define QE_IRAM_IADD_AIE 0x80000000 /* Auto Increment Enable */ | |
564 | #define QE_IRAM_IADD_BADDR 0x00080000 /* Base Address */ | |
e65650e6 | 565 | #define QE_IRAM_READY 0x80000000 /* Ready */ |
bc556ba9 | 566 | |
98658538 LY |
567 | /* UPC */ |
568 | #define UPGCR_PROTOCOL 0x80000000 /* protocol ul2 or pl2 */ | |
569 | #define UPGCR_TMS 0x40000000 /* Transmit master/slave mode */ | |
570 | #define UPGCR_RMS 0x20000000 /* Receive master/slave mode */ | |
571 | #define UPGCR_ADDR 0x10000000 /* Master MPHY Addr multiplexing */ | |
572 | #define UPGCR_DIAG 0x01000000 /* Diagnostic mode */ | |
573 | ||
6b0b594b | 574 | /* UCC GUEMR register */ |
98658538 | 575 | #define UCC_GUEMR_MODE_MASK_RX 0x02 |
98658538 | 576 | #define UCC_GUEMR_MODE_FAST_RX 0x02 |
98658538 | 577 | #define UCC_GUEMR_MODE_SLOW_RX 0x00 |
6b0b594b TT |
578 | #define UCC_GUEMR_MODE_MASK_TX 0x01 |
579 | #define UCC_GUEMR_MODE_FAST_TX 0x01 | |
98658538 | 580 | #define UCC_GUEMR_MODE_SLOW_TX 0x00 |
6b0b594b | 581 | #define UCC_GUEMR_MODE_MASK (UCC_GUEMR_MODE_MASK_RX | UCC_GUEMR_MODE_MASK_TX) |
98658538 LY |
582 | #define UCC_GUEMR_SET_RESERVED3 0x10 /* Bit 3 in the guemr is reserved but |
583 | must be set 1 */ | |
584 | ||
585 | /* structure representing UCC SLOW parameter RAM */ | |
586 | struct ucc_slow_pram { | |
6b0b594b TT |
587 | __be16 rbase; /* RX BD base address */ |
588 | __be16 tbase; /* TX BD base address */ | |
589 | u8 rbmr; /* RX bus mode register (same as CPM's RFCR) */ | |
590 | u8 tbmr; /* TX bus mode register (same as CPM's TFCR) */ | |
591 | __be16 mrblr; /* Rx buffer length */ | |
592 | __be32 rstate; /* Rx internal state */ | |
593 | __be32 rptr; /* Rx internal data pointer */ | |
594 | __be16 rbptr; /* rb BD Pointer */ | |
595 | __be16 rcount; /* Rx internal byte count */ | |
596 | __be32 rtemp; /* Rx temp */ | |
597 | __be32 tstate; /* Tx internal state */ | |
598 | __be32 tptr; /* Tx internal data pointer */ | |
599 | __be16 tbptr; /* Tx BD pointer */ | |
600 | __be16 tcount; /* Tx byte count */ | |
601 | __be32 ttemp; /* Tx temp */ | |
602 | __be32 rcrc; /* temp receive CRC */ | |
603 | __be32 tcrc; /* temp transmit CRC */ | |
98658538 LY |
604 | } __attribute__ ((packed)); |
605 | ||
606 | /* General UCC SLOW Mode Register (GUMRH & GUMRL) */ | |
6b0b594b TT |
607 | #define UCC_SLOW_GUMR_H_SAM_QMC 0x00000000 |
608 | #define UCC_SLOW_GUMR_H_SAM_SATM 0x00008000 | |
98658538 LY |
609 | #define UCC_SLOW_GUMR_H_REVD 0x00002000 |
610 | #define UCC_SLOW_GUMR_H_TRX 0x00001000 | |
611 | #define UCC_SLOW_GUMR_H_TTX 0x00000800 | |
612 | #define UCC_SLOW_GUMR_H_CDP 0x00000400 | |
613 | #define UCC_SLOW_GUMR_H_CTSP 0x00000200 | |
614 | #define UCC_SLOW_GUMR_H_CDS 0x00000100 | |
615 | #define UCC_SLOW_GUMR_H_CTSS 0x00000080 | |
616 | #define UCC_SLOW_GUMR_H_TFL 0x00000040 | |
617 | #define UCC_SLOW_GUMR_H_RFW 0x00000020 | |
618 | #define UCC_SLOW_GUMR_H_TXSY 0x00000010 | |
619 | #define UCC_SLOW_GUMR_H_4SYNC 0x00000004 | |
620 | #define UCC_SLOW_GUMR_H_8SYNC 0x00000008 | |
621 | #define UCC_SLOW_GUMR_H_16SYNC 0x0000000c | |
622 | #define UCC_SLOW_GUMR_H_RTSM 0x00000002 | |
623 | #define UCC_SLOW_GUMR_H_RSYN 0x00000001 | |
624 | ||
625 | #define UCC_SLOW_GUMR_L_TCI 0x10000000 | |
626 | #define UCC_SLOW_GUMR_L_RINV 0x02000000 | |
627 | #define UCC_SLOW_GUMR_L_TINV 0x01000000 | |
6b0b594b TT |
628 | #define UCC_SLOW_GUMR_L_TEND 0x00040000 |
629 | #define UCC_SLOW_GUMR_L_TDCR_MASK 0x00030000 | |
630 | #define UCC_SLOW_GUMR_L_TDCR_32 0x00030000 | |
631 | #define UCC_SLOW_GUMR_L_TDCR_16 0x00020000 | |
632 | #define UCC_SLOW_GUMR_L_TDCR_8 0x00010000 | |
633 | #define UCC_SLOW_GUMR_L_TDCR_1 0x00000000 | |
634 | #define UCC_SLOW_GUMR_L_RDCR_MASK 0x0000c000 | |
635 | #define UCC_SLOW_GUMR_L_RDCR_32 0x0000c000 | |
636 | #define UCC_SLOW_GUMR_L_RDCR_16 0x00008000 | |
637 | #define UCC_SLOW_GUMR_L_RDCR_8 0x00004000 | |
638 | #define UCC_SLOW_GUMR_L_RDCR_1 0x00000000 | |
639 | #define UCC_SLOW_GUMR_L_RENC_NRZI 0x00000800 | |
640 | #define UCC_SLOW_GUMR_L_RENC_NRZ 0x00000000 | |
641 | #define UCC_SLOW_GUMR_L_TENC_NRZI 0x00000100 | |
642 | #define UCC_SLOW_GUMR_L_TENC_NRZ 0x00000000 | |
643 | #define UCC_SLOW_GUMR_L_DIAG_MASK 0x000000c0 | |
644 | #define UCC_SLOW_GUMR_L_DIAG_LE 0x000000c0 | |
645 | #define UCC_SLOW_GUMR_L_DIAG_ECHO 0x00000080 | |
646 | #define UCC_SLOW_GUMR_L_DIAG_LOOP 0x00000040 | |
647 | #define UCC_SLOW_GUMR_L_DIAG_NORM 0x00000000 | |
98658538 LY |
648 | #define UCC_SLOW_GUMR_L_ENR 0x00000020 |
649 | #define UCC_SLOW_GUMR_L_ENT 0x00000010 | |
6b0b594b TT |
650 | #define UCC_SLOW_GUMR_L_MODE_MASK 0x0000000F |
651 | #define UCC_SLOW_GUMR_L_MODE_BISYNC 0x00000008 | |
652 | #define UCC_SLOW_GUMR_L_MODE_AHDLC 0x00000006 | |
653 | #define UCC_SLOW_GUMR_L_MODE_UART 0x00000004 | |
654 | #define UCC_SLOW_GUMR_L_MODE_QMC 0x00000002 | |
98658538 LY |
655 | |
656 | /* General UCC FAST Mode Register */ | |
c19b6d24 | 657 | #define UCC_FAST_GUMR_LOOPBACK 0x40000000 |
98658538 LY |
658 | #define UCC_FAST_GUMR_TCI 0x20000000 |
659 | #define UCC_FAST_GUMR_TRX 0x10000000 | |
660 | #define UCC_FAST_GUMR_TTX 0x08000000 | |
661 | #define UCC_FAST_GUMR_CDP 0x04000000 | |
662 | #define UCC_FAST_GUMR_CTSP 0x02000000 | |
663 | #define UCC_FAST_GUMR_CDS 0x01000000 | |
664 | #define UCC_FAST_GUMR_CTSS 0x00800000 | |
665 | #define UCC_FAST_GUMR_TXSY 0x00020000 | |
666 | #define UCC_FAST_GUMR_RSYN 0x00010000 | |
c7f235a7 HB |
667 | #define UCC_FAST_GUMR_SYNL_MASK 0x0000C000 |
668 | #define UCC_FAST_GUMR_SYNL_16 0x0000C000 | |
669 | #define UCC_FAST_GUMR_SYNL_8 0x00008000 | |
670 | #define UCC_FAST_GUMR_SYNL_AUTO 0x00004000 | |
98658538 LY |
671 | #define UCC_FAST_GUMR_RTSM 0x00002000 |
672 | #define UCC_FAST_GUMR_REVD 0x00000400 | |
673 | #define UCC_FAST_GUMR_ENR 0x00000020 | |
674 | #define UCC_FAST_GUMR_ENT 0x00000010 | |
675 | ||
6b0b594b TT |
676 | /* UART Slow UCC Event Register (UCCE) */ |
677 | #define UCC_UART_UCCE_AB 0x0200 | |
678 | #define UCC_UART_UCCE_IDLE 0x0100 | |
679 | #define UCC_UART_UCCE_GRA 0x0080 | |
680 | #define UCC_UART_UCCE_BRKE 0x0040 | |
681 | #define UCC_UART_UCCE_BRKS 0x0020 | |
682 | #define UCC_UART_UCCE_CCR 0x0008 | |
683 | #define UCC_UART_UCCE_BSY 0x0004 | |
684 | #define UCC_UART_UCCE_TX 0x0002 | |
685 | #define UCC_UART_UCCE_RX 0x0001 | |
686 | ||
687 | /* HDLC Slow UCC Event Register (UCCE) */ | |
688 | #define UCC_HDLC_UCCE_GLR 0x1000 | |
689 | #define UCC_HDLC_UCCE_GLT 0x0800 | |
690 | #define UCC_HDLC_UCCE_IDLE 0x0100 | |
691 | #define UCC_HDLC_UCCE_BRKE 0x0040 | |
692 | #define UCC_HDLC_UCCE_BRKS 0x0020 | |
693 | #define UCC_HDLC_UCCE_TXE 0x0010 | |
694 | #define UCC_HDLC_UCCE_RXF 0x0008 | |
695 | #define UCC_HDLC_UCCE_BSY 0x0004 | |
696 | #define UCC_HDLC_UCCE_TXB 0x0002 | |
697 | #define UCC_HDLC_UCCE_RXB 0x0001 | |
698 | ||
699 | /* BISYNC Slow UCC Event Register (UCCE) */ | |
700 | #define UCC_BISYNC_UCCE_GRA 0x0080 | |
701 | #define UCC_BISYNC_UCCE_TXE 0x0010 | |
702 | #define UCC_BISYNC_UCCE_RCH 0x0008 | |
703 | #define UCC_BISYNC_UCCE_BSY 0x0004 | |
704 | #define UCC_BISYNC_UCCE_TXB 0x0002 | |
705 | #define UCC_BISYNC_UCCE_RXB 0x0001 | |
706 | ||
707 | /* Gigabit Ethernet Fast UCC Event Register (UCCE) */ | |
708 | #define UCC_GETH_UCCE_MPD 0x80000000 | |
709 | #define UCC_GETH_UCCE_SCAR 0x40000000 | |
710 | #define UCC_GETH_UCCE_GRA 0x20000000 | |
711 | #define UCC_GETH_UCCE_CBPR 0x10000000 | |
712 | #define UCC_GETH_UCCE_BSY 0x08000000 | |
713 | #define UCC_GETH_UCCE_RXC 0x04000000 | |
714 | #define UCC_GETH_UCCE_TXC 0x02000000 | |
715 | #define UCC_GETH_UCCE_TXE 0x01000000 | |
716 | #define UCC_GETH_UCCE_TXB7 0x00800000 | |
717 | #define UCC_GETH_UCCE_TXB6 0x00400000 | |
718 | #define UCC_GETH_UCCE_TXB5 0x00200000 | |
719 | #define UCC_GETH_UCCE_TXB4 0x00100000 | |
720 | #define UCC_GETH_UCCE_TXB3 0x00080000 | |
721 | #define UCC_GETH_UCCE_TXB2 0x00040000 | |
722 | #define UCC_GETH_UCCE_TXB1 0x00020000 | |
723 | #define UCC_GETH_UCCE_TXB0 0x00010000 | |
724 | #define UCC_GETH_UCCE_RXB7 0x00008000 | |
725 | #define UCC_GETH_UCCE_RXB6 0x00004000 | |
726 | #define UCC_GETH_UCCE_RXB5 0x00002000 | |
727 | #define UCC_GETH_UCCE_RXB4 0x00001000 | |
728 | #define UCC_GETH_UCCE_RXB3 0x00000800 | |
729 | #define UCC_GETH_UCCE_RXB2 0x00000400 | |
730 | #define UCC_GETH_UCCE_RXB1 0x00000200 | |
731 | #define UCC_GETH_UCCE_RXB0 0x00000100 | |
732 | #define UCC_GETH_UCCE_RXF7 0x00000080 | |
733 | #define UCC_GETH_UCCE_RXF6 0x00000040 | |
734 | #define UCC_GETH_UCCE_RXF5 0x00000020 | |
735 | #define UCC_GETH_UCCE_RXF4 0x00000010 | |
736 | #define UCC_GETH_UCCE_RXF3 0x00000008 | |
737 | #define UCC_GETH_UCCE_RXF2 0x00000004 | |
738 | #define UCC_GETH_UCCE_RXF1 0x00000002 | |
739 | #define UCC_GETH_UCCE_RXF0 0x00000001 | |
740 | ||
fdd4e815 | 741 | /* UCC Protocol Specific Mode Register (UPSMR), when used for UART */ |
6b0b594b TT |
742 | #define UCC_UART_UPSMR_FLC 0x8000 |
743 | #define UCC_UART_UPSMR_SL 0x4000 | |
744 | #define UCC_UART_UPSMR_CL_MASK 0x3000 | |
745 | #define UCC_UART_UPSMR_CL_8 0x3000 | |
746 | #define UCC_UART_UPSMR_CL_7 0x2000 | |
747 | #define UCC_UART_UPSMR_CL_6 0x1000 | |
748 | #define UCC_UART_UPSMR_CL_5 0x0000 | |
749 | #define UCC_UART_UPSMR_UM_MASK 0x0c00 | |
750 | #define UCC_UART_UPSMR_UM_NORMAL 0x0000 | |
751 | #define UCC_UART_UPSMR_UM_MAN_MULTI 0x0400 | |
752 | #define UCC_UART_UPSMR_UM_AUTO_MULTI 0x0c00 | |
753 | #define UCC_UART_UPSMR_FRZ 0x0200 | |
754 | #define UCC_UART_UPSMR_RZS 0x0100 | |
755 | #define UCC_UART_UPSMR_SYN 0x0080 | |
756 | #define UCC_UART_UPSMR_DRT 0x0040 | |
757 | #define UCC_UART_UPSMR_PEN 0x0010 | |
758 | #define UCC_UART_UPSMR_RPM_MASK 0x000c | |
759 | #define UCC_UART_UPSMR_RPM_ODD 0x0000 | |
760 | #define UCC_UART_UPSMR_RPM_LOW 0x0004 | |
761 | #define UCC_UART_UPSMR_RPM_EVEN 0x0008 | |
762 | #define UCC_UART_UPSMR_RPM_HIGH 0x000C | |
763 | #define UCC_UART_UPSMR_TPM_MASK 0x0003 | |
764 | #define UCC_UART_UPSMR_TPM_ODD 0x0000 | |
765 | #define UCC_UART_UPSMR_TPM_LOW 0x0001 | |
766 | #define UCC_UART_UPSMR_TPM_EVEN 0x0002 | |
767 | #define UCC_UART_UPSMR_TPM_HIGH 0x0003 | |
98658538 | 768 | |
fdd4e815 TT |
769 | /* UCC Protocol Specific Mode Register (UPSMR), when used for Ethernet */ |
770 | #define UCC_GETH_UPSMR_FTFE 0x80000000 | |
771 | #define UCC_GETH_UPSMR_PTPE 0x40000000 | |
772 | #define UCC_GETH_UPSMR_ECM 0x04000000 | |
773 | #define UCC_GETH_UPSMR_HSE 0x02000000 | |
774 | #define UCC_GETH_UPSMR_PRO 0x00400000 | |
775 | #define UCC_GETH_UPSMR_CAP 0x00200000 | |
776 | #define UCC_GETH_UPSMR_RSH 0x00100000 | |
777 | #define UCC_GETH_UPSMR_RPM 0x00080000 | |
778 | #define UCC_GETH_UPSMR_R10M 0x00040000 | |
779 | #define UCC_GETH_UPSMR_RLPB 0x00020000 | |
780 | #define UCC_GETH_UPSMR_TBIM 0x00010000 | |
781 | #define UCC_GETH_UPSMR_RES1 0x00002000 | |
782 | #define UCC_GETH_UPSMR_RMM 0x00001000 | |
783 | #define UCC_GETH_UPSMR_CAM 0x00000400 | |
784 | #define UCC_GETH_UPSMR_BRO 0x00000200 | |
047584ce HW |
785 | #define UCC_GETH_UPSMR_SMM 0x00000080 |
786 | #define UCC_GETH_UPSMR_SGMM 0x00000020 | |
fdd4e815 | 787 | |
067bb938 HB |
788 | /* UCC Protocol Specific Mode Register (UPSMR), when used for HDLC */ |
789 | #define UCC_HDLC_UPSMR_RTE 0x02000000 | |
790 | #define UCC_HDLC_UPSMR_BUS 0x00200000 | |
791 | #define UCC_HDLC_UPSMR_CW8 0x00007000 | |
792 | ||
98658538 LY |
793 | /* UCC Transmit On Demand Register (UTODR) */ |
794 | #define UCC_SLOW_TOD 0x8000 | |
795 | #define UCC_FAST_TOD 0x8000 | |
796 | ||
6b0b594b TT |
797 | /* UCC Bus Mode Register masks */ |
798 | /* Not to be confused with the Bundle Mode Register */ | |
799 | #define UCC_BMR_GBL 0x20 | |
800 | #define UCC_BMR_BO_BE 0x10 | |
801 | #define UCC_BMR_CETM 0x04 | |
802 | #define UCC_BMR_DTB 0x02 | |
803 | #define UCC_BMR_BDB 0x01 | |
804 | ||
98658538 LY |
805 | /* Function code masks */ |
806 | #define FC_GBL 0x20 | |
807 | #define FC_DTB_LCL 0x02 | |
808 | #define UCC_FAST_FUNCTION_CODE_GBL 0x20 | |
809 | #define UCC_FAST_FUNCTION_CODE_DTB_LCL 0x02 | |
810 | #define UCC_FAST_FUNCTION_CODE_BDB_LCL 0x01 | |
811 | ||
98658538 LY |
812 | #endif /* __KERNEL__ */ |
813 | #endif /* _ASM_POWERPC_QE_H */ |