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1 | /* Copyright 2008 - 2016 Freescale Semiconductor, Inc. |
2 | * | |
3 | * Redistribution and use in source and binary forms, with or without | |
4 | * modification, are permitted provided that the following conditions are met: | |
5 | * * Redistributions of source code must retain the above copyright | |
6 | * notice, this list of conditions and the following disclaimer. | |
7 | * * Redistributions in binary form must reproduce the above copyright | |
8 | * notice, this list of conditions and the following disclaimer in the | |
9 | * documentation and/or other materials provided with the distribution. | |
10 | * * Neither the name of Freescale Semiconductor nor the | |
11 | * names of its contributors may be used to endorse or promote products | |
12 | * derived from this software without specific prior written permission. | |
13 | * | |
14 | * ALTERNATIVELY, this software may be distributed under the terms of the | |
15 | * GNU General Public License ("GPL") as published by the Free Software | |
16 | * Foundation, either version 2 of that License or (at your option) any | |
17 | * later version. | |
18 | * | |
19 | * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY | |
20 | * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED | |
21 | * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE | |
22 | * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY | |
23 | * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES | |
24 | * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; | |
25 | * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND | |
26 | * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT | |
27 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS | |
28 | * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. | |
29 | */ | |
30 | ||
31 | #ifndef __FSL_QMAN_H | |
32 | #define __FSL_QMAN_H | |
33 | ||
34 | #include <linux/bitops.h> | |
35 | ||
36 | /* Hardware constants */ | |
37 | #define QM_CHANNEL_SWPORTAL0 0 | |
38 | #define QMAN_CHANNEL_POOL1 0x21 | |
39 | #define QMAN_CHANNEL_POOL1_REV3 0x401 | |
40 | extern u16 qm_channel_pool1; | |
41 | ||
42 | /* Portal processing (interrupt) sources */ | |
43 | #define QM_PIRQ_CSCI 0x00100000 /* Congestion State Change */ | |
44 | #define QM_PIRQ_EQCI 0x00080000 /* Enqueue Command Committed */ | |
45 | #define QM_PIRQ_EQRI 0x00040000 /* EQCR Ring (below threshold) */ | |
46 | #define QM_PIRQ_DQRI 0x00020000 /* DQRR Ring (non-empty) */ | |
47 | #define QM_PIRQ_MRI 0x00010000 /* MR Ring (non-empty) */ | |
48 | /* | |
49 | * This mask contains all the interrupt sources that need handling except DQRI, | |
50 | * ie. that if present should trigger slow-path processing. | |
51 | */ | |
52 | #define QM_PIRQ_SLOW (QM_PIRQ_CSCI | QM_PIRQ_EQCI | QM_PIRQ_EQRI | \ | |
53 | QM_PIRQ_MRI) | |
54 | ||
55 | /* For qman_static_dequeue_*** APIs */ | |
56 | #define QM_SDQCR_CHANNELS_POOL_MASK 0x00007fff | |
57 | /* for n in [1,15] */ | |
58 | #define QM_SDQCR_CHANNELS_POOL(n) (0x00008000 >> (n)) | |
59 | /* for conversion from n of qm_channel */ | |
60 | static inline u32 QM_SDQCR_CHANNELS_POOL_CONV(u16 channel) | |
61 | { | |
62 | return QM_SDQCR_CHANNELS_POOL(channel + 1 - qm_channel_pool1); | |
63 | } | |
64 | ||
65 | /* --- QMan data structures (and associated constants) --- */ | |
66 | ||
67 | /* "Frame Descriptor (FD)" */ | |
68 | struct qm_fd { | |
69 | union { | |
70 | struct { | |
71 | u8 cfg8b_w1; | |
72 | u8 bpid; /* Buffer Pool ID */ | |
73 | u8 cfg8b_w3; | |
74 | u8 addr_hi; /* high 8-bits of 40-bit address */ | |
75 | __be32 addr_lo; /* low 32-bits of 40-bit address */ | |
76 | } __packed; | |
77 | __be64 data; | |
78 | }; | |
79 | __be32 cfg; /* format, offset, length / congestion */ | |
80 | union { | |
81 | __be32 cmd; | |
82 | __be32 status; | |
83 | }; | |
84 | } __aligned(8); | |
85 | ||
86 | #define QM_FD_FORMAT_SG BIT(31) | |
87 | #define QM_FD_FORMAT_LONG BIT(30) | |
88 | #define QM_FD_FORMAT_COMPOUND BIT(29) | |
89 | #define QM_FD_FORMAT_MASK GENMASK(31, 29) | |
90 | #define QM_FD_OFF_SHIFT 20 | |
91 | #define QM_FD_OFF_MASK GENMASK(28, 20) | |
92 | #define QM_FD_LEN_MASK GENMASK(19, 0) | |
93 | #define QM_FD_LEN_BIG_MASK GENMASK(28, 0) | |
94 | ||
95 | enum qm_fd_format { | |
96 | /* | |
97 | * 'contig' implies a contiguous buffer, whereas 'sg' implies a | |
98 | * scatter-gather table. 'big' implies a 29-bit length with no offset | |
99 | * field, otherwise length is 20-bit and offset is 9-bit. 'compound' | |
100 | * implies a s/g-like table, where each entry itself represents a frame | |
101 | * (contiguous or scatter-gather) and the 29-bit "length" is | |
102 | * interpreted purely for congestion calculations, ie. a "congestion | |
103 | * weight". | |
104 | */ | |
105 | qm_fd_contig = 0, | |
106 | qm_fd_contig_big = QM_FD_FORMAT_LONG, | |
107 | qm_fd_sg = QM_FD_FORMAT_SG, | |
108 | qm_fd_sg_big = QM_FD_FORMAT_SG | QM_FD_FORMAT_LONG, | |
109 | qm_fd_compound = QM_FD_FORMAT_COMPOUND | |
110 | }; | |
111 | ||
112 | static inline dma_addr_t qm_fd_addr(const struct qm_fd *fd) | |
113 | { | |
114 | return be64_to_cpu(fd->data) & 0xffffffffffLLU; | |
115 | } | |
116 | ||
117 | static inline u64 qm_fd_addr_get64(const struct qm_fd *fd) | |
118 | { | |
119 | return be64_to_cpu(fd->data) & 0xffffffffffLLU; | |
120 | } | |
121 | ||
122 | static inline void qm_fd_addr_set64(struct qm_fd *fd, u64 addr) | |
123 | { | |
124 | fd->addr_hi = upper_32_bits(addr); | |
125 | fd->addr_lo = cpu_to_be32(lower_32_bits(addr)); | |
126 | } | |
127 | ||
128 | /* | |
129 | * The 'format' field indicates the interpretation of the remaining | |
130 | * 29 bits of the 32-bit word. | |
131 | * If 'format' is _contig or _sg, 20b length and 9b offset. | |
132 | * If 'format' is _contig_big or _sg_big, 29b length. | |
133 | * If 'format' is _compound, 29b "congestion weight". | |
134 | */ | |
135 | static inline enum qm_fd_format qm_fd_get_format(const struct qm_fd *fd) | |
136 | { | |
137 | return be32_to_cpu(fd->cfg) & QM_FD_FORMAT_MASK; | |
138 | } | |
139 | ||
140 | static inline int qm_fd_get_offset(const struct qm_fd *fd) | |
141 | { | |
142 | return (be32_to_cpu(fd->cfg) & QM_FD_OFF_MASK) >> QM_FD_OFF_SHIFT; | |
143 | } | |
144 | ||
145 | static inline int qm_fd_get_length(const struct qm_fd *fd) | |
146 | { | |
147 | return be32_to_cpu(fd->cfg) & QM_FD_LEN_MASK; | |
148 | } | |
149 | ||
150 | static inline int qm_fd_get_len_big(const struct qm_fd *fd) | |
151 | { | |
152 | return be32_to_cpu(fd->cfg) & QM_FD_LEN_BIG_MASK; | |
153 | } | |
154 | ||
155 | static inline void qm_fd_set_param(struct qm_fd *fd, enum qm_fd_format fmt, | |
156 | int off, int len) | |
157 | { | |
158 | fd->cfg = cpu_to_be32(fmt | (len & QM_FD_LEN_BIG_MASK) | | |
159 | ((off << QM_FD_OFF_SHIFT) & QM_FD_OFF_MASK)); | |
160 | } | |
161 | ||
162 | #define qm_fd_set_contig(fd, off, len) \ | |
163 | qm_fd_set_param(fd, qm_fd_contig, off, len) | |
164 | #define qm_fd_set_sg(fd, off, len) qm_fd_set_param(fd, qm_fd_sg, off, len) | |
165 | #define qm_fd_set_contig_big(fd, len) \ | |
166 | qm_fd_set_param(fd, qm_fd_contig_big, 0, len) | |
167 | #define qm_fd_set_sg_big(fd, len) qm_fd_set_param(fd, qm_fd_sg_big, 0, len) | |
168 | ||
169 | static inline void qm_fd_clear_fd(struct qm_fd *fd) | |
170 | { | |
171 | fd->data = 0; | |
172 | fd->cfg = 0; | |
173 | fd->cmd = 0; | |
174 | } | |
175 | ||
176 | /* Scatter/Gather table entry */ | |
177 | struct qm_sg_entry { | |
178 | union { | |
179 | struct { | |
180 | u8 __reserved1[3]; | |
181 | u8 addr_hi; /* high 8-bits of 40-bit address */ | |
182 | __be32 addr_lo; /* low 32-bits of 40-bit address */ | |
183 | }; | |
184 | __be64 data; | |
185 | }; | |
186 | __be32 cfg; /* E bit, F bit, length */ | |
187 | u8 __reserved2; | |
188 | u8 bpid; | |
189 | __be16 offset; /* 13-bit, _res[13-15]*/ | |
190 | } __packed; | |
191 | ||
192 | #define QM_SG_LEN_MASK GENMASK(29, 0) | |
193 | #define QM_SG_OFF_MASK GENMASK(12, 0) | |
194 | #define QM_SG_FIN BIT(30) | |
195 | #define QM_SG_EXT BIT(31) | |
196 | ||
197 | static inline dma_addr_t qm_sg_addr(const struct qm_sg_entry *sg) | |
198 | { | |
199 | return be64_to_cpu(sg->data) & 0xffffffffffLLU; | |
200 | } | |
201 | ||
202 | static inline u64 qm_sg_entry_get64(const struct qm_sg_entry *sg) | |
203 | { | |
204 | return be64_to_cpu(sg->data) & 0xffffffffffLLU; | |
205 | } | |
206 | ||
207 | static inline void qm_sg_entry_set64(struct qm_sg_entry *sg, u64 addr) | |
208 | { | |
209 | sg->addr_hi = upper_32_bits(addr); | |
210 | sg->addr_lo = cpu_to_be32(lower_32_bits(addr)); | |
211 | } | |
212 | ||
213 | static inline bool qm_sg_entry_is_final(const struct qm_sg_entry *sg) | |
214 | { | |
215 | return be32_to_cpu(sg->cfg) & QM_SG_FIN; | |
216 | } | |
217 | ||
218 | static inline bool qm_sg_entry_is_ext(const struct qm_sg_entry *sg) | |
219 | { | |
220 | return be32_to_cpu(sg->cfg) & QM_SG_EXT; | |
221 | } | |
222 | ||
223 | static inline int qm_sg_entry_get_len(const struct qm_sg_entry *sg) | |
224 | { | |
225 | return be32_to_cpu(sg->cfg) & QM_SG_LEN_MASK; | |
226 | } | |
227 | ||
228 | static inline void qm_sg_entry_set_len(struct qm_sg_entry *sg, int len) | |
229 | { | |
230 | sg->cfg = cpu_to_be32(len & QM_SG_LEN_MASK); | |
231 | } | |
232 | ||
233 | static inline void qm_sg_entry_set_f(struct qm_sg_entry *sg, int len) | |
234 | { | |
235 | sg->cfg = cpu_to_be32(QM_SG_FIN | (len & QM_SG_LEN_MASK)); | |
236 | } | |
237 | ||
238 | static inline int qm_sg_entry_get_off(const struct qm_sg_entry *sg) | |
239 | { | |
240 | return be32_to_cpu(sg->offset) & QM_SG_OFF_MASK; | |
241 | } | |
242 | ||
243 | /* "Frame Dequeue Response" */ | |
244 | struct qm_dqrr_entry { | |
245 | u8 verb; | |
246 | u8 stat; | |
247 | u16 seqnum; /* 15-bit */ | |
248 | u8 tok; | |
249 | u8 __reserved2[3]; | |
250 | u32 fqid; /* 24-bit */ | |
efe848cd | 251 | u32 context_b; |
c535e923 CM |
252 | struct qm_fd fd; |
253 | u8 __reserved4[32]; | |
254 | } __packed; | |
255 | #define QM_DQRR_VERB_VBIT 0x80 | |
256 | #define QM_DQRR_VERB_MASK 0x7f /* where the verb contains; */ | |
257 | #define QM_DQRR_VERB_FRAME_DEQUEUE 0x60 /* "this format" */ | |
258 | #define QM_DQRR_STAT_FQ_EMPTY 0x80 /* FQ empty */ | |
259 | #define QM_DQRR_STAT_FQ_HELDACTIVE 0x40 /* FQ held active */ | |
260 | #define QM_DQRR_STAT_FQ_FORCEELIGIBLE 0x20 /* FQ was force-eligible'd */ | |
261 | #define QM_DQRR_STAT_FD_VALID 0x10 /* has a non-NULL FD */ | |
262 | #define QM_DQRR_STAT_UNSCHEDULED 0x02 /* Unscheduled dequeue */ | |
263 | #define QM_DQRR_STAT_DQCR_EXPIRED 0x01 /* VDQCR or PDQCR expired*/ | |
264 | ||
d6753c7e CM |
265 | /* 'fqid' is a 24-bit field in every h/w descriptor */ |
266 | #define QM_FQID_MASK GENMASK(23, 0) | |
267 | #define qm_fqid_set(p, v) ((p)->fqid = ((v) & QM_FQID_MASK)) | |
268 | #define qm_fqid_get(p) ((p)->fqid & QM_FQID_MASK) | |
269 | ||
c535e923 CM |
270 | /* "ERN Message Response" */ |
271 | /* "FQ State Change Notification" */ | |
272 | union qm_mr_entry { | |
273 | struct { | |
274 | u8 verb; | |
275 | u8 __reserved[63]; | |
276 | }; | |
277 | struct { | |
278 | u8 verb; | |
279 | u8 dca; | |
280 | u16 seqnum; | |
281 | u8 rc; /* Rej Code: 8-bit */ | |
b5399452 | 282 | u8 __reserved[3]; |
c535e923 CM |
283 | u32 fqid; /* 24-bit */ |
284 | u32 tag; | |
285 | struct qm_fd fd; | |
286 | u8 __reserved1[32]; | |
287 | } __packed ern; | |
288 | struct { | |
289 | u8 verb; | |
290 | u8 fqs; /* Frame Queue Status */ | |
291 | u8 __reserved1[6]; | |
292 | u32 fqid; /* 24-bit */ | |
efe848cd | 293 | u32 context_b; |
c535e923 CM |
294 | u8 __reserved2[48]; |
295 | } __packed fq; /* FQRN/FQRNI/FQRL/FQPN */ | |
296 | }; | |
297 | #define QM_MR_VERB_VBIT 0x80 | |
298 | /* | |
299 | * ERNs originating from direct-connect portals ("dcern") use 0x20 as a verb | |
300 | * which would be invalid as a s/w enqueue verb. A s/w ERN can be distinguished | |
301 | * from the other MR types by noting if the 0x20 bit is unset. | |
302 | */ | |
303 | #define QM_MR_VERB_TYPE_MASK 0x27 | |
304 | #define QM_MR_VERB_DC_ERN 0x20 | |
305 | #define QM_MR_VERB_FQRN 0x21 | |
306 | #define QM_MR_VERB_FQRNI 0x22 | |
307 | #define QM_MR_VERB_FQRL 0x23 | |
308 | #define QM_MR_VERB_FQPN 0x24 | |
309 | #define QM_MR_RC_MASK 0xf0 /* contains one of; */ | |
310 | #define QM_MR_RC_CGR_TAILDROP 0x00 | |
311 | #define QM_MR_RC_WRED 0x10 | |
312 | #define QM_MR_RC_ERROR 0x20 | |
313 | #define QM_MR_RC_ORPWINDOW_EARLY 0x30 | |
314 | #define QM_MR_RC_ORPWINDOW_LATE 0x40 | |
315 | #define QM_MR_RC_FQ_TAILDROP 0x50 | |
316 | #define QM_MR_RC_ORPWINDOW_RETIRED 0x60 | |
317 | #define QM_MR_RC_ORP_ZERO 0x70 | |
318 | #define QM_MR_FQS_ORLPRESENT 0x02 /* ORL fragments to come */ | |
319 | #define QM_MR_FQS_NOTEMPTY 0x01 /* FQ has enqueued frames */ | |
320 | ||
321 | /* | |
322 | * An identical structure of FQD fields is present in the "Init FQ" command and | |
323 | * the "Query FQ" result, it's suctioned out into the "struct qm_fqd" type. | |
324 | * Within that, the 'stashing' and 'taildrop' pieces are also factored out, the | |
325 | * latter has two inlines to assist with converting to/from the mant+exp | |
326 | * representation. | |
327 | */ | |
328 | struct qm_fqd_stashing { | |
329 | /* See QM_STASHING_EXCL_<...> */ | |
330 | u8 exclusive; | |
331 | /* Numbers of cachelines */ | |
332 | u8 cl; /* _res[6-7], as[4-5], ds[2-3], cs[0-1] */ | |
333 | }; | |
334 | ||
335 | struct qm_fqd_oac { | |
336 | /* "Overhead Accounting Control", see QM_OAC_<...> */ | |
337 | u8 oac; /* oac[6-7], _res[0-5] */ | |
338 | /* Two's-complement value (-128 to +127) */ | |
339 | s8 oal; /* "Overhead Accounting Length" */ | |
340 | }; | |
341 | ||
342 | struct qm_fqd { | |
343 | /* _res[6-7], orprws[3-5], oa[2], olws[0-1] */ | |
344 | u8 orpc; | |
345 | u8 cgid; | |
346 | __be16 fq_ctrl; /* See QM_FQCTRL_<...> */ | |
347 | __be16 dest_wq; /* channel[3-15], wq[0-2] */ | |
348 | __be16 ics_cred; /* 15-bit */ | |
349 | /* | |
350 | * For "Initialize Frame Queue" commands, the write-enable mask | |
351 | * determines whether 'td' or 'oac_init' is observed. For query | |
352 | * commands, this field is always 'td', and 'oac_query' (below) reflects | |
353 | * the Overhead ACcounting values. | |
354 | */ | |
355 | union { | |
356 | __be16 td; /* "Taildrop": _res[13-15], mant[5-12], exp[0-4] */ | |
357 | struct qm_fqd_oac oac_init; | |
358 | }; | |
359 | __be32 context_b; | |
360 | union { | |
361 | /* Treat it as 64-bit opaque */ | |
362 | __be64 opaque; | |
363 | struct { | |
364 | __be32 hi; | |
365 | __be32 lo; | |
366 | }; | |
367 | /* Treat it as s/w portal stashing config */ | |
368 | /* see "FQD Context_A field used for [...]" */ | |
369 | struct { | |
370 | struct qm_fqd_stashing stashing; | |
371 | /* | |
372 | * 48-bit address of FQ context to | |
373 | * stash, must be cacheline-aligned | |
374 | */ | |
375 | __be16 context_hi; | |
376 | __be32 context_lo; | |
377 | } __packed; | |
378 | } context_a; | |
379 | struct qm_fqd_oac oac_query; | |
380 | } __packed; | |
381 | ||
382 | #define QM_FQD_CHAN_OFF 3 | |
383 | #define QM_FQD_WQ_MASK GENMASK(2, 0) | |
384 | #define QM_FQD_TD_EXP_MASK GENMASK(4, 0) | |
385 | #define QM_FQD_TD_MANT_OFF 5 | |
386 | #define QM_FQD_TD_MANT_MASK GENMASK(12, 5) | |
387 | #define QM_FQD_TD_MAX 0xe0000000 | |
388 | #define QM_FQD_TD_MANT_MAX 0xff | |
389 | #define QM_FQD_OAC_OFF 6 | |
390 | #define QM_FQD_AS_OFF 4 | |
391 | #define QM_FQD_DS_OFF 2 | |
392 | #define QM_FQD_XS_MASK 0x3 | |
393 | ||
394 | /* 64-bit converters for context_hi/lo */ | |
395 | static inline u64 qm_fqd_stashing_get64(const struct qm_fqd *fqd) | |
396 | { | |
397 | return be64_to_cpu(fqd->context_a.opaque) & 0xffffffffffffULL; | |
398 | } | |
399 | ||
400 | static inline dma_addr_t qm_fqd_stashing_addr(const struct qm_fqd *fqd) | |
401 | { | |
402 | return be64_to_cpu(fqd->context_a.opaque) & 0xffffffffffffULL; | |
403 | } | |
404 | ||
405 | static inline u64 qm_fqd_context_a_get64(const struct qm_fqd *fqd) | |
406 | { | |
407 | return qm_fqd_stashing_get64(fqd); | |
408 | } | |
409 | ||
410 | static inline void qm_fqd_stashing_set64(struct qm_fqd *fqd, u64 addr) | |
411 | { | |
412 | fqd->context_a.context_hi = upper_32_bits(addr); | |
413 | fqd->context_a.context_lo = lower_32_bits(addr); | |
414 | } | |
415 | ||
416 | static inline void qm_fqd_context_a_set64(struct qm_fqd *fqd, u64 addr) | |
417 | { | |
9f3670e8 | 418 | fqd->context_a.hi = cpu_to_be32(upper_32_bits(addr)); |
c535e923 CM |
419 | fqd->context_a.lo = cpu_to_be32(lower_32_bits(addr)); |
420 | } | |
421 | ||
422 | /* convert a threshold value into mant+exp representation */ | |
423 | static inline int qm_fqd_set_taildrop(struct qm_fqd *fqd, u32 val, | |
424 | int roundup) | |
425 | { | |
426 | u32 e = 0; | |
427 | int td, oddbit = 0; | |
428 | ||
429 | if (val > QM_FQD_TD_MAX) | |
430 | return -ERANGE; | |
431 | ||
432 | while (val > QM_FQD_TD_MANT_MAX) { | |
433 | oddbit = val & 1; | |
434 | val >>= 1; | |
435 | e++; | |
436 | if (roundup && oddbit) | |
437 | val++; | |
438 | } | |
439 | ||
440 | td = (val << QM_FQD_TD_MANT_OFF) & QM_FQD_TD_MANT_MASK; | |
441 | td |= (e & QM_FQD_TD_EXP_MASK); | |
442 | fqd->td = cpu_to_be16(td); | |
443 | return 0; | |
444 | } | |
445 | /* and the other direction */ | |
446 | static inline int qm_fqd_get_taildrop(const struct qm_fqd *fqd) | |
447 | { | |
448 | int td = be16_to_cpu(fqd->td); | |
449 | ||
450 | return ((td & QM_FQD_TD_MANT_MASK) >> QM_FQD_TD_MANT_OFF) | |
451 | << (td & QM_FQD_TD_EXP_MASK); | |
452 | } | |
453 | ||
454 | static inline void qm_fqd_set_stashing(struct qm_fqd *fqd, u8 as, u8 ds, u8 cs) | |
455 | { | |
456 | struct qm_fqd_stashing *st = &fqd->context_a.stashing; | |
457 | ||
458 | st->cl = ((as & QM_FQD_XS_MASK) << QM_FQD_AS_OFF) | | |
459 | ((ds & QM_FQD_XS_MASK) << QM_FQD_DS_OFF) | | |
460 | (cs & QM_FQD_XS_MASK); | |
461 | } | |
462 | ||
463 | static inline u8 qm_fqd_get_stashing(const struct qm_fqd *fqd) | |
464 | { | |
465 | return fqd->context_a.stashing.cl; | |
466 | } | |
467 | ||
468 | static inline void qm_fqd_set_oac(struct qm_fqd *fqd, u8 val) | |
469 | { | |
470 | fqd->oac_init.oac = val << QM_FQD_OAC_OFF; | |
471 | } | |
472 | ||
473 | static inline void qm_fqd_set_oal(struct qm_fqd *fqd, s8 val) | |
474 | { | |
475 | fqd->oac_init.oal = val; | |
476 | } | |
477 | ||
478 | static inline void qm_fqd_set_destwq(struct qm_fqd *fqd, int ch, int wq) | |
479 | { | |
480 | fqd->dest_wq = cpu_to_be16((ch << QM_FQD_CHAN_OFF) | | |
481 | (wq & QM_FQD_WQ_MASK)); | |
482 | } | |
483 | ||
484 | static inline int qm_fqd_get_chan(const struct qm_fqd *fqd) | |
485 | { | |
486 | return be16_to_cpu(fqd->dest_wq) >> QM_FQD_CHAN_OFF; | |
487 | } | |
488 | ||
489 | static inline int qm_fqd_get_wq(const struct qm_fqd *fqd) | |
490 | { | |
491 | return be16_to_cpu(fqd->dest_wq) & QM_FQD_WQ_MASK; | |
492 | } | |
493 | ||
494 | /* See "Frame Queue Descriptor (FQD)" */ | |
495 | /* Frame Queue Descriptor (FQD) field 'fq_ctrl' uses these constants */ | |
496 | #define QM_FQCTRL_MASK 0x07ff /* 'fq_ctrl' flags; */ | |
497 | #define QM_FQCTRL_CGE 0x0400 /* Congestion Group Enable */ | |
498 | #define QM_FQCTRL_TDE 0x0200 /* Tail-Drop Enable */ | |
499 | #define QM_FQCTRL_CTXASTASHING 0x0080 /* Context-A stashing */ | |
500 | #define QM_FQCTRL_CPCSTASH 0x0040 /* CPC Stash Enable */ | |
501 | #define QM_FQCTRL_FORCESFDR 0x0008 /* High-priority SFDRs */ | |
502 | #define QM_FQCTRL_AVOIDBLOCK 0x0004 /* Don't block active */ | |
503 | #define QM_FQCTRL_HOLDACTIVE 0x0002 /* Hold active in portal */ | |
504 | #define QM_FQCTRL_PREFERINCACHE 0x0001 /* Aggressively cache FQD */ | |
505 | #define QM_FQCTRL_LOCKINCACHE QM_FQCTRL_PREFERINCACHE /* older naming */ | |
506 | ||
507 | /* See "FQD Context_A field used for [...] */ | |
508 | /* Frame Queue Descriptor (FQD) field 'CONTEXT_A' uses these constants */ | |
509 | #define QM_STASHING_EXCL_ANNOTATION 0x04 | |
510 | #define QM_STASHING_EXCL_DATA 0x02 | |
511 | #define QM_STASHING_EXCL_CTX 0x01 | |
512 | ||
513 | /* See "Intra Class Scheduling" */ | |
514 | /* FQD field 'OAC' (Overhead ACcounting) uses these constants */ | |
515 | #define QM_OAC_ICS 0x2 /* Accounting for Intra-Class Scheduling */ | |
516 | #define QM_OAC_CG 0x1 /* Accounting for Congestion Groups */ | |
517 | ||
518 | /* | |
519 | * This struct represents the 32-bit "WR_PARM_[GYR]" parameters in CGR fields | |
520 | * and associated commands/responses. The WRED parameters are calculated from | |
521 | * these fields as follows; | |
522 | * MaxTH = MA * (2 ^ Mn) | |
523 | * Slope = SA / (2 ^ Sn) | |
524 | * MaxP = 4 * (Pn + 1) | |
525 | */ | |
526 | struct qm_cgr_wr_parm { | |
527 | /* MA[24-31], Mn[19-23], SA[12-18], Sn[6-11], Pn[0-5] */ | |
528 | u32 word; | |
529 | }; | |
530 | /* | |
531 | * This struct represents the 13-bit "CS_THRES" CGR field. In the corresponding | |
532 | * management commands, this is padded to a 16-bit structure field, so that's | |
533 | * how we represent it here. The congestion state threshold is calculated from | |
534 | * these fields as follows; | |
535 | * CS threshold = TA * (2 ^ Tn) | |
536 | */ | |
537 | struct qm_cgr_cs_thres { | |
538 | /* _res[13-15], TA[5-12], Tn[0-4] */ | |
539 | u16 word; | |
540 | }; | |
541 | /* | |
542 | * This identical structure of CGR fields is present in the "Init/Modify CGR" | |
543 | * commands and the "Query CGR" result. It's suctioned out here into its own | |
544 | * struct. | |
545 | */ | |
546 | struct __qm_mc_cgr { | |
547 | struct qm_cgr_wr_parm wr_parm_g; | |
548 | struct qm_cgr_wr_parm wr_parm_y; | |
549 | struct qm_cgr_wr_parm wr_parm_r; | |
550 | u8 wr_en_g; /* boolean, use QM_CGR_EN */ | |
551 | u8 wr_en_y; /* boolean, use QM_CGR_EN */ | |
552 | u8 wr_en_r; /* boolean, use QM_CGR_EN */ | |
553 | u8 cscn_en; /* boolean, use QM_CGR_EN */ | |
554 | union { | |
555 | struct { | |
496bfa11 CM |
556 | u16 cscn_targ_upd_ctrl; /* use QM_CGR_TARG_UDP_* */ |
557 | u16 cscn_targ_dcp_low; | |
c535e923 CM |
558 | }; |
559 | u32 cscn_targ; /* use QM_CGR_TARG_* */ | |
560 | }; | |
561 | u8 cstd_en; /* boolean, use QM_CGR_EN */ | |
562 | u8 cs; /* boolean, only used in query response */ | |
563 | struct qm_cgr_cs_thres cs_thres; /* use qm_cgr_cs_thres_set64() */ | |
564 | u8 mode; /* QMAN_CGR_MODE_FRAME not supported in rev1.0 */ | |
565 | } __packed; | |
566 | #define QM_CGR_EN 0x01 /* For wr_en_*, cscn_en, cstd_en */ | |
567 | #define QM_CGR_TARG_UDP_CTRL_WRITE_BIT 0x8000 /* value written to portal bit*/ | |
568 | #define QM_CGR_TARG_UDP_CTRL_DCP 0x4000 /* 0: SWP, 1: DCP */ | |
569 | #define QM_CGR_TARG_PORTAL(n) (0x80000000 >> (n)) /* s/w portal, 0-9 */ | |
570 | #define QM_CGR_TARG_FMAN0 0x00200000 /* direct-connect portal: fman0 */ | |
571 | #define QM_CGR_TARG_FMAN1 0x00100000 /* : fman1 */ | |
572 | /* Convert CGR thresholds to/from "cs_thres" format */ | |
573 | static inline u64 qm_cgr_cs_thres_get64(const struct qm_cgr_cs_thres *th) | |
574 | { | |
575 | return ((th->word >> 5) & 0xff) << (th->word & 0x1f); | |
576 | } | |
577 | ||
578 | static inline int qm_cgr_cs_thres_set64(struct qm_cgr_cs_thres *th, u64 val, | |
579 | int roundup) | |
580 | { | |
581 | u32 e = 0; | |
582 | int oddbit = 0; | |
583 | ||
584 | while (val > 0xff) { | |
585 | oddbit = val & 1; | |
586 | val >>= 1; | |
587 | e++; | |
588 | if (roundup && oddbit) | |
589 | val++; | |
590 | } | |
591 | th->word = ((val & 0xff) << 5) | (e & 0x1f); | |
592 | return 0; | |
593 | } | |
594 | ||
595 | /* "Initialize FQ" */ | |
596 | struct qm_mcc_initfq { | |
597 | u8 __reserved1[2]; | |
598 | u16 we_mask; /* Write Enable Mask */ | |
599 | u32 fqid; /* 24-bit */ | |
600 | u16 count; /* Initialises 'count+1' FQDs */ | |
601 | struct qm_fqd fqd; /* the FQD fields go here */ | |
602 | u8 __reserved2[30]; | |
603 | } __packed; | |
604 | /* "Initialize/Modify CGR" */ | |
605 | struct qm_mcc_initcgr { | |
606 | u8 __reserve1[2]; | |
607 | u16 we_mask; /* Write Enable Mask */ | |
608 | struct __qm_mc_cgr cgr; /* CGR fields */ | |
609 | u8 __reserved2[2]; | |
610 | u8 cgid; | |
611 | u8 __reserved3[32]; | |
612 | } __packed; | |
613 | ||
614 | /* INITFQ-specific flags */ | |
615 | #define QM_INITFQ_WE_MASK 0x01ff /* 'Write Enable' flags; */ | |
616 | #define QM_INITFQ_WE_OAC 0x0100 | |
617 | #define QM_INITFQ_WE_ORPC 0x0080 | |
618 | #define QM_INITFQ_WE_CGID 0x0040 | |
619 | #define QM_INITFQ_WE_FQCTRL 0x0020 | |
620 | #define QM_INITFQ_WE_DESTWQ 0x0010 | |
621 | #define QM_INITFQ_WE_ICSCRED 0x0008 | |
622 | #define QM_INITFQ_WE_TDTHRESH 0x0004 | |
623 | #define QM_INITFQ_WE_CONTEXTB 0x0002 | |
624 | #define QM_INITFQ_WE_CONTEXTA 0x0001 | |
625 | /* INITCGR/MODIFYCGR-specific flags */ | |
626 | #define QM_CGR_WE_MASK 0x07ff /* 'Write Enable Mask'; */ | |
627 | #define QM_CGR_WE_WR_PARM_G 0x0400 | |
628 | #define QM_CGR_WE_WR_PARM_Y 0x0200 | |
629 | #define QM_CGR_WE_WR_PARM_R 0x0100 | |
630 | #define QM_CGR_WE_WR_EN_G 0x0080 | |
631 | #define QM_CGR_WE_WR_EN_Y 0x0040 | |
632 | #define QM_CGR_WE_WR_EN_R 0x0020 | |
633 | #define QM_CGR_WE_CSCN_EN 0x0010 | |
634 | #define QM_CGR_WE_CSCN_TARG 0x0008 | |
635 | #define QM_CGR_WE_CSTD_EN 0x0004 | |
636 | #define QM_CGR_WE_CS_THRES 0x0002 | |
637 | #define QM_CGR_WE_MODE 0x0001 | |
638 | ||
639 | #define QMAN_CGR_FLAG_USE_INIT 0x00000001 | |
640 | ||
641 | /* Portal and Frame Queues */ | |
642 | /* Represents a managed portal */ | |
643 | struct qman_portal; | |
644 | ||
645 | /* | |
646 | * This object type represents QMan frame queue descriptors (FQD), it is | |
647 | * cacheline-aligned, and initialised by qman_create_fq(). The structure is | |
648 | * defined further down. | |
649 | */ | |
650 | struct qman_fq; | |
651 | ||
652 | /* | |
653 | * This object type represents a QMan congestion group, it is defined further | |
654 | * down. | |
655 | */ | |
656 | struct qman_cgr; | |
657 | ||
658 | /* | |
659 | * This enum, and the callback type that returns it, are used when handling | |
660 | * dequeued frames via DQRR. Note that for "null" callbacks registered with the | |
efe848cd | 661 | * portal object (for handling dequeues that do not demux because context_b is |
c535e923 CM |
662 | * NULL), the return value *MUST* be qman_cb_dqrr_consume. |
663 | */ | |
664 | enum qman_cb_dqrr_result { | |
665 | /* DQRR entry can be consumed */ | |
666 | qman_cb_dqrr_consume, | |
667 | /* Like _consume, but requests parking - FQ must be held-active */ | |
668 | qman_cb_dqrr_park, | |
669 | /* Does not consume, for DCA mode only. */ | |
670 | qman_cb_dqrr_defer, | |
671 | /* | |
672 | * Stop processing without consuming this ring entry. Exits the current | |
673 | * qman_p_poll_dqrr() or interrupt-handling, as appropriate. If within | |
674 | * an interrupt handler, the callback would typically call | |
675 | * qman_irqsource_remove(QM_PIRQ_DQRI) before returning this value, | |
676 | * otherwise the interrupt will reassert immediately. | |
677 | */ | |
678 | qman_cb_dqrr_stop, | |
679 | /* Like qman_cb_dqrr_stop, but consumes the current entry. */ | |
680 | qman_cb_dqrr_consume_stop | |
681 | }; | |
682 | typedef enum qman_cb_dqrr_result (*qman_cb_dqrr)(struct qman_portal *qm, | |
683 | struct qman_fq *fq, | |
684 | const struct qm_dqrr_entry *dqrr); | |
685 | ||
686 | /* | |
687 | * This callback type is used when handling ERNs, FQRNs and FQRLs via MR. They | |
688 | * are always consumed after the callback returns. | |
689 | */ | |
690 | typedef void (*qman_cb_mr)(struct qman_portal *qm, struct qman_fq *fq, | |
691 | const union qm_mr_entry *msg); | |
692 | ||
693 | /* | |
694 | * s/w-visible states. Ie. tentatively scheduled + truly scheduled + active + | |
695 | * held-active + held-suspended are just "sched". Things like "retired" will not | |
696 | * be assumed until it is complete (ie. QMAN_FQ_STATE_CHANGING is set until | |
697 | * then, to indicate it's completing and to gate attempts to retry the retire | |
698 | * command). Note, park commands do not set QMAN_FQ_STATE_CHANGING because it's | |
699 | * technically impossible in the case of enqueue DCAs (which refer to DQRR ring | |
700 | * index rather than the FQ that ring entry corresponds to), so repeated park | |
701 | * commands are allowed (if you're silly enough to try) but won't change FQ | |
702 | * state, and the resulting park notifications move FQs from "sched" to | |
703 | * "parked". | |
704 | */ | |
705 | enum qman_fq_state { | |
706 | qman_fq_state_oos, | |
707 | qman_fq_state_parked, | |
708 | qman_fq_state_sched, | |
709 | qman_fq_state_retired | |
710 | }; | |
711 | ||
712 | #define QMAN_FQ_STATE_CHANGING 0x80000000 /* 'state' is changing */ | |
713 | #define QMAN_FQ_STATE_NE 0x40000000 /* retired FQ isn't empty */ | |
714 | #define QMAN_FQ_STATE_ORL 0x20000000 /* retired FQ has ORL */ | |
715 | #define QMAN_FQ_STATE_BLOCKOOS 0xe0000000 /* if any are set, no OOS */ | |
716 | #define QMAN_FQ_STATE_CGR_EN 0x10000000 /* CGR enabled */ | |
717 | #define QMAN_FQ_STATE_VDQCR 0x08000000 /* being volatile dequeued */ | |
718 | ||
719 | /* | |
720 | * Frame queue objects (struct qman_fq) are stored within memory passed to | |
721 | * qman_create_fq(), as this allows stashing of caller-provided demux callback | |
722 | * pointers at no extra cost to stashing of (driver-internal) FQ state. If the | |
723 | * caller wishes to add per-FQ state and have it benefit from dequeue-stashing, | |
724 | * they should; | |
725 | * | |
726 | * (a) extend the qman_fq structure with their state; eg. | |
727 | * | |
728 | * // myfq is allocated and driver_fq callbacks filled in; | |
729 | * struct my_fq { | |
730 | * struct qman_fq base; | |
731 | * int an_extra_field; | |
732 | * [ ... add other fields to be associated with each FQ ...] | |
733 | * } *myfq = some_my_fq_allocator(); | |
734 | * struct qman_fq *fq = qman_create_fq(fqid, flags, &myfq->base); | |
735 | * | |
736 | * // in a dequeue callback, access extra fields from 'fq' via a cast; | |
737 | * struct my_fq *myfq = (struct my_fq *)fq; | |
738 | * do_something_with(myfq->an_extra_field); | |
739 | * [...] | |
740 | * | |
741 | * (b) when and if configuring the FQ for context stashing, specify how ever | |
742 | * many cachelines are required to stash 'struct my_fq', to accelerate not | |
743 | * only the QMan driver but the callback as well. | |
744 | */ | |
745 | ||
746 | struct qman_fq_cb { | |
747 | qman_cb_dqrr dqrr; /* for dequeued frames */ | |
748 | qman_cb_mr ern; /* for s/w ERNs */ | |
749 | qman_cb_mr fqs; /* frame-queue state changes*/ | |
750 | }; | |
751 | ||
752 | struct qman_fq { | |
753 | /* Caller of qman_create_fq() provides these demux callbacks */ | |
754 | struct qman_fq_cb cb; | |
755 | /* | |
756 | * These are internal to the driver, don't touch. In particular, they | |
757 | * may change, be removed, or extended (so you shouldn't rely on | |
758 | * sizeof(qman_fq) being a constant). | |
759 | */ | |
760 | u32 fqid, idx; | |
761 | unsigned long flags; | |
762 | enum qman_fq_state state; | |
763 | int cgr_groupid; | |
764 | }; | |
765 | ||
766 | /* | |
767 | * This callback type is used when handling congestion group entry/exit. | |
768 | * 'congested' is non-zero on congestion-entry, and zero on congestion-exit. | |
769 | */ | |
770 | typedef void (*qman_cb_cgr)(struct qman_portal *qm, | |
771 | struct qman_cgr *cgr, int congested); | |
772 | ||
773 | struct qman_cgr { | |
774 | /* Set these prior to qman_create_cgr() */ | |
775 | u32 cgrid; /* 0..255, but u32 to allow specials like -1, 256, etc.*/ | |
776 | qman_cb_cgr cb; | |
777 | /* These are private to the driver */ | |
778 | u16 chan; /* portal channel this object is created on */ | |
779 | struct list_head node; | |
780 | }; | |
781 | ||
782 | /* Flags to qman_create_fq() */ | |
783 | #define QMAN_FQ_FLAG_NO_ENQUEUE 0x00000001 /* can't enqueue */ | |
784 | #define QMAN_FQ_FLAG_NO_MODIFY 0x00000002 /* can only enqueue */ | |
785 | #define QMAN_FQ_FLAG_TO_DCPORTAL 0x00000004 /* consumed by CAAM/PME/Fman */ | |
786 | #define QMAN_FQ_FLAG_DYNAMIC_FQID 0x00000020 /* (de)allocate fqid */ | |
787 | ||
788 | /* Flags to qman_init_fq() */ | |
789 | #define QMAN_INITFQ_FLAG_SCHED 0x00000001 /* schedule rather than park */ | |
790 | #define QMAN_INITFQ_FLAG_LOCAL 0x00000004 /* set dest portal */ | |
791 | ||
792 | /* Portal Management */ | |
793 | /** | |
794 | * qman_p_irqsource_add - add processing sources to be interrupt-driven | |
795 | * @bits: bitmask of QM_PIRQ_**I processing sources | |
796 | * | |
797 | * Adds processing sources that should be interrupt-driven (rather than | |
798 | * processed via qman_poll_***() functions). | |
799 | */ | |
800 | void qman_p_irqsource_add(struct qman_portal *p, u32 bits); | |
801 | ||
802 | /** | |
803 | * qman_p_irqsource_remove - remove processing sources from being int-driven | |
804 | * @bits: bitmask of QM_PIRQ_**I processing sources | |
805 | * | |
806 | * Removes processing sources from being interrupt-driven, so that they will | |
807 | * instead be processed via qman_poll_***() functions. | |
808 | */ | |
809 | void qman_p_irqsource_remove(struct qman_portal *p, u32 bits); | |
810 | ||
811 | /** | |
812 | * qman_affine_cpus - return a mask of cpus that have affine portals | |
813 | */ | |
814 | const cpumask_t *qman_affine_cpus(void); | |
815 | ||
816 | /** | |
817 | * qman_affine_channel - return the channel ID of an portal | |
818 | * @cpu: the cpu whose affine portal is the subject of the query | |
819 | * | |
820 | * If @cpu is -1, the affine portal for the current CPU will be used. It is a | |
821 | * bug to call this function for any value of @cpu (other than -1) that is not a | |
822 | * member of the mask returned from qman_affine_cpus(). | |
823 | */ | |
824 | u16 qman_affine_channel(int cpu); | |
825 | ||
826 | /** | |
827 | * qman_get_affine_portal - return the portal pointer affine to cpu | |
828 | * @cpu: the cpu whose affine portal is the subject of the query | |
829 | */ | |
830 | struct qman_portal *qman_get_affine_portal(int cpu); | |
831 | ||
832 | /** | |
833 | * qman_p_poll_dqrr - process DQRR (fast-path) entries | |
834 | * @limit: the maximum number of DQRR entries to process | |
835 | * | |
836 | * Use of this function requires that DQRR processing not be interrupt-driven. | |
837 | * The return value represents the number of DQRR entries processed. | |
838 | */ | |
839 | int qman_p_poll_dqrr(struct qman_portal *p, unsigned int limit); | |
840 | ||
841 | /** | |
842 | * qman_p_static_dequeue_add - Add pool channels to the portal SDQCR | |
843 | * @pools: bit-mask of pool channels, using QM_SDQCR_CHANNELS_POOL(n) | |
844 | * | |
845 | * Adds a set of pool channels to the portal's static dequeue command register | |
846 | * (SDQCR). The requested pools are limited to those the portal has dequeue | |
847 | * access to. | |
848 | */ | |
849 | void qman_p_static_dequeue_add(struct qman_portal *p, u32 pools); | |
850 | ||
851 | /* FQ management */ | |
852 | /** | |
853 | * qman_create_fq - Allocates a FQ | |
854 | * @fqid: the index of the FQD to encapsulate, must be "Out of Service" | |
855 | * @flags: bit-mask of QMAN_FQ_FLAG_*** options | |
856 | * @fq: memory for storing the 'fq', with callbacks filled in | |
857 | * | |
858 | * Creates a frame queue object for the given @fqid, unless the | |
859 | * QMAN_FQ_FLAG_DYNAMIC_FQID flag is set in @flags, in which case a FQID is | |
860 | * dynamically allocated (or the function fails if none are available). Once | |
861 | * created, the caller should not touch the memory at 'fq' except as extended to | |
862 | * adjacent memory for user-defined fields (see the definition of "struct | |
863 | * qman_fq" for more info). NO_MODIFY is only intended for enqueuing to | |
864 | * pre-existing frame-queues that aren't to be otherwise interfered with, it | |
865 | * prevents all other modifications to the frame queue. The TO_DCPORTAL flag | |
efe848cd | 866 | * causes the driver to honour any context_b modifications requested in the |
c535e923 CM |
867 | * qm_init_fq() API, as this indicates the frame queue will be consumed by a |
868 | * direct-connect portal (PME, CAAM, or Fman). When frame queues are consumed by | |
efe848cd CM |
869 | * software portals, the context_b field is controlled by the driver and can't |
870 | * be modified by the caller. | |
c535e923 CM |
871 | */ |
872 | int qman_create_fq(u32 fqid, u32 flags, struct qman_fq *fq); | |
873 | ||
874 | /** | |
875 | * qman_destroy_fq - Deallocates a FQ | |
876 | * @fq: the frame queue object to release | |
877 | * | |
878 | * The memory for this frame queue object ('fq' provided in qman_create_fq()) is | |
879 | * not deallocated but the caller regains ownership, to do with as desired. The | |
880 | * FQ must be in the 'out-of-service' or in the 'parked' state. | |
881 | */ | |
882 | void qman_destroy_fq(struct qman_fq *fq); | |
883 | ||
884 | /** | |
885 | * qman_fq_fqid - Queries the frame queue ID of a FQ object | |
886 | * @fq: the frame queue object to query | |
887 | */ | |
888 | u32 qman_fq_fqid(struct qman_fq *fq); | |
889 | ||
890 | /** | |
891 | * qman_init_fq - Initialises FQ fields, leaves the FQ "parked" or "scheduled" | |
892 | * @fq: the frame queue object to modify, must be 'parked' or new. | |
893 | * @flags: bit-mask of QMAN_INITFQ_FLAG_*** options | |
894 | * @opts: the FQ-modification settings, as defined in the low-level API | |
895 | * | |
896 | * The @opts parameter comes from the low-level portal API. Select | |
897 | * QMAN_INITFQ_FLAG_SCHED in @flags to cause the frame queue to be scheduled | |
898 | * rather than parked. NB, @opts can be NULL. | |
899 | * | |
900 | * Note that some fields and options within @opts may be ignored or overwritten | |
901 | * by the driver; | |
902 | * 1. the 'count' and 'fqid' fields are always ignored (this operation only | |
903 | * affects one frame queue: @fq). | |
904 | * 2. the QM_INITFQ_WE_CONTEXTB option of the 'we_mask' field and the associated | |
905 | * 'fqd' structure's 'context_b' field are sometimes overwritten; | |
906 | * - if @fq was not created with QMAN_FQ_FLAG_TO_DCPORTAL, then context_b is | |
907 | * initialised to a value used by the driver for demux. | |
908 | * - if context_b is initialised for demux, so is context_a in case stashing | |
909 | * is requested (see item 4). | |
910 | * (So caller control of context_b is only possible for TO_DCPORTAL frame queue | |
911 | * objects.) | |
912 | * 3. if @flags contains QMAN_INITFQ_FLAG_LOCAL, the 'fqd' structure's | |
913 | * 'dest::channel' field will be overwritten to match the portal used to issue | |
914 | * the command. If the WE_DESTWQ write-enable bit had already been set by the | |
915 | * caller, the channel workqueue will be left as-is, otherwise the write-enable | |
916 | * bit is set and the workqueue is set to a default of 4. If the "LOCAL" flag | |
917 | * isn't set, the destination channel/workqueue fields and the write-enable bit | |
918 | * are left as-is. | |
919 | * 4. if the driver overwrites context_a/b for demux, then if | |
920 | * QM_INITFQ_WE_CONTEXTA is set, the driver will only overwrite | |
921 | * context_a.address fields and will leave the stashing fields provided by the | |
922 | * user alone, otherwise it will zero out the context_a.stashing fields. | |
923 | */ | |
924 | int qman_init_fq(struct qman_fq *fq, u32 flags, struct qm_mcc_initfq *opts); | |
925 | ||
926 | /** | |
927 | * qman_schedule_fq - Schedules a FQ | |
928 | * @fq: the frame queue object to schedule, must be 'parked' | |
929 | * | |
930 | * Schedules the frame queue, which must be Parked, which takes it to | |
931 | * Tentatively-Scheduled or Truly-Scheduled depending on its fill-level. | |
932 | */ | |
933 | int qman_schedule_fq(struct qman_fq *fq); | |
934 | ||
935 | /** | |
936 | * qman_retire_fq - Retires a FQ | |
937 | * @fq: the frame queue object to retire | |
938 | * @flags: FQ flags (QMAN_FQ_STATE*) if retirement completes immediately | |
939 | * | |
940 | * Retires the frame queue. This returns zero if it succeeds immediately, +1 if | |
941 | * the retirement was started asynchronously, otherwise it returns negative for | |
942 | * failure. When this function returns zero, @flags is set to indicate whether | |
943 | * the retired FQ is empty and/or whether it has any ORL fragments (to show up | |
944 | * as ERNs). Otherwise the corresponding flags will be known when a subsequent | |
945 | * FQRN message shows up on the portal's message ring. | |
946 | * | |
947 | * NB, if the retirement is asynchronous (the FQ was in the Truly Scheduled or | |
948 | * Active state), the completion will be via the message ring as a FQRN - but | |
949 | * the corresponding callback may occur before this function returns!! Ie. the | |
950 | * caller should be prepared to accept the callback as the function is called, | |
951 | * not only once it has returned. | |
952 | */ | |
953 | int qman_retire_fq(struct qman_fq *fq, u32 *flags); | |
954 | ||
955 | /** | |
956 | * qman_oos_fq - Puts a FQ "out of service" | |
957 | * @fq: the frame queue object to be put out-of-service, must be 'retired' | |
958 | * | |
959 | * The frame queue must be retired and empty, and if any order restoration list | |
960 | * was released as ERNs at the time of retirement, they must all be consumed. | |
961 | */ | |
962 | int qman_oos_fq(struct qman_fq *fq); | |
963 | ||
964 | /** | |
965 | * qman_enqueue - Enqueue a frame to a frame queue | |
966 | * @fq: the frame queue object to enqueue to | |
967 | * @fd: a descriptor of the frame to be enqueued | |
968 | * | |
969 | * Fills an entry in the EQCR of portal @qm to enqueue the frame described by | |
970 | * @fd. The descriptor details are copied from @fd to the EQCR entry, the 'pid' | |
971 | * field is ignored. The return value is non-zero on error, such as ring full. | |
972 | */ | |
973 | int qman_enqueue(struct qman_fq *fq, const struct qm_fd *fd); | |
974 | ||
975 | /** | |
976 | * qman_alloc_fqid_range - Allocate a contiguous range of FQIDs | |
977 | * @result: is set by the API to the base FQID of the allocated range | |
978 | * @count: the number of FQIDs required | |
979 | * | |
980 | * Returns 0 on success, or a negative error code. | |
981 | */ | |
982 | int qman_alloc_fqid_range(u32 *result, u32 count); | |
983 | #define qman_alloc_fqid(result) qman_alloc_fqid_range(result, 1) | |
984 | ||
985 | /** | |
986 | * qman_release_fqid - Release the specified frame queue ID | |
987 | * @fqid: the FQID to be released back to the resource pool | |
988 | * | |
989 | * This function can also be used to seed the allocator with | |
990 | * FQID ranges that it can subsequently allocate from. | |
991 | * Returns 0 on success, or a negative error code. | |
992 | */ | |
993 | int qman_release_fqid(u32 fqid); | |
994 | ||
995 | /* Pool-channel management */ | |
996 | /** | |
997 | * qman_alloc_pool_range - Allocate a contiguous range of pool-channel IDs | |
998 | * @result: is set by the API to the base pool-channel ID of the allocated range | |
999 | * @count: the number of pool-channel IDs required | |
1000 | * | |
1001 | * Returns 0 on success, or a negative error code. | |
1002 | */ | |
1003 | int qman_alloc_pool_range(u32 *result, u32 count); | |
1004 | #define qman_alloc_pool(result) qman_alloc_pool_range(result, 1) | |
1005 | ||
1006 | /** | |
1007 | * qman_release_pool - Release the specified pool-channel ID | |
1008 | * @id: the pool-chan ID to be released back to the resource pool | |
1009 | * | |
1010 | * This function can also be used to seed the allocator with | |
1011 | * pool-channel ID ranges that it can subsequently allocate from. | |
1012 | * Returns 0 on success, or a negative error code. | |
1013 | */ | |
1014 | int qman_release_pool(u32 id); | |
1015 | ||
1016 | /* CGR management */ | |
1017 | /** | |
1018 | * qman_create_cgr - Register a congestion group object | |
1019 | * @cgr: the 'cgr' object, with fields filled in | |
1020 | * @flags: QMAN_CGR_FLAG_* values | |
1021 | * @opts: optional state of CGR settings | |
1022 | * | |
1023 | * Registers this object to receiving congestion entry/exit callbacks on the | |
1024 | * portal affine to the cpu portal on which this API is executed. If opts is | |
1025 | * NULL then only the callback (cgr->cb) function is registered. If @flags | |
1026 | * contains QMAN_CGR_FLAG_USE_INIT, then an init hw command (which will reset | |
1027 | * any unspecified parameters) will be used rather than a modify hw hardware | |
1028 | * (which only modifies the specified parameters). | |
1029 | */ | |
1030 | int qman_create_cgr(struct qman_cgr *cgr, u32 flags, | |
1031 | struct qm_mcc_initcgr *opts); | |
1032 | ||
1033 | /** | |
1034 | * qman_delete_cgr - Deregisters a congestion group object | |
1035 | * @cgr: the 'cgr' object to deregister | |
1036 | * | |
1037 | * "Unplugs" this CGR object from the portal affine to the cpu on which this API | |
1038 | * is executed. This must be excuted on the same affine portal on which it was | |
1039 | * created. | |
1040 | */ | |
1041 | int qman_delete_cgr(struct qman_cgr *cgr); | |
1042 | ||
1043 | /** | |
1044 | * qman_delete_cgr_safe - Deregisters a congestion group object from any CPU | |
1045 | * @cgr: the 'cgr' object to deregister | |
1046 | * | |
1047 | * This will select the proper CPU and run there qman_delete_cgr(). | |
1048 | */ | |
1049 | void qman_delete_cgr_safe(struct qman_cgr *cgr); | |
1050 | ||
1051 | /** | |
1052 | * qman_query_cgr_congested - Queries CGR's congestion status | |
1053 | * @cgr: the 'cgr' object to query | |
1054 | * @result: returns 'cgr's congestion status, 1 (true) if congested | |
1055 | */ | |
1056 | int qman_query_cgr_congested(struct qman_cgr *cgr, bool *result); | |
1057 | ||
1058 | /** | |
1059 | * qman_alloc_cgrid_range - Allocate a contiguous range of CGR IDs | |
1060 | * @result: is set by the API to the base CGR ID of the allocated range | |
1061 | * @count: the number of CGR IDs required | |
1062 | * | |
1063 | * Returns 0 on success, or a negative error code. | |
1064 | */ | |
1065 | int qman_alloc_cgrid_range(u32 *result, u32 count); | |
1066 | #define qman_alloc_cgrid(result) qman_alloc_cgrid_range(result, 1) | |
1067 | ||
1068 | /** | |
1069 | * qman_release_cgrid - Release the specified CGR ID | |
1070 | * @id: the CGR ID to be released back to the resource pool | |
1071 | * | |
1072 | * This function can also be used to seed the allocator with | |
1073 | * CGR ID ranges that it can subsequently allocate from. | |
1074 | * Returns 0 on success, or a negative error code. | |
1075 | */ | |
1076 | int qman_release_cgrid(u32 id); | |
1077 | ||
1078 | #endif /* __FSL_QMAN_H */ |