[mirror_ubuntu-bionic-kernel.git] / include / soc / tegra / pmc.h

/*
 * Copyright (c) 2010 Google, Inc
 * Copyright (c) 2014 NVIDIA Corporation
 *
 * Author:
 *	Colin Cross <ccross@google.com>
 *
 * This software is licensed under the terms of the GNU General Public
 * License version 2, as published by the Free Software Foundation, and
 * may be copied, distributed, and modified under those terms.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 */

#ifndef __SOC_TEGRA_PMC_H__
#define __SOC_TEGRA_PMC_H__

#include <linux/reboot.h>

#include <soc/tegra/pm.h>

struct clk;
struct reset_control;

#ifdef CONFIG_PM_SLEEP
enum tegra_suspend_mode tegra_pmc_get_suspend_mode(void);
void tegra_pmc_set_suspend_mode(enum tegra_suspend_mode mode);
void tegra_pmc_enter_suspend_mode(enum tegra_suspend_mode mode);
#endif /* CONFIG_PM_SLEEP */

#ifdef CONFIG_SMP
bool tegra_pmc_cpu_is_powered(unsigned int cpuid);
int tegra_pmc_cpu_power_on(unsigned int cpuid);
int tegra_pmc_cpu_remove_clamping(unsigned int cpuid);
#endif /* CONFIG_SMP */

/*
 * powergate and I/O rail APIs
 */

#define TEGRA_POWERGATE_CPU	0
#define TEGRA_POWERGATE_3D	1
#define TEGRA_POWERGATE_VENC	2
#define TEGRA_POWERGATE_PCIE	3
#define TEGRA_POWERGATE_VDEC	4
#define TEGRA_POWERGATE_L2	5
#define TEGRA_POWERGATE_MPE	6
#define TEGRA_POWERGATE_HEG	7
#define TEGRA_POWERGATE_SATA	8
#define TEGRA_POWERGATE_CPU1	9
#define TEGRA_POWERGATE_CPU2	10
#define TEGRA_POWERGATE_CPU3	11
#define TEGRA_POWERGATE_CELP	12
#define TEGRA_POWERGATE_3D1	13
#define TEGRA_POWERGATE_CPU0	14
#define TEGRA_POWERGATE_C0NC	15
#define TEGRA_POWERGATE_C1NC	16
#define TEGRA_POWERGATE_SOR	17
#define TEGRA_POWERGATE_DIS	18
#define TEGRA_POWERGATE_DISB	19
#define TEGRA_POWERGATE_XUSBA	20
#define TEGRA_POWERGATE_XUSBB	21
#define TEGRA_POWERGATE_XUSBC	22
#define TEGRA_POWERGATE_VIC	23
#define TEGRA_POWERGATE_IRAM	24
#define TEGRA_POWERGATE_NVDEC	25
#define TEGRA_POWERGATE_NVJPG	26
#define TEGRA_POWERGATE_AUD	27
#define TEGRA_POWERGATE_DFD	28
#define TEGRA_POWERGATE_VE2	29
#define TEGRA_POWERGATE_MAX	TEGRA_POWERGATE_VE2

#define TEGRA_POWERGATE_3D0	TEGRA_POWERGATE_3D

#define TEGRA_IO_RAIL_CSIA	0
#define TEGRA_IO_RAIL_CSIB	1
#define TEGRA_IO_RAIL_DSI	2
#define TEGRA_IO_RAIL_MIPI_BIAS	3
#define TEGRA_IO_RAIL_PEX_BIAS	4
#define TEGRA_IO_RAIL_PEX_CLK1	5
#define TEGRA_IO_RAIL_PEX_CLK2	6
#define TEGRA_IO_RAIL_USB0	9
#define TEGRA_IO_RAIL_USB1	10
#define TEGRA_IO_RAIL_USB2	11
#define TEGRA_IO_RAIL_USB_BIAS	12
#define TEGRA_IO_RAIL_NAND	13
#define TEGRA_IO_RAIL_UART	14
#define TEGRA_IO_RAIL_BB	15
#define TEGRA_IO_RAIL_AUDIO	17
#define TEGRA_IO_RAIL_HSIC	19
#define TEGRA_IO_RAIL_COMP	22
#define TEGRA_IO_RAIL_HDMI	28
#define TEGRA_IO_RAIL_PEX_CNTRL	32
#define TEGRA_IO_RAIL_SDMMC1	33
#define TEGRA_IO_RAIL_SDMMC3	34
#define TEGRA_IO_RAIL_SDMMC4	35
#define TEGRA_IO_RAIL_CAM	36
#define TEGRA_IO_RAIL_RES	37
#define TEGRA_IO_RAIL_HV	38
#define TEGRA_IO_RAIL_DSIB	39
#define TEGRA_IO_RAIL_DSIC	40
#define TEGRA_IO_RAIL_DSID	41
#define TEGRA_IO_RAIL_CSIE	44
#define TEGRA_IO_RAIL_LVDS	57
#define TEGRA_IO_RAIL_SYS_DDC	58

#ifdef CONFIG_ARCH_TEGRA
int tegra_powergate_is_powered(unsigned int id);
int tegra_powergate_power_on(unsigned int id);
int tegra_powergate_power_off(unsigned int id);
int tegra_powergate_remove_clamping(unsigned int id);

/* Must be called with clk disabled, and returns with clk enabled */
int tegra_powergate_sequence_power_up(unsigned int id, struct clk *clk,
				      struct reset_control *rst);

int tegra_io_rail_power_on(unsigned int id);
int tegra_io_rail_power_off(unsigned int id);
#else
static inline int tegra_powergate_is_powered(unsigned int id)
{
	return -ENOSYS;
}

static inline int tegra_powergate_power_on(unsigned int id)
{
	return -ENOSYS;
}

static inline int tegra_powergate_power_off(unsigned int id)
{
	return -ENOSYS;
}

static inline int tegra_powergate_remove_clamping(unsigned int id)
{
	return -ENOSYS;
}

static inline int tegra_powergate_sequence_power_up(unsigned int id,
						    struct clk *clk,
						    struct reset_control *rst)
{
	return -ENOSYS;
}

static inline int tegra_io_rail_power_on(unsigned int id)
{
	return -ENOSYS;
}

static inline int tegra_io_rail_power_off(unsigned int id)
{
	return -ENOSYS;
}
#endif /* CONFIG_ARCH_TEGRA */

#endif /* __SOC_TEGRA_PMC_H__ */
Commit	Line	Data
ce1e3262	1	/*
ce1e3262	2	* Copyright (c) 2010 Google, Inc
7232398a	3	* Copyright (c) 2014 NVIDIA Corporation
ce1e3262 CC	4	*
	5	* Author:
	6	* Colin Cross <ccross@google.com>
	7	*
	8	* This software is licensed under the terms of the GNU General Public
	9	* License version 2, as published by the Free Software Foundation, and
	10	* may be copied, distributed, and modified under those terms.
	11	*
	12	* This program is distributed in the hope that it will be useful,
	13	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	14	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	15	* GNU General Public License for more details.
	16	*
	17	*/
	18
7232398a TR	19	#ifndef __SOC_TEGRA_PMC_H__
	20	#define __SOC_TEGRA_PMC_H__
	21
	22	#include <linux/reboot.h>
	23
	24	#include <soc/tegra/pm.h>
ce1e3262	25
a25186eb	26	struct clk;
80b28791	27	struct reset_control;
a25186eb	28
7232398a TR	29	#ifdef CONFIG_PM_SLEEP
	30	enum tegra_suspend_mode tegra_pmc_get_suspend_mode(void);
	31	void tegra_pmc_set_suspend_mode(enum tegra_suspend_mode mode);
	32	void tegra_pmc_enter_suspend_mode(enum tegra_suspend_mode mode);
	33	#endif /* CONFIG_PM_SLEEP */
	34
	35	#ifdef CONFIG_SMP
70293ed0 JH	36	bool tegra_pmc_cpu_is_powered(unsigned int cpuid);
	37	int tegra_pmc_cpu_power_on(unsigned int cpuid);
	38	int tegra_pmc_cpu_remove_clamping(unsigned int cpuid);
7232398a TR	39	#endif /* CONFIG_SMP */
	40
	41	/*
	42	* powergate and I/O rail APIs
	43	*/
	44
ce1e3262 CC	45	#define TEGRA_POWERGATE_CPU 0
	46	#define TEGRA_POWERGATE_3D 1
	47	#define TEGRA_POWERGATE_VENC 2
	48	#define TEGRA_POWERGATE_PCIE 3
	49	#define TEGRA_POWERGATE_VDEC 4
	50	#define TEGRA_POWERGATE_L2 5
	51	#define TEGRA_POWERGATE_MPE 6
6cafa97d PDS	52	#define TEGRA_POWERGATE_HEG 7
	53	#define TEGRA_POWERGATE_SATA 8
	54	#define TEGRA_POWERGATE_CPU1 9
	55	#define TEGRA_POWERGATE_CPU2 10
	56	#define TEGRA_POWERGATE_CPU3 11
	57	#define TEGRA_POWERGATE_CELP 12
	58	#define TEGRA_POWERGATE_3D1 13
bd6a9ddc TR	59	#define TEGRA_POWERGATE_CPU0 14
	60	#define TEGRA_POWERGATE_C0NC 15
	61	#define TEGRA_POWERGATE_C1NC 16
9a716579	62	#define TEGRA_POWERGATE_SOR 17
bd6a9ddc TR	63	#define TEGRA_POWERGATE_DIS 18
	64	#define TEGRA_POWERGATE_DISB 19
	65	#define TEGRA_POWERGATE_XUSBA 20
	66	#define TEGRA_POWERGATE_XUSBB 21
	67	#define TEGRA_POWERGATE_XUSBC 22
9a716579 TR	68	#define TEGRA_POWERGATE_VIC 23
9a716579 TR	69	#define TEGRA_POWERGATE_IRAM 24
c2fe4694 TR	70	#define TEGRA_POWERGATE_NVDEC 25
	71	#define TEGRA_POWERGATE_NVJPG 26
	72	#define TEGRA_POWERGATE_AUD 27
	73	#define TEGRA_POWERGATE_DFD 28
	74	#define TEGRA_POWERGATE_VE2 29
a3804512	75	#define TEGRA_POWERGATE_MAX TEGRA_POWERGATE_VE2
6cafa97d	76
6cafa97d	77	#define TEGRA_POWERGATE_3D0 TEGRA_POWERGATE_3D
ce1e3262	78
9d4450ae TR	79	#define TEGRA_IO_RAIL_CSIA 0
	80	#define TEGRA_IO_RAIL_CSIB 1
	81	#define TEGRA_IO_RAIL_DSI 2
	82	#define TEGRA_IO_RAIL_MIPI_BIAS 3
	83	#define TEGRA_IO_RAIL_PEX_BIAS 4
	84	#define TEGRA_IO_RAIL_PEX_CLK1 5
	85	#define TEGRA_IO_RAIL_PEX_CLK2 6
	86	#define TEGRA_IO_RAIL_USB0 9
	87	#define TEGRA_IO_RAIL_USB1 10
	88	#define TEGRA_IO_RAIL_USB2 11
	89	#define TEGRA_IO_RAIL_USB_BIAS 12
	90	#define TEGRA_IO_RAIL_NAND 13
	91	#define TEGRA_IO_RAIL_UART 14
	92	#define TEGRA_IO_RAIL_BB 15
	93	#define TEGRA_IO_RAIL_AUDIO 17
	94	#define TEGRA_IO_RAIL_HSIC 19
	95	#define TEGRA_IO_RAIL_COMP 22
	96	#define TEGRA_IO_RAIL_HDMI 28
	97	#define TEGRA_IO_RAIL_PEX_CNTRL 32
	98	#define TEGRA_IO_RAIL_SDMMC1 33
	99	#define TEGRA_IO_RAIL_SDMMC3 34
	100	#define TEGRA_IO_RAIL_SDMMC4 35
	101	#define TEGRA_IO_RAIL_CAM 36
	102	#define TEGRA_IO_RAIL_RES 37
	103	#define TEGRA_IO_RAIL_HV 38
	104	#define TEGRA_IO_RAIL_DSIB 39
	105	#define TEGRA_IO_RAIL_DSIC 40
	106	#define TEGRA_IO_RAIL_DSID 41
	107	#define TEGRA_IO_RAIL_CSIE 44
	108	#define TEGRA_IO_RAIL_LVDS 57
	109	#define TEGRA_IO_RAIL_SYS_DDC 58
	110
9886e1fd	111	#ifdef CONFIG_ARCH_TEGRA
70293ed0 JH	112	int tegra_powergate_is_powered(unsigned int id);
	113	int tegra_powergate_power_on(unsigned int id);
	114	int tegra_powergate_power_off(unsigned int id);
	115	int tegra_powergate_remove_clamping(unsigned int id);
ce1e3262 CC	116
ce1e3262 CC	117	/* Must be called with clk disabled, and returns with clk enabled */
70293ed0	118	int tegra_powergate_sequence_power_up(unsigned int id, struct clk *clk,
80b28791	119	struct reset_control *rst);
9d4450ae	120
70293ed0 JH	121	int tegra_io_rail_power_on(unsigned int id);
70293ed0 JH	122	int tegra_io_rail_power_off(unsigned int id);
9886e1fd	123	#else
70293ed0	124	static inline int tegra_powergate_is_powered(unsigned int id)
9886e1fd TR	125	{
	126	return -ENOSYS;
	127	}
	128
70293ed0	129	static inline int tegra_powergate_power_on(unsigned int id)
9886e1fd TR	130	{
	131	return -ENOSYS;
	132	}
	133
70293ed0	134	static inline int tegra_powergate_power_off(unsigned int id)
9886e1fd TR	135	{
	136	return -ENOSYS;
	137	}
	138
70293ed0	139	static inline int tegra_powergate_remove_clamping(unsigned int id)
9886e1fd TR	140	{
	141	return -ENOSYS;
	142	}
	143
70293ed0 JH	144	static inline int tegra_powergate_sequence_power_up(unsigned int id,
70293ed0 JH	145	struct clk *clk,
f53f4159	146	struct reset_control *rst)
9886e1fd TR	147	{
	148	return -ENOSYS;
	149	}
9d4450ae	150
70293ed0	151	static inline int tegra_io_rail_power_on(unsigned int id)
9d4450ae TR	152	{
	153	return -ENOSYS;
	154	}
	155
70293ed0	156	static inline int tegra_io_rail_power_off(unsigned int id)
9d4450ae TR	157	{
	158	return -ENOSYS;
	159	}
7232398a	160	#endif /* CONFIG_ARCH_TEGRA */
ce1e3262	161
7232398a	162	#endif /* __SOC_TEGRA_PMC_H__ */