[mirror_ubuntu-artful-kernel.git] / include / sound / cs4271.h

/*
 * Definitions for CS4271 ASoC codec driver
 *
 * Copyright (c) 2010 Alexander Sverdlin <subaparts@yandex.ru>
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License
 * as published by the Free Software Foundation; either version 2
 * of the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 */

#ifndef __CS4271_H
#define __CS4271_H

struct cs4271_platform_data {
	int gpio_nreset;	/* GPIO driving Reset pin, if any */
	bool amutec_eq_bmutec;	/* flag to enable AMUTEC=BMUTEC */

	/*
	 * The CS4271 requires its LRCLK and MCLK to be stable before its RESET
	 * line is de-asserted. That also means that clocks cannot be changed
	 * without putting the chip back into hardware reset, which also requires
	 * a complete re-initialization of all registers.
	 *
	 * One (undocumented) workaround is to assert and de-assert the PDN bit
	 * in the MODE2 register. This workaround can be enabled with the
	 * following flag.
	 *
	 * Note that this is not needed in case the clocks are stable
	 * throughout the entire runtime of the codec.
	 */
	bool enable_soft_reset;
};

#endif /* __CS4271_H */
Commit	Line	Data
67b22517 AS	1	/*
	2	* Definitions for CS4271 ASoC codec driver
	3	*
	4	* Copyright (c) 2010 Alexander Sverdlin <subaparts@yandex.ru>
	5	*
	6	* This program is free software; you can redistribute it and/or
	7	* modify it under the terms of the GNU General Public License
	8	* as published by the Free Software Foundation; either version 2
	9	* of the License, or (at your option) any later version.
	10	*
	11	* This program is distributed in the hope that it will be useful,
	12	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	13	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	14	* GNU General Public License for more details.
	15	*/
	16
	17	#ifndef __CS4271_H
	18	#define __CS4271_H
	19
	20	struct cs4271_platform_data {
	21	int gpio_nreset; /* GPIO driving Reset pin, if any */
26047e2d	22	bool amutec_eq_bmutec; /* flag to enable AMUTEC=BMUTEC */
fd23fb9f DM	23
	24	/*
	25	* The CS4271 requires its LRCLK and MCLK to be stable before its RESET
	26	* line is de-asserted. That also means that clocks cannot be changed
	27	* without putting the chip back into hardware reset, which also requires
	28	* a complete re-initialization of all registers.
	29	*
	30	* One (undocumented) workaround is to assert and de-assert the PDN bit
	31	* in the MODE2 register. This workaround can be enabled with the
	32	* following flag.
	33	*
	34	* Note that this is not needed in case the clocks are stable
	35	* throughout the entire runtime of the codec.
	36	*/
	37	bool enable_soft_reset;
67b22517 AS	38	};
	39
	40	#endif /* __CS4271_H */