[mirror_ubuntu-bionic-kernel.git] / include / sound / hda_register.h

/* SPDX-License-Identifier: GPL-2.0 */
/*
 * HD-audio controller (Azalia) registers and helpers
 *
 * For traditional reasons, we still use azx_ prefix here
 */

#ifndef __SOUND_HDA_REGISTER_H
#define __SOUND_HDA_REGISTER_H

#include <linux/io.h>
#include <sound/hdaudio.h>

#define AZX_REG_GCAP			0x00
#define   AZX_GCAP_64OK		(1 << 0)   /* 64bit address support */
#define   AZX_GCAP_NSDO		(3 << 1)   /* # of serial data out signals */
#define   AZX_GCAP_BSS		(31 << 3)  /* # of bidirectional streams */
#define   AZX_GCAP_ISS		(15 << 8)  /* # of input streams */
#define   AZX_GCAP_OSS		(15 << 12) /* # of output streams */
#define AZX_REG_VMIN			0x02
#define AZX_REG_VMAJ			0x03
#define AZX_REG_OUTPAY			0x04
#define AZX_REG_INPAY			0x06
#define AZX_REG_GCTL			0x08
#define   AZX_GCTL_RESET	(1 << 0)   /* controller reset */
#define   AZX_GCTL_FCNTRL	(1 << 1)   /* flush control */
#define   AZX_GCTL_UNSOL	(1 << 8)   /* accept unsol. response enable */
#define AZX_REG_WAKEEN			0x0c
#define AZX_REG_STATESTS		0x0e
#define AZX_REG_GSTS			0x10
#define   AZX_GSTS_FSTS		(1 << 1)   /* flush status */
#define AZX_REG_GCAP2			0x12
#define AZX_REG_LLCH			0x14
#define AZX_REG_OUTSTRMPAY		0x18
#define AZX_REG_INSTRMPAY		0x1A
#define AZX_REG_INTCTL			0x20
#define AZX_REG_INTSTS			0x24
#define AZX_REG_WALLCLK			0x30	/* 24Mhz source */
#define AZX_REG_OLD_SSYNC		0x34	/* SSYNC for old ICH */
#define AZX_REG_SSYNC			0x38
#define AZX_REG_CORBLBASE		0x40
#define AZX_REG_CORBUBASE		0x44
#define AZX_REG_CORBWP			0x48
#define AZX_REG_CORBRP			0x4a
#define   AZX_CORBRP_RST	(1 << 15)  /* read pointer reset */
#define AZX_REG_CORBCTL			0x4c
#define   AZX_CORBCTL_RUN	(1 << 1)   /* enable DMA */
#define   AZX_CORBCTL_CMEIE	(1 << 0)   /* enable memory error irq */
#define AZX_REG_CORBSTS			0x4d
#define   AZX_CORBSTS_CMEI	(1 << 0)   /* memory error indication */
#define AZX_REG_CORBSIZE		0x4e

#define AZX_REG_RIRBLBASE		0x50
#define AZX_REG_RIRBUBASE		0x54
#define AZX_REG_RIRBWP			0x58
#define   AZX_RIRBWP_RST	(1 << 15)  /* write pointer reset */
#define AZX_REG_RINTCNT			0x5a
#define AZX_REG_RIRBCTL			0x5c
#define   AZX_RBCTL_IRQ_EN	(1 << 0)   /* enable IRQ */
#define   AZX_RBCTL_DMA_EN	(1 << 1)   /* enable DMA */
#define   AZX_RBCTL_OVERRUN_EN	(1 << 2)   /* enable overrun irq */
#define AZX_REG_RIRBSTS			0x5d
#define   AZX_RBSTS_IRQ		(1 << 0)   /* response irq */
#define   AZX_RBSTS_OVERRUN	(1 << 2)   /* overrun irq */
#define AZX_REG_RIRBSIZE		0x5e

#define AZX_REG_IC			0x60
#define AZX_REG_IR			0x64
#define AZX_REG_IRS			0x68
#define   AZX_IRS_VALID		(1<<1)
#define   AZX_IRS_BUSY		(1<<0)

#define AZX_REG_DPLBASE			0x70
#define AZX_REG_DPUBASE			0x74
#define   AZX_DPLBASE_ENABLE	0x1	/* Enable position buffer */

/* SD offset: SDI0=0x80, SDI1=0xa0, ... SDO3=0x160 */
enum { SDI0, SDI1, SDI2, SDI3, SDO0, SDO1, SDO2, SDO3 };

/* stream register offsets from stream base */
#define AZX_REG_SD_CTL			0x00
#define AZX_REG_SD_STS			0x03
#define AZX_REG_SD_LPIB			0x04
#define AZX_REG_SD_CBL			0x08
#define AZX_REG_SD_LVI			0x0c
#define AZX_REG_SD_FIFOW		0x0e
#define AZX_REG_SD_FIFOSIZE		0x10
#define AZX_REG_SD_FORMAT		0x12
#define AZX_REG_SD_FIFOL		0x14
#define AZX_REG_SD_BDLPL		0x18
#define AZX_REG_SD_BDLPU		0x1c

/* GTS registers */
#define AZX_REG_LLCH			0x14

#define AZX_REG_GTS_BASE		0x520

#define AZX_REG_GTSCC	(AZX_REG_GTS_BASE + 0x00)
#define AZX_REG_WALFCC	(AZX_REG_GTS_BASE + 0x04)
#define AZX_REG_TSCCL	(AZX_REG_GTS_BASE + 0x08)
#define AZX_REG_TSCCU	(AZX_REG_GTS_BASE + 0x0C)
#define AZX_REG_LLPFOC	(AZX_REG_GTS_BASE + 0x14)
#define AZX_REG_LLPCL	(AZX_REG_GTS_BASE + 0x18)
#define AZX_REG_LLPCU	(AZX_REG_GTS_BASE + 0x1C)

/* Haswell/Broadwell display HD-A controller Extended Mode registers */
#define AZX_REG_HSW_EM4			0x100c
#define AZX_REG_HSW_EM5			0x1010

/* Skylake/Broxton vendor-specific registers */
#define AZX_REG_VS_EM1			0x1000
#define AZX_REG_VS_INRC			0x1004
#define AZX_REG_VS_OUTRC		0x1008
#define AZX_REG_VS_FIFOTRK		0x100C
#define AZX_REG_VS_FIFOTRK2		0x1010
#define AZX_REG_VS_EM2			0x1030
#define AZX_REG_VS_EM3L			0x1038
#define AZX_REG_VS_EM3U			0x103C
#define AZX_REG_VS_EM4L			0x1040
#define AZX_REG_VS_EM4U			0x1044
#define AZX_REG_VS_LTRC			0x1048
#define AZX_REG_VS_D0I3C		0x104A
#define AZX_REG_VS_PCE			0x104B
#define AZX_REG_VS_L2MAGC		0x1050
#define AZX_REG_VS_L2LAHPT		0x1054
#define AZX_REG_VS_SDXDPIB_XBASE	0x1084
#define AZX_REG_VS_SDXDPIB_XINTERVAL	0x20
#define AZX_REG_VS_SDXEFIFOS_XBASE	0x1094
#define AZX_REG_VS_SDXEFIFOS_XINTERVAL	0x20

/* PCI space */
#define AZX_PCIREG_TCSEL		0x44

/*
 * other constants
 */

/* max number of fragments - we may use more if allocating more pages for BDL */
#define BDL_SIZE		4096
#define AZX_MAX_BDL_ENTRIES	(BDL_SIZE / 16)
#define AZX_MAX_FRAG		32
/* max buffer size - no h/w limit, you can increase as you like */
#define AZX_MAX_BUF_SIZE	(1024*1024*1024)

/* RIRB int mask: overrun[2], response[0] */
#define RIRB_INT_RESPONSE	0x01
#define RIRB_INT_OVERRUN	0x04
#define RIRB_INT_MASK		0x05

/* STATESTS int mask: S3,SD2,SD1,SD0 */
#define STATESTS_INT_MASK	((1 << HDA_MAX_CODECS) - 1)

/* SD_CTL bits */
#define SD_CTL_STREAM_RESET	0x01	/* stream reset bit */
#define SD_CTL_DMA_START	0x02	/* stream DMA start bit */
#define SD_CTL_STRIPE		(3 << 16)	/* stripe control */
#define SD_CTL_TRAFFIC_PRIO	(1 << 18)	/* traffic priority */
#define SD_CTL_DIR		(1 << 19)	/* bi-directional stream */
#define SD_CTL_STREAM_TAG_MASK	(0xf << 20)
#define SD_CTL_STREAM_TAG_SHIFT	20

/* SD_CTL and SD_STS */
#define SD_INT_DESC_ERR		0x10	/* descriptor error interrupt */
#define SD_INT_FIFO_ERR		0x08	/* FIFO error interrupt */
#define SD_INT_COMPLETE		0x04	/* completion interrupt */
#define SD_INT_MASK		(SD_INT_DESC_ERR|SD_INT_FIFO_ERR|\
				 SD_INT_COMPLETE)

/* SD_STS */
#define SD_STS_FIFO_READY	0x20	/* FIFO ready */

/* INTCTL and INTSTS */
#define AZX_INT_ALL_STREAM	0xff	   /* all stream interrupts */
#define AZX_INT_CTRL_EN	0x40000000 /* controller interrupt enable bit */
#define AZX_INT_GLOBAL_EN	0x80000000 /* global interrupt enable bit */

/* below are so far hardcoded - should read registers in future */
#define AZX_MAX_CORB_ENTRIES	256
#define AZX_MAX_RIRB_ENTRIES	256

/* Capability header  Structure */
#define AZX_REG_CAP_HDR			0x0
#define AZX_CAP_HDR_VER_OFF		28
#define AZX_CAP_HDR_VER_MASK		(0xF << AZX_CAP_HDR_VER_OFF)
#define AZX_CAP_HDR_ID_OFF		16
#define AZX_CAP_HDR_ID_MASK		(0xFFF << AZX_CAP_HDR_ID_OFF)
#define AZX_CAP_HDR_NXT_PTR_MASK	0xFFFF

/* registers of Software Position Based FIFO Capability Structure */
#define AZX_SPB_CAP_ID			0x4
#define AZX_REG_SPB_BASE_ADDR		0x700
#define AZX_REG_SPB_SPBFCH		0x00
#define AZX_REG_SPB_SPBFCCTL		0x04
/* Base used to calculate the iterating register offset */
#define AZX_SPB_BASE			0x08
/* Interval used to calculate the iterating register offset */
#define AZX_SPB_INTERVAL		0x08
/* SPIB base */
#define AZX_SPB_SPIB			0x00
/* SPIB MAXFIFO base*/
#define AZX_SPB_MAXFIFO			0x04

/* registers of Global Time Synchronization Capability Structure */
#define AZX_GTS_CAP_ID			0x1
#define AZX_REG_GTS_GTSCH		0x00
#define AZX_REG_GTS_GTSCD		0x04
#define AZX_REG_GTS_GTSCTLAC		0x0C
#define AZX_GTS_BASE			0x20
#define AZX_GTS_INTERVAL		0x20

/* registers for Processing Pipe Capability Structure */
#define AZX_PP_CAP_ID			0x3
#define AZX_REG_PP_PPCH			0x10
#define AZX_REG_PP_PPCTL		0x04
#define AZX_PPCTL_PIE			(1<<31)
#define AZX_PPCTL_GPROCEN		(1<<30)
/* _X_ = dma engine # and cannot * exceed 29 (per spec max 30 dma engines) */
#define AZX_PPCTL_PROCEN(_X_)		(1<<(_X_))

#define AZX_REG_PP_PPSTS		0x08

#define AZX_PPHC_BASE			0x10
#define AZX_PPHC_INTERVAL		0x10

#define AZX_REG_PPHCLLPL		0x0
#define AZX_REG_PPHCLLPU		0x4
#define AZX_REG_PPHCLDPL		0x8
#define AZX_REG_PPHCLDPU		0xC

#define AZX_PPLC_BASE			0x10
#define AZX_PPLC_MULTI			0x10
#define AZX_PPLC_INTERVAL		0x10

#define AZX_REG_PPLCCTL			0x0
#define AZX_PPLCCTL_STRM_BITS		4
#define AZX_PPLCCTL_STRM_SHIFT		20
#define AZX_REG_MASK(bit_num, offset) \
	(((1 << (bit_num)) - 1) << (offset))
#define AZX_PPLCCTL_STRM_MASK \
	AZX_REG_MASK(AZX_PPLCCTL_STRM_BITS, AZX_PPLCCTL_STRM_SHIFT)
#define AZX_PPLCCTL_RUN			(1<<1)
#define AZX_PPLCCTL_STRST		(1<<0)

#define AZX_REG_PPLCFMT			0x4
#define AZX_REG_PPLCLLPL		0x8
#define AZX_REG_PPLCLLPU		0xC

/* registers for Multiple Links Capability Structure */
#define AZX_ML_CAP_ID			0x2
#define AZX_REG_ML_MLCH			0x00
#define AZX_REG_ML_MLCD			0x04
#define AZX_ML_BASE			0x40
#define AZX_ML_INTERVAL			0x40

#define AZX_REG_ML_LCAP			0x00
#define AZX_REG_ML_LCTL			0x04
#define AZX_REG_ML_LOSIDV		0x08
#define AZX_REG_ML_LSDIID		0x0C
#define AZX_REG_ML_LPSOO		0x10
#define AZX_REG_ML_LPSIO		0x12
#define AZX_REG_ML_LWALFC		0x18
#define AZX_REG_ML_LOUTPAY		0x20
#define AZX_REG_ML_LINPAY		0x30

#define ML_LCTL_SCF_MASK			0xF
#define AZX_MLCTL_SPA				(0x1 << 16)
#define AZX_MLCTL_CPA				(0x1 << 23)
#define AZX_MLCTL_SPA_SHIFT			16
#define AZX_MLCTL_CPA_SHIFT			23

/* registers for DMA Resume Capability Structure */
#define AZX_DRSM_CAP_ID			0x5
#define AZX_REG_DRSM_CTL		0x4
/* Base used to calculate the iterating register offset */
#define AZX_DRSM_BASE			0x08
/* Interval used to calculate the iterating register offset */
#define AZX_DRSM_INTERVAL		0x08

/* Global time synchronization registers */
#define GTSCC_TSCCD_MASK		0x80000000
#define GTSCC_TSCCD_SHIFT		BIT(31)
#define GTSCC_TSCCI_MASK		0x20
#define GTSCC_CDMAS_DMA_DIR_SHIFT	4

#define WALFCC_CIF_MASK			0x1FF
#define WALFCC_FN_SHIFT			9
#define HDA_CLK_CYCLES_PER_FRAME	512

/*
 * An error occurs near frame "rollover". The clocks in frame value indicates
 * whether this error may have occurred. Here we use the value of 10. Please
 * see the errata for the right number [<10]
 */
#define HDA_MAX_CYCLE_VALUE		499
#define HDA_MAX_CYCLE_OFFSET		10
#define HDA_MAX_CYCLE_READ_RETRY	10

#define TSCCU_CCU_SHIFT			32
#define LLPC_CCU_SHIFT			32


/*
 * helpers to read the stream position
 */
static inline unsigned int
snd_hdac_stream_get_pos_lpib(struct hdac_stream *stream)
{
	return snd_hdac_stream_readl(stream, SD_LPIB);
}

static inline unsigned int
snd_hdac_stream_get_pos_posbuf(struct hdac_stream *stream)
{
	return le32_to_cpu(*stream->posbuf);
}

#endif /* __SOUND_HDA_REGISTER_H */
Commit	Line	Data
b2441318	1	/* SPDX-License-Identifier: GPL-2.0 */
14752412 TI	2	/*
	3	* HD-audio controller (Azalia) registers and helpers
	4	*
	5	* For traditional reasons, we still use azx_ prefix here
	6	*/
	7
	8	#ifndef __SOUND_HDA_REGISTER_H
	9	#define __SOUND_HDA_REGISTER_H
	10
	11	#include <linux/io.h>
	12	#include <sound/hdaudio.h>
	13
	14	#define AZX_REG_GCAP 0x00
	15	#define AZX_GCAP_64OK (1 << 0) /* 64bit address support */
	16	#define AZX_GCAP_NSDO (3 << 1) /* # of serial data out signals */
	17	#define AZX_GCAP_BSS (31 << 3) /* # of bidirectional streams */
	18	#define AZX_GCAP_ISS (15 << 8) /* # of input streams */
	19	#define AZX_GCAP_OSS (15 << 12) /* # of output streams */
	20	#define AZX_REG_VMIN 0x02
	21	#define AZX_REG_VMAJ 0x03
	22	#define AZX_REG_OUTPAY 0x04
	23	#define AZX_REG_INPAY 0x06
	24	#define AZX_REG_GCTL 0x08
	25	#define AZX_GCTL_RESET (1 << 0) /* controller reset */
	26	#define AZX_GCTL_FCNTRL (1 << 1) /* flush control */
	27	#define AZX_GCTL_UNSOL (1 << 8) /* accept unsol. response enable */
	28	#define AZX_REG_WAKEEN 0x0c
	29	#define AZX_REG_STATESTS 0x0e
	30	#define AZX_REG_GSTS 0x10
	31	#define AZX_GSTS_FSTS (1 << 1) /* flush status */
83b0b677 JK	32	#define AZX_REG_GCAP2 0x12
	33	#define AZX_REG_LLCH 0x14
	34	#define AZX_REG_OUTSTRMPAY 0x18
	35	#define AZX_REG_INSTRMPAY 0x1A
14752412 TI	36	#define AZX_REG_INTCTL 0x20
	37	#define AZX_REG_INTSTS 0x24
	38	#define AZX_REG_WALLCLK 0x30 /* 24Mhz source */
	39	#define AZX_REG_OLD_SSYNC 0x34 /* SSYNC for old ICH */
	40	#define AZX_REG_SSYNC 0x38
	41	#define AZX_REG_CORBLBASE 0x40
	42	#define AZX_REG_CORBUBASE 0x44
	43	#define AZX_REG_CORBWP 0x48
	44	#define AZX_REG_CORBRP 0x4a
	45	#define AZX_CORBRP_RST (1 << 15) /* read pointer reset */
	46	#define AZX_REG_CORBCTL 0x4c
	47	#define AZX_CORBCTL_RUN (1 << 1) /* enable DMA */
	48	#define AZX_CORBCTL_CMEIE (1 << 0) /* enable memory error irq */
	49	#define AZX_REG_CORBSTS 0x4d
	50	#define AZX_CORBSTS_CMEI (1 << 0) /* memory error indication */
	51	#define AZX_REG_CORBSIZE 0x4e
	52
	53	#define AZX_REG_RIRBLBASE 0x50
	54	#define AZX_REG_RIRBUBASE 0x54
	55	#define AZX_REG_RIRBWP 0x58
	56	#define AZX_RIRBWP_RST (1 << 15) /* write pointer reset */
	57	#define AZX_REG_RINTCNT 0x5a
	58	#define AZX_REG_RIRBCTL 0x5c
	59	#define AZX_RBCTL_IRQ_EN (1 << 0) /* enable IRQ */
	60	#define AZX_RBCTL_DMA_EN (1 << 1) /* enable DMA */
	61	#define AZX_RBCTL_OVERRUN_EN (1 << 2) /* enable overrun irq */
	62	#define AZX_REG_RIRBSTS 0x5d
	63	#define AZX_RBSTS_IRQ (1 << 0) /* response irq */
	64	#define AZX_RBSTS_OVERRUN (1 << 2) /* overrun irq */
	65	#define AZX_REG_RIRBSIZE 0x5e
	66
	67	#define AZX_REG_IC 0x60
	68	#define AZX_REG_IR 0x64
	69	#define AZX_REG_IRS 0x68
	70	#define AZX_IRS_VALID (1<<1)
	71	#define AZX_IRS_BUSY (1<<0)
	72
	73	#define AZX_REG_DPLBASE 0x70
	74	#define AZX_REG_DPUBASE 0x74
	75	#define AZX_DPLBASE_ENABLE 0x1 /* Enable position buffer */
	76
	77	/* SD offset: SDI0=0x80, SDI1=0xa0, ... SDO3=0x160 */
	78	enum { SDI0, SDI1, SDI2, SDI3, SDO0, SDO1, SDO2, SDO3 };
	79
	80	/* stream register offsets from stream base */
	81	#define AZX_REG_SD_CTL 0x00
	82	#define AZX_REG_SD_STS 0x03
	83	#define AZX_REG_SD_LPIB 0x04
	84	#define AZX_REG_SD_CBL 0x08
	85	#define AZX_REG_SD_LVI 0x0c
	86	#define AZX_REG_SD_FIFOW 0x0e
	87	#define AZX_REG_SD_FIFOSIZE 0x10
	88	#define AZX_REG_SD_FORMAT 0x12
83b0b677	89	#define AZX_REG_SD_FIFOL 0x14
14752412 TI	90	#define AZX_REG_SD_BDLPL 0x18
	91	#define AZX_REG_SD_BDLPU 0x1c
	92
50279d9b GS	93	/* GTS registers */
	94	#define AZX_REG_LLCH 0x14
	95
	96	#define AZX_REG_GTS_BASE 0x520
	97
	98	#define AZX_REG_GTSCC (AZX_REG_GTS_BASE + 0x00)
	99	#define AZX_REG_WALFCC (AZX_REG_GTS_BASE + 0x04)
	100	#define AZX_REG_TSCCL (AZX_REG_GTS_BASE + 0x08)
	101	#define AZX_REG_TSCCU (AZX_REG_GTS_BASE + 0x0C)
	102	#define AZX_REG_LLPFOC (AZX_REG_GTS_BASE + 0x14)
	103	#define AZX_REG_LLPCL (AZX_REG_GTS_BASE + 0x18)
	104	#define AZX_REG_LLPCU (AZX_REG_GTS_BASE + 0x1C)
	105
98d8fc6c ML	106	/* Haswell/Broadwell display HD-A controller Extended Mode registers */
	107	#define AZX_REG_HSW_EM4 0x100c
	108	#define AZX_REG_HSW_EM5 0x1010
	109
70eafad8 TI	110	/* Skylake/Broxton vendor-specific registers */
	111	#define AZX_REG_VS_EM1 0x1000
	112	#define AZX_REG_VS_INRC 0x1004
	113	#define AZX_REG_VS_OUTRC 0x1008
	114	#define AZX_REG_VS_FIFOTRK 0x100C
	115	#define AZX_REG_VS_FIFOTRK2 0x1010
	116	#define AZX_REG_VS_EM2 0x1030
	117	#define AZX_REG_VS_EM3L 0x1038
	118	#define AZX_REG_VS_EM3U 0x103C
	119	#define AZX_REG_VS_EM4L 0x1040
	120	#define AZX_REG_VS_EM4U 0x1044
	121	#define AZX_REG_VS_LTRC 0x1048
	122	#define AZX_REG_VS_D0I3C 0x104A
	123	#define AZX_REG_VS_PCE 0x104B
	124	#define AZX_REG_VS_L2MAGC 0x1050
	125	#define AZX_REG_VS_L2LAHPT 0x1054
	126	#define AZX_REG_VS_SDXDPIB_XBASE 0x1084
	127	#define AZX_REG_VS_SDXDPIB_XINTERVAL 0x20
	128	#define AZX_REG_VS_SDXEFIFOS_XBASE 0x1094
	129	#define AZX_REG_VS_SDXEFIFOS_XINTERVAL 0x20
7c23b7c1	130
14752412 TI	131	/* PCI space */
	132	#define AZX_PCIREG_TCSEL 0x44
	133
	134	/*
	135	* other constants
	136	*/
	137
	138	/* max number of fragments - we may use more if allocating more pages for BDL */
	139	#define BDL_SIZE 4096
	140	#define AZX_MAX_BDL_ENTRIES (BDL_SIZE / 16)
	141	#define AZX_MAX_FRAG 32
	142	/* max buffer size - no h/w limit, you can increase as you like */
	143	#define AZX_MAX_BUF_SIZE (102410241024)
	144
	145	/* RIRB int mask: overrun[2], response[0] */
	146	#define RIRB_INT_RESPONSE 0x01
	147	#define RIRB_INT_OVERRUN 0x04
	148	#define RIRB_INT_MASK 0x05
	149
	150	/* STATESTS int mask: S3,SD2,SD1,SD0 */
	151	#define STATESTS_INT_MASK ((1 << HDA_MAX_CODECS) - 1)
	152
	153	/* SD_CTL bits */
	154	#define SD_CTL_STREAM_RESET 0x01 /* stream reset bit */
	155	#define SD_CTL_DMA_START 0x02 /* stream DMA start bit */
	156	#define SD_CTL_STRIPE (3 << 16) /* stripe control */
	157	#define SD_CTL_TRAFFIC_PRIO (1 << 18) /* traffic priority */
	158	#define SD_CTL_DIR (1 << 19) /* bi-directional stream */
	159	#define SD_CTL_STREAM_TAG_MASK (0xf << 20)
	160	#define SD_CTL_STREAM_TAG_SHIFT 20
	161
	162	/* SD_CTL and SD_STS */
	163	#define SD_INT_DESC_ERR 0x10 /* descriptor error interrupt */
	164	#define SD_INT_FIFO_ERR 0x08 /* FIFO error interrupt */
	165	#define SD_INT_COMPLETE 0x04 /* completion interrupt */
	166	#define SD_INT_MASK (SD_INT_DESC_ERR\|SD_INT_FIFO_ERR\|\
	167	SD_INT_COMPLETE)
	168
	169	/* SD_STS */
	170	#define SD_STS_FIFO_READY 0x20 /* FIFO ready */
	171
	172	/* INTCTL and INTSTS */
	173	#define AZX_INT_ALL_STREAM 0xff /* all stream interrupts */
	174	#define AZX_INT_CTRL_EN 0x40000000 /* controller interrupt enable bit */
	175	#define AZX_INT_GLOBAL_EN 0x80000000 /* global interrupt enable bit */
	176
	177	/* below are so far hardcoded - should read registers in future */
	178	#define AZX_MAX_CORB_ENTRIES 256
	179	#define AZX_MAX_RIRB_ENTRIES 256
	180
83b0b677 JK	181	/* Capability header Structure */
	182	#define AZX_REG_CAP_HDR 0x0
	183	#define AZX_CAP_HDR_VER_OFF 28
	184	#define AZX_CAP_HDR_VER_MASK (0xF << AZX_CAP_HDR_VER_OFF)
	185	#define AZX_CAP_HDR_ID_OFF 16
	186	#define AZX_CAP_HDR_ID_MASK (0xFFF << AZX_CAP_HDR_ID_OFF)
	187	#define AZX_CAP_HDR_NXT_PTR_MASK 0xFFFF
	188
	189	/* registers of Software Position Based FIFO Capability Structure */
	190	#define AZX_SPB_CAP_ID 0x4
	191	#define AZX_REG_SPB_BASE_ADDR 0x700
	192	#define AZX_REG_SPB_SPBFCH 0x00
	193	#define AZX_REG_SPB_SPBFCCTL 0x04
	194	/* Base used to calculate the iterating register offset */
	195	#define AZX_SPB_BASE 0x08
	196	/* Interval used to calculate the iterating register offset */
	197	#define AZX_SPB_INTERVAL 0x08
ee8bc4df JK	198	/* SPIB base */
	199	#define AZX_SPB_SPIB 0x00
	200	/* SPIB MAXFIFO base*/
	201	#define AZX_SPB_MAXFIFO 0x04
83b0b677 JK	202
	203	/* registers of Global Time Synchronization Capability Structure */
	204	#define AZX_GTS_CAP_ID 0x1
	205	#define AZX_REG_GTS_GTSCH 0x00
	206	#define AZX_REG_GTS_GTSCD 0x04
	207	#define AZX_REG_GTS_GTSCTLAC 0x0C
	208	#define AZX_GTS_BASE 0x20
	209	#define AZX_GTS_INTERVAL 0x20
	210
	211	/* registers for Processing Pipe Capability Structure */
	212	#define AZX_PP_CAP_ID 0x3
	213	#define AZX_REG_PP_PPCH 0x10
	214	#define AZX_REG_PP_PPCTL 0x04
	215	#define AZX_PPCTL_PIE (1<<31)
	216	#define AZX_PPCTL_GPROCEN (1<<30)
	217	/* _X_ = dma engine # and cannot * exceed 29 (per spec max 30 dma engines) */
	218	#define AZX_PPCTL_PROCEN(_X_) (1<<(_X_))
	219
	220	#define AZX_REG_PP_PPSTS 0x08
	221
	222	#define AZX_PPHC_BASE 0x10
	223	#define AZX_PPHC_INTERVAL 0x10
	224
	225	#define AZX_REG_PPHCLLPL 0x0
	226	#define AZX_REG_PPHCLLPU 0x4
	227	#define AZX_REG_PPHCLDPL 0x8
	228	#define AZX_REG_PPHCLDPU 0xC
	229
	230	#define AZX_PPLC_BASE 0x10
	231	#define AZX_PPLC_MULTI 0x10
	232	#define AZX_PPLC_INTERVAL 0x10
	233
	234	#define AZX_REG_PPLCCTL 0x0
	235	#define AZX_PPLCCTL_STRM_BITS 4
	236	#define AZX_PPLCCTL_STRM_SHIFT 20
	237	#define AZX_REG_MASK(bit_num, offset) \
	238	(((1 << (bit_num)) - 1) << (offset))
	239	#define AZX_PPLCCTL_STRM_MASK \
	240	AZX_REG_MASK(AZX_PPLCCTL_STRM_BITS, AZX_PPLCCTL_STRM_SHIFT)
	241	#define AZX_PPLCCTL_RUN (1<<1)
	242	#define AZX_PPLCCTL_STRST (1<<0)
	243
	244	#define AZX_REG_PPLCFMT 0x4
	245	#define AZX_REG_PPLCLLPL 0x8
	246	#define AZX_REG_PPLCLLPU 0xC
	247
	248	/* registers for Multiple Links Capability Structure */
	249	#define AZX_ML_CAP_ID 0x2
	250	#define AZX_REG_ML_MLCH 0x00
	251	#define AZX_REG_ML_MLCD 0x04
	252	#define AZX_ML_BASE 0x40
	253	#define AZX_ML_INTERVAL 0x40
	254
	255	#define AZX_REG_ML_LCAP 0x00
	256	#define AZX_REG_ML_LCTL 0x04
	257	#define AZX_REG_ML_LOSIDV 0x08
	258	#define AZX_REG_ML_LSDIID 0x0C
	259	#define AZX_REG_ML_LPSOO 0x10
	260	#define AZX_REG_ML_LPSIO 0x12
	261	#define AZX_REG_ML_LWALFC 0x18
	262	#define AZX_REG_ML_LOUTPAY 0x20
	263	#define AZX_REG_ML_LINPAY 0x30
	264
dde5bff5 LY	265	#define ML_LCTL_SCF_MASK 0xF
	266	#define AZX_MLCTL_SPA (0x1 << 16)
	267	#define AZX_MLCTL_CPA (0x1 << 23)
	268	#define AZX_MLCTL_SPA_SHIFT 16
	269	#define AZX_MLCTL_CPA_SHIFT 23
a9c48f7f JK	270
	271	/* registers for DMA Resume Capability Structure */
	272	#define AZX_DRSM_CAP_ID 0x5
	273	#define AZX_REG_DRSM_CTL 0x4
	274	/* Base used to calculate the iterating register offset */
	275	#define AZX_DRSM_BASE 0x08
	276	/* Interval used to calculate the iterating register offset */
	277	#define AZX_DRSM_INTERVAL 0x08
	278
50279d9b GS	279	/* Global time synchronization registers */
	280	#define GTSCC_TSCCD_MASK 0x80000000
	281	#define GTSCC_TSCCD_SHIFT BIT(31)
	282	#define GTSCC_TSCCI_MASK 0x20
	283	#define GTSCC_CDMAS_DMA_DIR_SHIFT 4
	284
	285	#define WALFCC_CIF_MASK 0x1FF
	286	#define WALFCC_FN_SHIFT 9
	287	#define HDA_CLK_CYCLES_PER_FRAME 512
	288
	289	/*
	290	* An error occurs near frame "rollover". The clocks in frame value indicates
	291	* whether this error may have occurred. Here we use the value of 10. Please
	292	* see the errata for the right number [<10]
	293	*/
	294	#define HDA_MAX_CYCLE_VALUE 499
	295	#define HDA_MAX_CYCLE_OFFSET 10
	296	#define HDA_MAX_CYCLE_READ_RETRY 10
	297
	298	#define TSCCU_CCU_SHIFT 32
	299	#define LLPC_CCU_SHIFT 32
	300
	301
14752412 TI	302	/*
	303	* helpers to read the stream position
	304	*/
	305	static inline unsigned int
	306	snd_hdac_stream_get_pos_lpib(struct hdac_stream *stream)
	307	{
	308	return snd_hdac_stream_readl(stream, SD_LPIB);
	309	}
	310
	311	static inline unsigned int
	312	snd_hdac_stream_get_pos_posbuf(struct hdac_stream *stream)
	313	{
	314	return le32_to_cpu(*stream->posbuf);
	315	}
	316
	317	#endif /* __SOUND_HDA_REGISTER_H */