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Commit | Line | Data |
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14752412 TI |
1 | /* |
2 | * HD-audio controller (Azalia) registers and helpers | |
3 | * | |
4 | * For traditional reasons, we still use azx_ prefix here | |
5 | */ | |
6 | ||
7 | #ifndef __SOUND_HDA_REGISTER_H | |
8 | #define __SOUND_HDA_REGISTER_H | |
9 | ||
10 | #include <linux/io.h> | |
11 | #include <sound/hdaudio.h> | |
12 | ||
13 | #define AZX_REG_GCAP 0x00 | |
14 | #define AZX_GCAP_64OK (1 << 0) /* 64bit address support */ | |
15 | #define AZX_GCAP_NSDO (3 << 1) /* # of serial data out signals */ | |
16 | #define AZX_GCAP_BSS (31 << 3) /* # of bidirectional streams */ | |
17 | #define AZX_GCAP_ISS (15 << 8) /* # of input streams */ | |
18 | #define AZX_GCAP_OSS (15 << 12) /* # of output streams */ | |
19 | #define AZX_REG_VMIN 0x02 | |
20 | #define AZX_REG_VMAJ 0x03 | |
21 | #define AZX_REG_OUTPAY 0x04 | |
22 | #define AZX_REG_INPAY 0x06 | |
23 | #define AZX_REG_GCTL 0x08 | |
24 | #define AZX_GCTL_RESET (1 << 0) /* controller reset */ | |
25 | #define AZX_GCTL_FCNTRL (1 << 1) /* flush control */ | |
26 | #define AZX_GCTL_UNSOL (1 << 8) /* accept unsol. response enable */ | |
27 | #define AZX_REG_WAKEEN 0x0c | |
28 | #define AZX_REG_STATESTS 0x0e | |
29 | #define AZX_REG_GSTS 0x10 | |
30 | #define AZX_GSTS_FSTS (1 << 1) /* flush status */ | |
31 | #define AZX_REG_INTCTL 0x20 | |
32 | #define AZX_REG_INTSTS 0x24 | |
33 | #define AZX_REG_WALLCLK 0x30 /* 24Mhz source */ | |
34 | #define AZX_REG_OLD_SSYNC 0x34 /* SSYNC for old ICH */ | |
35 | #define AZX_REG_SSYNC 0x38 | |
36 | #define AZX_REG_CORBLBASE 0x40 | |
37 | #define AZX_REG_CORBUBASE 0x44 | |
38 | #define AZX_REG_CORBWP 0x48 | |
39 | #define AZX_REG_CORBRP 0x4a | |
40 | #define AZX_CORBRP_RST (1 << 15) /* read pointer reset */ | |
41 | #define AZX_REG_CORBCTL 0x4c | |
42 | #define AZX_CORBCTL_RUN (1 << 1) /* enable DMA */ | |
43 | #define AZX_CORBCTL_CMEIE (1 << 0) /* enable memory error irq */ | |
44 | #define AZX_REG_CORBSTS 0x4d | |
45 | #define AZX_CORBSTS_CMEI (1 << 0) /* memory error indication */ | |
46 | #define AZX_REG_CORBSIZE 0x4e | |
47 | ||
48 | #define AZX_REG_RIRBLBASE 0x50 | |
49 | #define AZX_REG_RIRBUBASE 0x54 | |
50 | #define AZX_REG_RIRBWP 0x58 | |
51 | #define AZX_RIRBWP_RST (1 << 15) /* write pointer reset */ | |
52 | #define AZX_REG_RINTCNT 0x5a | |
53 | #define AZX_REG_RIRBCTL 0x5c | |
54 | #define AZX_RBCTL_IRQ_EN (1 << 0) /* enable IRQ */ | |
55 | #define AZX_RBCTL_DMA_EN (1 << 1) /* enable DMA */ | |
56 | #define AZX_RBCTL_OVERRUN_EN (1 << 2) /* enable overrun irq */ | |
57 | #define AZX_REG_RIRBSTS 0x5d | |
58 | #define AZX_RBSTS_IRQ (1 << 0) /* response irq */ | |
59 | #define AZX_RBSTS_OVERRUN (1 << 2) /* overrun irq */ | |
60 | #define AZX_REG_RIRBSIZE 0x5e | |
61 | ||
62 | #define AZX_REG_IC 0x60 | |
63 | #define AZX_REG_IR 0x64 | |
64 | #define AZX_REG_IRS 0x68 | |
65 | #define AZX_IRS_VALID (1<<1) | |
66 | #define AZX_IRS_BUSY (1<<0) | |
67 | ||
68 | #define AZX_REG_DPLBASE 0x70 | |
69 | #define AZX_REG_DPUBASE 0x74 | |
70 | #define AZX_DPLBASE_ENABLE 0x1 /* Enable position buffer */ | |
71 | ||
72 | /* SD offset: SDI0=0x80, SDI1=0xa0, ... SDO3=0x160 */ | |
73 | enum { SDI0, SDI1, SDI2, SDI3, SDO0, SDO1, SDO2, SDO3 }; | |
74 | ||
75 | /* stream register offsets from stream base */ | |
76 | #define AZX_REG_SD_CTL 0x00 | |
77 | #define AZX_REG_SD_STS 0x03 | |
78 | #define AZX_REG_SD_LPIB 0x04 | |
79 | #define AZX_REG_SD_CBL 0x08 | |
80 | #define AZX_REG_SD_LVI 0x0c | |
81 | #define AZX_REG_SD_FIFOW 0x0e | |
82 | #define AZX_REG_SD_FIFOSIZE 0x10 | |
83 | #define AZX_REG_SD_FORMAT 0x12 | |
84 | #define AZX_REG_SD_BDLPL 0x18 | |
85 | #define AZX_REG_SD_BDLPU 0x1c | |
86 | ||
98d8fc6c ML |
87 | /* Haswell/Broadwell display HD-A controller Extended Mode registers */ |
88 | #define AZX_REG_HSW_EM4 0x100c | |
89 | #define AZX_REG_HSW_EM5 0x1010 | |
90 | ||
14752412 TI |
91 | /* PCI space */ |
92 | #define AZX_PCIREG_TCSEL 0x44 | |
93 | ||
94 | /* | |
95 | * other constants | |
96 | */ | |
97 | ||
98 | /* max number of fragments - we may use more if allocating more pages for BDL */ | |
99 | #define BDL_SIZE 4096 | |
100 | #define AZX_MAX_BDL_ENTRIES (BDL_SIZE / 16) | |
101 | #define AZX_MAX_FRAG 32 | |
102 | /* max buffer size - no h/w limit, you can increase as you like */ | |
103 | #define AZX_MAX_BUF_SIZE (1024*1024*1024) | |
104 | ||
105 | /* RIRB int mask: overrun[2], response[0] */ | |
106 | #define RIRB_INT_RESPONSE 0x01 | |
107 | #define RIRB_INT_OVERRUN 0x04 | |
108 | #define RIRB_INT_MASK 0x05 | |
109 | ||
110 | /* STATESTS int mask: S3,SD2,SD1,SD0 */ | |
111 | #define STATESTS_INT_MASK ((1 << HDA_MAX_CODECS) - 1) | |
112 | ||
113 | /* SD_CTL bits */ | |
114 | #define SD_CTL_STREAM_RESET 0x01 /* stream reset bit */ | |
115 | #define SD_CTL_DMA_START 0x02 /* stream DMA start bit */ | |
116 | #define SD_CTL_STRIPE (3 << 16) /* stripe control */ | |
117 | #define SD_CTL_TRAFFIC_PRIO (1 << 18) /* traffic priority */ | |
118 | #define SD_CTL_DIR (1 << 19) /* bi-directional stream */ | |
119 | #define SD_CTL_STREAM_TAG_MASK (0xf << 20) | |
120 | #define SD_CTL_STREAM_TAG_SHIFT 20 | |
121 | ||
122 | /* SD_CTL and SD_STS */ | |
123 | #define SD_INT_DESC_ERR 0x10 /* descriptor error interrupt */ | |
124 | #define SD_INT_FIFO_ERR 0x08 /* FIFO error interrupt */ | |
125 | #define SD_INT_COMPLETE 0x04 /* completion interrupt */ | |
126 | #define SD_INT_MASK (SD_INT_DESC_ERR|SD_INT_FIFO_ERR|\ | |
127 | SD_INT_COMPLETE) | |
128 | ||
129 | /* SD_STS */ | |
130 | #define SD_STS_FIFO_READY 0x20 /* FIFO ready */ | |
131 | ||
132 | /* INTCTL and INTSTS */ | |
133 | #define AZX_INT_ALL_STREAM 0xff /* all stream interrupts */ | |
134 | #define AZX_INT_CTRL_EN 0x40000000 /* controller interrupt enable bit */ | |
135 | #define AZX_INT_GLOBAL_EN 0x80000000 /* global interrupt enable bit */ | |
136 | ||
137 | /* below are so far hardcoded - should read registers in future */ | |
138 | #define AZX_MAX_CORB_ENTRIES 256 | |
139 | #define AZX_MAX_RIRB_ENTRIES 256 | |
140 | ||
141 | /* | |
142 | * helpers to read the stream position | |
143 | */ | |
144 | static inline unsigned int | |
145 | snd_hdac_stream_get_pos_lpib(struct hdac_stream *stream) | |
146 | { | |
147 | return snd_hdac_stream_readl(stream, SD_LPIB); | |
148 | } | |
149 | ||
150 | static inline unsigned int | |
151 | snd_hdac_stream_get_pos_posbuf(struct hdac_stream *stream) | |
152 | { | |
153 | return le32_to_cpu(*stream->posbuf); | |
154 | } | |
155 | ||
156 | #endif /* __SOUND_HDA_REGISTER_H */ |