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Commit | Line | Data |
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b2441318 | 1 | /* SPDX-License-Identifier: GPL-2.0 */ |
e3d280fc TI |
2 | /* |
3 | * HD-audio core stuff | |
4 | */ | |
5 | ||
6 | #ifndef __SOUND_HDAUDIO_H | |
7 | #define __SOUND_HDAUDIO_H | |
8 | ||
9 | #include <linux/device.h> | |
14752412 | 10 | #include <linux/interrupt.h> |
4d024fe8 | 11 | #include <linux/io.h> |
feb20fae | 12 | #include <linux/pm_runtime.h> |
14752412 TI |
13 | #include <linux/timecounter.h> |
14 | #include <sound/core.h> | |
a6ea5fe9 | 15 | #include <sound/pcm.h> |
14752412 | 16 | #include <sound/memalloc.h> |
d068ebc2 | 17 | #include <sound/hda_verbs.h> |
98d8fc6c | 18 | #include <drm/i915_component.h> |
d068ebc2 | 19 | |
7639a06c TI |
20 | /* codec node id */ |
21 | typedef u16 hda_nid_t; | |
22 | ||
d068ebc2 | 23 | struct hdac_bus; |
14752412 | 24 | struct hdac_stream; |
d068ebc2 TI |
25 | struct hdac_device; |
26 | struct hdac_driver; | |
3256be65 | 27 | struct hdac_widget_tree; |
da23ac1e | 28 | struct hda_device_id; |
e3d280fc TI |
29 | |
30 | /* | |
31 | * exported bus type | |
32 | */ | |
33 | extern struct bus_type snd_hda_bus_type; | |
34 | ||
71fc4c7e TI |
35 | /* |
36 | * generic arrays | |
37 | */ | |
38 | struct snd_array { | |
39 | unsigned int used; | |
40 | unsigned int alloced; | |
41 | unsigned int elem_size; | |
42 | unsigned int alloc_align; | |
43 | void *list; | |
44 | }; | |
45 | ||
e3d280fc TI |
46 | /* |
47 | * HD-audio codec base device | |
48 | */ | |
49 | struct hdac_device { | |
50 | struct device dev; | |
51 | int type; | |
d068ebc2 TI |
52 | struct hdac_bus *bus; |
53 | unsigned int addr; /* codec address */ | |
54 | struct list_head list; /* list point for bus codec_list */ | |
7639a06c TI |
55 | |
56 | hda_nid_t afg; /* AFG node id */ | |
57 | hda_nid_t mfg; /* MFG node id */ | |
58 | ||
59 | /* ids */ | |
60 | unsigned int vendor_id; | |
61 | unsigned int subsystem_id; | |
62 | unsigned int revision_id; | |
63 | unsigned int afg_function_id; | |
64 | unsigned int mfg_function_id; | |
65 | unsigned int afg_unsol:1; | |
66 | unsigned int mfg_unsol:1; | |
67 | ||
68 | unsigned int power_caps; /* FG power caps */ | |
69 | ||
70 | const char *vendor_name; /* codec vendor name */ | |
71 | const char *chip_name; /* codec chip name */ | |
72 | ||
05852448 TI |
73 | /* verb exec op override */ |
74 | int (*exec_verb)(struct hdac_device *dev, unsigned int cmd, | |
75 | unsigned int flags, unsigned int *res); | |
76 | ||
7639a06c TI |
77 | /* widgets */ |
78 | unsigned int num_nodes; | |
79 | hda_nid_t start_nid, end_nid; | |
80 | ||
81 | /* misc flags */ | |
82 | atomic_t in_pm; /* suspend/resume being performed */ | |
3256be65 TI |
83 | |
84 | /* sysfs */ | |
ed180abb | 85 | struct mutex widget_lock; |
3256be65 | 86 | struct hdac_widget_tree *widgets; |
4d75faa0 TI |
87 | |
88 | /* regmap */ | |
89 | struct regmap *regmap; | |
1a462be5 | 90 | struct mutex regmap_lock; |
5e56bcea | 91 | struct snd_array vendor_verbs; |
4d75faa0 | 92 | bool lazy_cache:1; /* don't wake up for writes */ |
faa75f8a | 93 | bool caps_overwriting:1; /* caps overwrite being in process */ |
40ba66a7 | 94 | bool cache_coef:1; /* cache COEF read/write too */ |
e3d280fc TI |
95 | }; |
96 | ||
97 | /* device/driver type used for matching */ | |
98 | enum { | |
99 | HDA_DEV_CORE, | |
100 | HDA_DEV_LEGACY, | |
c1cc18b1 | 101 | HDA_DEV_ASOC, |
e3d280fc TI |
102 | }; |
103 | ||
d82b51c8 PLB |
104 | enum { |
105 | SND_SKL_PCI_BIND_AUTO, /* automatic selection based on pci class */ | |
106 | SND_SKL_PCI_BIND_LEGACY,/* bind only with legacy driver */ | |
107 | SND_SKL_PCI_BIND_ASOC /* bind only with ASoC driver */ | |
108 | }; | |
109 | ||
7639a06c TI |
110 | /* direction */ |
111 | enum { | |
112 | HDA_INPUT, HDA_OUTPUT | |
113 | }; | |
114 | ||
e3d280fc TI |
115 | #define dev_to_hdac_dev(_dev) container_of(_dev, struct hdac_device, dev) |
116 | ||
7639a06c TI |
117 | int snd_hdac_device_init(struct hdac_device *dev, struct hdac_bus *bus, |
118 | const char *name, unsigned int addr); | |
119 | void snd_hdac_device_exit(struct hdac_device *dev); | |
3256be65 TI |
120 | int snd_hdac_device_register(struct hdac_device *codec); |
121 | void snd_hdac_device_unregister(struct hdac_device *codec); | |
ded255be | 122 | int snd_hdac_device_set_chip_name(struct hdac_device *codec, const char *name); |
4f9e0c38 | 123 | int snd_hdac_codec_modalias(struct hdac_device *hdac, char *buf, size_t size); |
7639a06c | 124 | |
774a075a | 125 | int snd_hdac_refresh_widgets(struct hdac_device *codec); |
7639a06c | 126 | |
7639a06c TI |
127 | int snd_hdac_read(struct hdac_device *codec, hda_nid_t nid, |
128 | unsigned int verb, unsigned int parm, unsigned int *res); | |
01ed3c06 TI |
129 | int _snd_hdac_read_parm(struct hdac_device *codec, hda_nid_t nid, int parm, |
130 | unsigned int *res); | |
9ba17b4d TI |
131 | int snd_hdac_read_parm_uncached(struct hdac_device *codec, hda_nid_t nid, |
132 | int parm); | |
faa75f8a TI |
133 | int snd_hdac_override_parm(struct hdac_device *codec, hda_nid_t nid, |
134 | unsigned int parm, unsigned int val); | |
7639a06c TI |
135 | int snd_hdac_get_connections(struct hdac_device *codec, hda_nid_t nid, |
136 | hda_nid_t *conn_list, int max_conns); | |
137 | int snd_hdac_get_sub_nodes(struct hdac_device *codec, hda_nid_t nid, | |
138 | hda_nid_t *start_id); | |
b7d023e1 TI |
139 | unsigned int snd_hdac_calc_stream_format(unsigned int rate, |
140 | unsigned int channels, | |
a6ea5fe9 | 141 | snd_pcm_format_t format, |
b7d023e1 TI |
142 | unsigned int maxbps, |
143 | unsigned short spdif_ctls); | |
144 | int snd_hdac_query_supported_pcm(struct hdac_device *codec, hda_nid_t nid, | |
145 | u32 *ratesp, u64 *formatsp, unsigned int *bpsp); | |
146 | bool snd_hdac_is_supported_format(struct hdac_device *codec, hda_nid_t nid, | |
147 | unsigned int format); | |
7639a06c | 148 | |
1b5e6167 SP |
149 | int snd_hdac_codec_read(struct hdac_device *hdac, hda_nid_t nid, |
150 | int flags, unsigned int verb, unsigned int parm); | |
151 | int snd_hdac_codec_write(struct hdac_device *hdac, hda_nid_t nid, | |
152 | int flags, unsigned int verb, unsigned int parm); | |
153 | bool snd_hdac_check_power_state(struct hdac_device *hdac, | |
154 | hda_nid_t nid, unsigned int target_state); | |
09787492 AK |
155 | unsigned int snd_hdac_sync_power_state(struct hdac_device *hdac, |
156 | hda_nid_t nid, unsigned int target_state); | |
01ed3c06 TI |
157 | /** |
158 | * snd_hdac_read_parm - read a codec parameter | |
159 | * @codec: the codec object | |
160 | * @nid: NID to read a parameter | |
161 | * @parm: parameter to read | |
162 | * | |
163 | * Returns -1 for error. If you need to distinguish the error more | |
164 | * strictly, use _snd_hdac_read_parm() directly. | |
165 | */ | |
166 | static inline int snd_hdac_read_parm(struct hdac_device *codec, hda_nid_t nid, | |
167 | int parm) | |
168 | { | |
169 | unsigned int val; | |
170 | ||
171 | return _snd_hdac_read_parm(codec, nid, parm, &val) < 0 ? -1 : val; | |
172 | } | |
173 | ||
7639a06c | 174 | #ifdef CONFIG_PM |
fbce23a0 TI |
175 | int snd_hdac_power_up(struct hdac_device *codec); |
176 | int snd_hdac_power_down(struct hdac_device *codec); | |
177 | int snd_hdac_power_up_pm(struct hdac_device *codec); | |
178 | int snd_hdac_power_down_pm(struct hdac_device *codec); | |
fc4f000b | 179 | int snd_hdac_keep_power_up(struct hdac_device *codec); |
feb20fae TI |
180 | |
181 | /* call this at entering into suspend/resume callbacks in codec driver */ | |
182 | static inline void snd_hdac_enter_pm(struct hdac_device *codec) | |
183 | { | |
184 | atomic_inc(&codec->in_pm); | |
185 | } | |
186 | ||
187 | /* call this at leaving from suspend/resume callbacks in codec driver */ | |
188 | static inline void snd_hdac_leave_pm(struct hdac_device *codec) | |
189 | { | |
190 | atomic_dec(&codec->in_pm); | |
191 | } | |
192 | ||
193 | static inline bool snd_hdac_is_in_pm(struct hdac_device *codec) | |
194 | { | |
195 | return atomic_read(&codec->in_pm); | |
196 | } | |
197 | ||
198 | static inline bool snd_hdac_is_power_on(struct hdac_device *codec) | |
199 | { | |
200 | return !pm_runtime_suspended(&codec->dev); | |
201 | } | |
7639a06c | 202 | #else |
fbce23a0 TI |
203 | static inline int snd_hdac_power_up(struct hdac_device *codec) { return 0; } |
204 | static inline int snd_hdac_power_down(struct hdac_device *codec) { return 0; } | |
205 | static inline int snd_hdac_power_up_pm(struct hdac_device *codec) { return 0; } | |
206 | static inline int snd_hdac_power_down_pm(struct hdac_device *codec) { return 0; } | |
fc4f000b | 207 | static inline int snd_hdac_keep_power_up(struct hdac_device *codec) { return 0; } |
feb20fae TI |
208 | static inline void snd_hdac_enter_pm(struct hdac_device *codec) {} |
209 | static inline void snd_hdac_leave_pm(struct hdac_device *codec) {} | |
79263c3b JY |
210 | static inline bool snd_hdac_is_in_pm(struct hdac_device *codec) { return false; } |
211 | static inline bool snd_hdac_is_power_on(struct hdac_device *codec) { return true; } | |
7639a06c TI |
212 | #endif |
213 | ||
e3d280fc TI |
214 | /* |
215 | * HD-audio codec base driver | |
216 | */ | |
217 | struct hdac_driver { | |
218 | struct device_driver driver; | |
219 | int type; | |
ec71efc9 | 220 | const struct hda_device_id *id_table; |
e3d280fc | 221 | int (*match)(struct hdac_device *dev, struct hdac_driver *drv); |
d068ebc2 | 222 | void (*unsol_event)(struct hdac_device *dev, unsigned int event); |
e1df9317 RU |
223 | |
224 | /* fields used by ext bus APIs */ | |
225 | int (*probe)(struct hdac_device *dev); | |
226 | int (*remove)(struct hdac_device *dev); | |
227 | void (*shutdown)(struct hdac_device *dev); | |
e3d280fc TI |
228 | }; |
229 | ||
230 | #define drv_to_hdac_driver(_drv) container_of(_drv, struct hdac_driver, driver) | |
231 | ||
ec71efc9 VK |
232 | const struct hda_device_id * |
233 | hdac_get_device_id(struct hdac_device *hdev, struct hdac_driver *drv); | |
234 | ||
d068ebc2 | 235 | /* |
14752412 | 236 | * Bus verb operators |
d068ebc2 TI |
237 | */ |
238 | struct hdac_bus_ops { | |
239 | /* send a single command */ | |
240 | int (*command)(struct hdac_bus *bus, unsigned int cmd); | |
241 | /* get a response from the last command */ | |
242 | int (*get_response)(struct hdac_bus *bus, unsigned int addr, | |
243 | unsigned int *res); | |
f9e5fd1b KV |
244 | /* notify of codec link power-up/down */ |
245 | void (*link_power)(struct hdac_device *hdev, bool enable); | |
d068ebc2 TI |
246 | }; |
247 | ||
cb04ba33 RU |
248 | /* |
249 | * ops used for ASoC HDA codec drivers | |
250 | */ | |
251 | struct hdac_ext_bus_ops { | |
252 | int (*hdev_attach)(struct hdac_device *hdev); | |
253 | int (*hdev_detach)(struct hdac_device *hdev); | |
254 | }; | |
255 | ||
d068ebc2 | 256 | #define HDA_UNSOL_QUEUE_SIZE 64 |
14752412 TI |
257 | #define HDA_MAX_CODECS 8 /* limit by controller side */ |
258 | ||
14752412 TI |
259 | /* |
260 | * CORB/RIRB | |
261 | * | |
262 | * Each CORB entry is 4byte, RIRB is 8byte | |
263 | */ | |
264 | struct hdac_rb { | |
265 | __le32 *buf; /* virtual address of CORB/RIRB buffer */ | |
266 | dma_addr_t addr; /* physical address of CORB/RIRB buffer */ | |
267 | unsigned short rp, wp; /* RIRB read/write pointers */ | |
268 | int cmds[HDA_MAX_CODECS]; /* number of pending requests */ | |
269 | u32 res[HDA_MAX_CODECS]; /* last read value */ | |
270 | }; | |
d068ebc2 | 271 | |
14752412 TI |
272 | /* |
273 | * HD-audio bus base driver | |
6720b384 VK |
274 | * |
275 | * @ppcap: pp capabilities pointer | |
276 | * @spbcap: SPIB capabilities pointer | |
277 | * @mlcap: MultiLink capabilities pointer | |
278 | * @gtscap: gts capabilities pointer | |
279 | * @drsmcap: dma resume capabilities pointer | |
76f56fae RU |
280 | * @num_streams: streams supported |
281 | * @idx: HDA link index | |
282 | * @hlink_list: link list of HDA links | |
e61ab9f0 | 283 | * @lock: lock for link and display power mgmt |
76f56fae | 284 | * @cmd_dma_state: state of cmd DMAs: CORB and RIRB |
14752412 | 285 | */ |
d068ebc2 TI |
286 | struct hdac_bus { |
287 | struct device *dev; | |
288 | const struct hdac_bus_ops *ops; | |
cb04ba33 | 289 | const struct hdac_ext_bus_ops *ext_ops; |
14752412 TI |
290 | |
291 | /* h/w resources */ | |
292 | unsigned long addr; | |
293 | void __iomem *remap_addr; | |
294 | int irq; | |
d068ebc2 | 295 | |
6720b384 VK |
296 | void __iomem *ppcap; |
297 | void __iomem *spbcap; | |
298 | void __iomem *mlcap; | |
299 | void __iomem *gtscap; | |
300 | void __iomem *drsmcap; | |
301 | ||
d068ebc2 TI |
302 | /* codec linked list */ |
303 | struct list_head codec_list; | |
304 | unsigned int num_codecs; | |
305 | ||
306 | /* link caddr -> codec */ | |
307 | struct hdac_device *caddr_tbl[HDA_MAX_CODEC_ADDRESS + 1]; | |
308 | ||
309 | /* unsolicited event queue */ | |
310 | u32 unsol_queue[HDA_UNSOL_QUEUE_SIZE * 2]; /* ring buffer */ | |
311 | unsigned int unsol_rp, unsol_wp; | |
312 | struct work_struct unsol_work; | |
313 | ||
14752412 TI |
314 | /* bit flags of detected codecs */ |
315 | unsigned long codec_mask; | |
316 | ||
d068ebc2 TI |
317 | /* bit flags of powered codecs */ |
318 | unsigned long codec_powered; | |
319 | ||
14752412 TI |
320 | /* CORB/RIRB */ |
321 | struct hdac_rb corb; | |
322 | struct hdac_rb rirb; | |
323 | unsigned int last_cmd[HDA_MAX_CODECS]; /* last sent command */ | |
88452da9 | 324 | wait_queue_head_t rirb_wq; |
14752412 TI |
325 | |
326 | /* CORB/RIRB and position buffers */ | |
327 | struct snd_dma_buffer rb; | |
328 | struct snd_dma_buffer posbuf; | |
619a1f19 | 329 | int dma_type; /* SNDRV_DMA_TYPE_XXX for CORB/RIRB */ |
14752412 TI |
330 | |
331 | /* hdac_stream linked list */ | |
332 | struct list_head stream_list; | |
333 | ||
334 | /* operation state */ | |
335 | bool chip_init:1; /* h/w initialized */ | |
336 | ||
337 | /* behavior flags */ | |
4d024fe8 | 338 | bool aligned_mmio:1; /* aligned MMIO access */ |
d068ebc2 | 339 | bool sync_write:1; /* sync after verb write */ |
14752412 TI |
340 | bool use_posbuf:1; /* use position buffer */ |
341 | bool snoop:1; /* enable snooping */ | |
342 | bool align_bdle_4k:1; /* BDLE align 4K boundary */ | |
343 | bool reverse_assign:1; /* assign devices in reverse order */ | |
344 | bool corbrp_self_clear:1; /* CORBRP clears itself after reset */ | |
8af42130 | 345 | bool polling_mode:1; |
5f2cb361 | 346 | bool needs_damn_long_delay:1; |
8af42130 BL |
347 | |
348 | int poll_count; | |
14752412 TI |
349 | |
350 | int bdl_pos_adj; /* BDL position adjustment */ | |
d068ebc2 | 351 | |
4106820b MK |
352 | /* delay time in us for dma stop */ |
353 | unsigned int dma_stop_delay; | |
354 | ||
d068ebc2 | 355 | /* locks */ |
14752412 | 356 | spinlock_t reg_lock; |
d068ebc2 | 357 | struct mutex cmd_mutex; |
e61ab9f0 | 358 | struct mutex lock; |
98d8fc6c | 359 | |
ae891abe TI |
360 | /* DRM component interface */ |
361 | struct drm_audio_component *audio_component; | |
029d92c2 | 362 | long display_power_status; |
d31c85fc | 363 | unsigned long display_power_active; |
76f56fae RU |
364 | |
365 | /* parameters required for enhanced capabilities */ | |
366 | int num_streams; | |
367 | int idx; | |
368 | ||
e61ab9f0 | 369 | /* link management */ |
76f56fae | 370 | struct list_head hlink_list; |
76f56fae | 371 | bool cmd_dma_state; |
67ae482a SP |
372 | |
373 | /* factor used to derive STRIPE control value */ | |
374 | unsigned int sdo_limit; | |
d068ebc2 TI |
375 | }; |
376 | ||
377 | int snd_hdac_bus_init(struct hdac_bus *bus, struct device *dev, | |
19abfefd | 378 | const struct hdac_bus_ops *ops); |
d068ebc2 | 379 | void snd_hdac_bus_exit(struct hdac_bus *bus); |
d068ebc2 TI |
380 | int snd_hdac_bus_exec_verb_unlocked(struct hdac_bus *bus, unsigned int addr, |
381 | unsigned int cmd, unsigned int *res); | |
d068ebc2 | 382 | |
f9e5fd1b KV |
383 | void snd_hdac_codec_link_up(struct hdac_device *codec); |
384 | void snd_hdac_codec_link_down(struct hdac_device *codec); | |
7639a06c | 385 | |
14752412 TI |
386 | int snd_hdac_bus_send_cmd(struct hdac_bus *bus, unsigned int val); |
387 | int snd_hdac_bus_get_response(struct hdac_bus *bus, unsigned int addr, | |
388 | unsigned int *res); | |
6720b384 | 389 | int snd_hdac_bus_parse_capabilities(struct hdac_bus *bus); |
14752412 TI |
390 | |
391 | bool snd_hdac_bus_init_chip(struct hdac_bus *bus, bool full_reset); | |
392 | void snd_hdac_bus_stop_chip(struct hdac_bus *bus); | |
393 | void snd_hdac_bus_init_cmd_io(struct hdac_bus *bus); | |
394 | void snd_hdac_bus_stop_cmd_io(struct hdac_bus *bus); | |
395 | void snd_hdac_bus_enter_link_reset(struct hdac_bus *bus); | |
396 | void snd_hdac_bus_exit_link_reset(struct hdac_bus *bus); | |
75383f8d | 397 | int snd_hdac_bus_reset_link(struct hdac_bus *bus, bool full_reset); |
f9e5fd1b | 398 | void snd_hdac_bus_link_power(struct hdac_device *hdev, bool enable); |
14752412 TI |
399 | |
400 | void snd_hdac_bus_update_rirb(struct hdac_bus *bus); | |
473f4145 | 401 | int snd_hdac_bus_handle_stream_irq(struct hdac_bus *bus, unsigned int status, |
14752412 TI |
402 | void (*ack)(struct hdac_bus *, |
403 | struct hdac_stream *)); | |
404 | ||
304dad30 JK |
405 | int snd_hdac_bus_alloc_stream_pages(struct hdac_bus *bus); |
406 | void snd_hdac_bus_free_stream_pages(struct hdac_bus *bus); | |
407 | ||
19abfefd TI |
408 | #ifdef CONFIG_SND_HDA_ALIGNED_MMIO |
409 | unsigned int snd_hdac_aligned_read(void __iomem *addr, unsigned int mask); | |
410 | void snd_hdac_aligned_write(unsigned int val, void __iomem *addr, | |
411 | unsigned int mask); | |
4d024fe8 TI |
412 | #define snd_hdac_aligned_mmio(bus) (bus)->aligned_mmio |
413 | #else | |
414 | #define snd_hdac_aligned_mmio(bus) false | |
415 | #define snd_hdac_aligned_read(addr, mask) 0 | |
416 | #define snd_hdac_aligned_write(val, addr, mask) do {} while (0) | |
417 | #endif | |
418 | ||
419 | static inline void snd_hdac_reg_writeb(struct hdac_bus *bus, void __iomem *addr, | |
420 | u8 val) | |
421 | { | |
422 | if (snd_hdac_aligned_mmio(bus)) | |
423 | snd_hdac_aligned_write(val, addr, 0xff); | |
424 | else | |
425 | writeb(val, addr); | |
426 | } | |
427 | ||
428 | static inline void snd_hdac_reg_writew(struct hdac_bus *bus, void __iomem *addr, | |
429 | u16 val) | |
430 | { | |
431 | if (snd_hdac_aligned_mmio(bus)) | |
432 | snd_hdac_aligned_write(val, addr, 0xffff); | |
433 | else | |
434 | writew(val, addr); | |
435 | } | |
436 | ||
437 | static inline u8 snd_hdac_reg_readb(struct hdac_bus *bus, void __iomem *addr) | |
438 | { | |
439 | return snd_hdac_aligned_mmio(bus) ? | |
440 | snd_hdac_aligned_read(addr, 0xff) : readb(addr); | |
441 | } | |
442 | ||
443 | static inline u16 snd_hdac_reg_readw(struct hdac_bus *bus, void __iomem *addr) | |
444 | { | |
445 | return snd_hdac_aligned_mmio(bus) ? | |
446 | snd_hdac_aligned_read(addr, 0xffff) : readw(addr); | |
447 | } | |
448 | ||
449 | #define snd_hdac_reg_writel(bus, addr, val) writel(val, addr) | |
450 | #define snd_hdac_reg_readl(bus, addr) readl(addr) | |
19abfefd | 451 | |
14752412 TI |
452 | /* |
453 | * macros for easy use | |
454 | */ | |
2c1f8138 | 455 | #define _snd_hdac_chip_writeb(chip, reg, value) \ |
4d024fe8 | 456 | snd_hdac_reg_writeb(chip, (chip)->remap_addr + (reg), value) |
2c1f8138 | 457 | #define _snd_hdac_chip_readb(chip, reg) \ |
4d024fe8 | 458 | snd_hdac_reg_readb(chip, (chip)->remap_addr + (reg)) |
2c1f8138 | 459 | #define _snd_hdac_chip_writew(chip, reg, value) \ |
4d024fe8 | 460 | snd_hdac_reg_writew(chip, (chip)->remap_addr + (reg), value) |
2c1f8138 | 461 | #define _snd_hdac_chip_readw(chip, reg) \ |
4d024fe8 | 462 | snd_hdac_reg_readw(chip, (chip)->remap_addr + (reg)) |
2c1f8138 | 463 | #define _snd_hdac_chip_writel(chip, reg, value) \ |
4d024fe8 | 464 | snd_hdac_reg_writel(chip, (chip)->remap_addr + (reg), value) |
2c1f8138 | 465 | #define _snd_hdac_chip_readl(chip, reg) \ |
4d024fe8 | 466 | snd_hdac_reg_readl(chip, (chip)->remap_addr + (reg)) |
14752412 TI |
467 | |
468 | /* read/write a register, pass without AZX_REG_ prefix */ | |
469 | #define snd_hdac_chip_writel(chip, reg, value) \ | |
2c1f8138 | 470 | _snd_hdac_chip_writel(chip, AZX_REG_ ## reg, value) |
14752412 | 471 | #define snd_hdac_chip_writew(chip, reg, value) \ |
2c1f8138 | 472 | _snd_hdac_chip_writew(chip, AZX_REG_ ## reg, value) |
14752412 | 473 | #define snd_hdac_chip_writeb(chip, reg, value) \ |
2c1f8138 | 474 | _snd_hdac_chip_writeb(chip, AZX_REG_ ## reg, value) |
14752412 | 475 | #define snd_hdac_chip_readl(chip, reg) \ |
2c1f8138 | 476 | _snd_hdac_chip_readl(chip, AZX_REG_ ## reg) |
14752412 | 477 | #define snd_hdac_chip_readw(chip, reg) \ |
2c1f8138 | 478 | _snd_hdac_chip_readw(chip, AZX_REG_ ## reg) |
14752412 | 479 | #define snd_hdac_chip_readb(chip, reg) \ |
2c1f8138 | 480 | _snd_hdac_chip_readb(chip, AZX_REG_ ## reg) |
14752412 TI |
481 | |
482 | /* update a register, pass without AZX_REG_ prefix */ | |
483 | #define snd_hdac_chip_updatel(chip, reg, mask, val) \ | |
484 | snd_hdac_chip_writel(chip, reg, \ | |
485 | (snd_hdac_chip_readl(chip, reg) & ~(mask)) | (val)) | |
486 | #define snd_hdac_chip_updatew(chip, reg, mask, val) \ | |
487 | snd_hdac_chip_writew(chip, reg, \ | |
488 | (snd_hdac_chip_readw(chip, reg) & ~(mask)) | (val)) | |
489 | #define snd_hdac_chip_updateb(chip, reg, mask, val) \ | |
490 | snd_hdac_chip_writeb(chip, reg, \ | |
491 | (snd_hdac_chip_readb(chip, reg) & ~(mask)) | (val)) | |
492 | ||
493 | /* | |
494 | * HD-audio stream | |
495 | */ | |
496 | struct hdac_stream { | |
497 | struct hdac_bus *bus; | |
498 | struct snd_dma_buffer bdl; /* BDL buffer */ | |
499 | __le32 *posbuf; /* position buffer pointer */ | |
500 | int direction; /* playback / capture (SNDRV_PCM_STREAM_*) */ | |
501 | ||
502 | unsigned int bufsize; /* size of the play buffer in bytes */ | |
503 | unsigned int period_bytes; /* size of the period in bytes */ | |
504 | unsigned int frags; /* number for period in the play buffer */ | |
505 | unsigned int fifo_size; /* FIFO size */ | |
506 | ||
507 | void __iomem *sd_addr; /* stream descriptor pointer */ | |
508 | ||
509 | u32 sd_int_sta_mask; /* stream int status mask */ | |
510 | ||
511 | /* pcm support */ | |
512 | struct snd_pcm_substream *substream; /* assigned substream, | |
513 | * set in PCM open | |
514 | */ | |
4a9ce6e4 | 515 | struct snd_compr_stream *cstream; |
14752412 TI |
516 | unsigned int format_val; /* format value to be set in the |
517 | * controller and the codec | |
518 | */ | |
519 | unsigned char stream_tag; /* assigned stream */ | |
520 | unsigned char index; /* stream index */ | |
521 | int assigned_key; /* last device# key assigned to */ | |
522 | ||
523 | bool opened:1; | |
524 | bool running:1; | |
6d23c8f5 | 525 | bool prepared:1; |
14752412 | 526 | bool no_period_wakeup:1; |
8f3f600b | 527 | bool locked:1; |
e38e486d | 528 | bool stripe:1; /* apply stripe control */ |
14752412 | 529 | |
4a9ce6e4 | 530 | u64 curr_pos; |
14752412 TI |
531 | /* timestamp */ |
532 | unsigned long start_wallclk; /* start + minimum wallclk */ | |
533 | unsigned long period_wallclk; /* wallclk for period */ | |
534 | struct timecounter tc; | |
535 | struct cyclecounter cc; | |
536 | int delay_negative_threshold; | |
537 | ||
538 | struct list_head list; | |
8f3f600b TI |
539 | #ifdef CONFIG_SND_HDA_DSP_LOADER |
540 | /* DSP access mutex */ | |
541 | struct mutex dsp_mutex; | |
542 | #endif | |
14752412 TI |
543 | }; |
544 | ||
545 | void snd_hdac_stream_init(struct hdac_bus *bus, struct hdac_stream *azx_dev, | |
546 | int idx, int direction, int tag); | |
547 | struct hdac_stream *snd_hdac_stream_assign(struct hdac_bus *bus, | |
548 | struct snd_pcm_substream *substream); | |
549 | void snd_hdac_stream_release(struct hdac_stream *azx_dev); | |
4308c9b0 JK |
550 | struct hdac_stream *snd_hdac_get_stream(struct hdac_bus *bus, |
551 | int dir, int stream_tag); | |
14752412 TI |
552 | |
553 | int snd_hdac_stream_setup(struct hdac_stream *azx_dev); | |
554 | void snd_hdac_stream_cleanup(struct hdac_stream *azx_dev); | |
555 | int snd_hdac_stream_setup_periods(struct hdac_stream *azx_dev); | |
86f6501b JK |
556 | int snd_hdac_stream_set_params(struct hdac_stream *azx_dev, |
557 | unsigned int format_val); | |
14752412 TI |
558 | void snd_hdac_stream_start(struct hdac_stream *azx_dev, bool fresh_start); |
559 | void snd_hdac_stream_clear(struct hdac_stream *azx_dev); | |
560 | void snd_hdac_stream_stop(struct hdac_stream *azx_dev); | |
561 | void snd_hdac_stream_reset(struct hdac_stream *azx_dev); | |
562 | void snd_hdac_stream_sync_trigger(struct hdac_stream *azx_dev, bool set, | |
563 | unsigned int streams, unsigned int reg); | |
564 | void snd_hdac_stream_sync(struct hdac_stream *azx_dev, bool start, | |
565 | unsigned int streams); | |
566 | void snd_hdac_stream_timecounter_init(struct hdac_stream *azx_dev, | |
567 | unsigned int streams); | |
5dd3d271 SP |
568 | int snd_hdac_get_stream_stripe_ctl(struct hdac_bus *bus, |
569 | struct snd_pcm_substream *substream); | |
570 | ||
14752412 TI |
571 | /* |
572 | * macros for easy use | |
573 | */ | |
14752412 TI |
574 | /* read/write a register, pass without AZX_REG_ prefix */ |
575 | #define snd_hdac_stream_writel(dev, reg, value) \ | |
4d024fe8 | 576 | snd_hdac_reg_writel((dev)->bus, (dev)->sd_addr + AZX_REG_ ## reg, value) |
14752412 | 577 | #define snd_hdac_stream_writew(dev, reg, value) \ |
4d024fe8 | 578 | snd_hdac_reg_writew((dev)->bus, (dev)->sd_addr + AZX_REG_ ## reg, value) |
14752412 | 579 | #define snd_hdac_stream_writeb(dev, reg, value) \ |
4d024fe8 | 580 | snd_hdac_reg_writeb((dev)->bus, (dev)->sd_addr + AZX_REG_ ## reg, value) |
14752412 | 581 | #define snd_hdac_stream_readl(dev, reg) \ |
4d024fe8 | 582 | snd_hdac_reg_readl((dev)->bus, (dev)->sd_addr + AZX_REG_ ## reg) |
14752412 | 583 | #define snd_hdac_stream_readw(dev, reg) \ |
4d024fe8 | 584 | snd_hdac_reg_readw((dev)->bus, (dev)->sd_addr + AZX_REG_ ## reg) |
14752412 | 585 | #define snd_hdac_stream_readb(dev, reg) \ |
4d024fe8 | 586 | snd_hdac_reg_readb((dev)->bus, (dev)->sd_addr + AZX_REG_ ## reg) |
14752412 TI |
587 | |
588 | /* update a register, pass without AZX_REG_ prefix */ | |
589 | #define snd_hdac_stream_updatel(dev, reg, mask, val) \ | |
590 | snd_hdac_stream_writel(dev, reg, \ | |
591 | (snd_hdac_stream_readl(dev, reg) & \ | |
592 | ~(mask)) | (val)) | |
593 | #define snd_hdac_stream_updatew(dev, reg, mask, val) \ | |
594 | snd_hdac_stream_writew(dev, reg, \ | |
595 | (snd_hdac_stream_readw(dev, reg) & \ | |
596 | ~(mask)) | (val)) | |
597 | #define snd_hdac_stream_updateb(dev, reg, mask, val) \ | |
598 | snd_hdac_stream_writeb(dev, reg, \ | |
599 | (snd_hdac_stream_readb(dev, reg) & \ | |
600 | ~(mask)) | (val)) | |
601 | ||
8f3f600b TI |
602 | #ifdef CONFIG_SND_HDA_DSP_LOADER |
603 | /* DSP lock helpers */ | |
604 | #define snd_hdac_dsp_lock_init(dev) mutex_init(&(dev)->dsp_mutex) | |
605 | #define snd_hdac_dsp_lock(dev) mutex_lock(&(dev)->dsp_mutex) | |
606 | #define snd_hdac_dsp_unlock(dev) mutex_unlock(&(dev)->dsp_mutex) | |
607 | #define snd_hdac_stream_is_locked(dev) ((dev)->locked) | |
608 | /* DSP loader helpers */ | |
609 | int snd_hdac_dsp_prepare(struct hdac_stream *azx_dev, unsigned int format, | |
610 | unsigned int byte_size, struct snd_dma_buffer *bufp); | |
611 | void snd_hdac_dsp_trigger(struct hdac_stream *azx_dev, bool start); | |
612 | void snd_hdac_dsp_cleanup(struct hdac_stream *azx_dev, | |
613 | struct snd_dma_buffer *dmab); | |
614 | #else /* CONFIG_SND_HDA_DSP_LOADER */ | |
615 | #define snd_hdac_dsp_lock_init(dev) do {} while (0) | |
616 | #define snd_hdac_dsp_lock(dev) do {} while (0) | |
617 | #define snd_hdac_dsp_unlock(dev) do {} while (0) | |
618 | #define snd_hdac_stream_is_locked(dev) 0 | |
619 | ||
620 | static inline int | |
621 | snd_hdac_dsp_prepare(struct hdac_stream *azx_dev, unsigned int format, | |
622 | unsigned int byte_size, struct snd_dma_buffer *bufp) | |
623 | { | |
624 | return 0; | |
625 | } | |
626 | ||
627 | static inline void snd_hdac_dsp_trigger(struct hdac_stream *azx_dev, bool start) | |
628 | { | |
629 | } | |
630 | ||
631 | static inline void snd_hdac_dsp_cleanup(struct hdac_stream *azx_dev, | |
632 | struct snd_dma_buffer *dmab) | |
633 | { | |
634 | } | |
635 | #endif /* CONFIG_SND_HDA_DSP_LOADER */ | |
636 | ||
637 | ||
71fc4c7e TI |
638 | /* |
639 | * generic array helpers | |
640 | */ | |
641 | void *snd_array_new(struct snd_array *array); | |
642 | void snd_array_free(struct snd_array *array); | |
643 | static inline void snd_array_init(struct snd_array *array, unsigned int size, | |
644 | unsigned int align) | |
645 | { | |
646 | array->elem_size = size; | |
647 | array->alloc_align = align; | |
648 | } | |
649 | ||
650 | static inline void *snd_array_elem(struct snd_array *array, unsigned int idx) | |
651 | { | |
652 | return array->list + idx * array->elem_size; | |
653 | } | |
654 | ||
655 | static inline unsigned int snd_array_index(struct snd_array *array, void *ptr) | |
656 | { | |
657 | return (unsigned long)(ptr - array->list) / array->elem_size; | |
658 | } | |
659 | ||
a9c2dfc8 TI |
660 | /* a helper macro to iterate for each snd_array element */ |
661 | #define snd_array_for_each(array, idx, ptr) \ | |
662 | for ((idx) = 0, (ptr) = (array)->list; (idx) < (array)->used; \ | |
663 | (ptr) = snd_array_elem(array, ++(idx))) | |
664 | ||
e3d280fc | 665 | #endif /* __SOUND_HDAUDIO_H */ |