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[mirror_ubuntu-bionic-kernel.git] / include / sound / hdaudio.h
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b2441318 1/* SPDX-License-Identifier: GPL-2.0 */
e3d280fc
TI		 2/*
3 * HD-audio core stuff
4 */
5
6#ifndef __SOUND_HDAUDIO_H
7#define __SOUND_HDAUDIO_H
8
9#include <linux/device.h>
14752412
TI		 10#include <linux/interrupt.h>
11#include <linux/timecounter.h>
12#include <sound/core.h>
13#include <sound/memalloc.h>
d068ebc2 14#include <sound/hda_verbs.h>
98d8fc6c 15#include <drm/i915_component.h>
d068ebc2 16
7639a06c
TI		 17/* codec node id */
18typedef u16 hda_nid_t;
19
d068ebc2 20struct hdac_bus;
14752412 21struct hdac_stream;
d068ebc2
TI		 22struct hdac_device;
23struct hdac_driver;
3256be65 24struct hdac_widget_tree;
da23ac1e 25struct hda_device_id;
e3d280fc
TI		 26
27/*
28 * exported bus type
29 */
30extern struct bus_type snd_hda_bus_type;
31
71fc4c7e
TI		 32/*
33 * generic arrays
34 */
35struct snd_array {
36 unsigned int used;
37 unsigned int alloced;
38 unsigned int elem_size;
39 unsigned int alloc_align;
40 void *list;
41};
42
e3d280fc
TI		 43/*
44 * HD-audio codec base device
45 */
46struct hdac_device {
47 struct device dev;
48 int type;
d068ebc2
TI		 49 struct hdac_bus *bus;
50 unsigned int addr; /* codec address */
51 struct list_head list; /* list point for bus codec_list */
7639a06c
TI		 52
53 hda_nid_t afg; /* AFG node id */
54 hda_nid_t mfg; /* MFG node id */
55
56 /* ids */
57 unsigned int vendor_id;
58 unsigned int subsystem_id;
59 unsigned int revision_id;
60 unsigned int afg_function_id;
61 unsigned int mfg_function_id;
62 unsigned int afg_unsol:1;
63 unsigned int mfg_unsol:1;
64
65 unsigned int power_caps; /* FG power caps */
66
67 const char *vendor_name; /* codec vendor name */
68 const char *chip_name; /* codec chip name */
69
05852448
TI		 70 /* verb exec op override */
71 int (*exec_verb)(struct hdac_device *dev, unsigned int cmd,
72 unsigned int flags, unsigned int *res);
73
7639a06c
TI		 74 /* widgets */
75 unsigned int num_nodes;
76 hda_nid_t start_nid, end_nid;
77
78 /* misc flags */
79 atomic_t in_pm; /* suspend/resume being performed */
a5e7e07c 80 bool link_power_control:1;
3256be65
TI		 81
82 /* sysfs */
83 struct hdac_widget_tree *widgets;
4d75faa0
TI		 84
85 /* regmap */
86 struct regmap *regmap;
5e56bcea 87 struct snd_array vendor_verbs;
4d75faa0 88 bool lazy_cache:1; /* don't wake up for writes */
faa75f8a 89 bool caps_overwriting:1; /* caps overwrite being in process */
40ba66a7 90 bool cache_coef:1; /* cache COEF read/write too */
e3d280fc
TI		 91};
92
93/* device/driver type used for matching */
94enum {
95 HDA_DEV_CORE,
96 HDA_DEV_LEGACY,
c1cc18b1 97 HDA_DEV_ASOC,
e3d280fc
TI		 98};
99
7639a06c
TI		 100/* direction */
101enum {
102 HDA_INPUT, HDA_OUTPUT
103};
104
e3d280fc
TI		 105#define dev_to_hdac_dev(_dev) container_of(_dev, struct hdac_device, dev)
106
7639a06c
TI		 107int snd_hdac_device_init(struct hdac_device *dev, struct hdac_bus *bus,
108 const char *name, unsigned int addr);
109void snd_hdac_device_exit(struct hdac_device *dev);
3256be65
TI		 110int snd_hdac_device_register(struct hdac_device *codec);
111void snd_hdac_device_unregister(struct hdac_device *codec);
ded255be 112int snd_hdac_device_set_chip_name(struct hdac_device *codec, const char *name);
4f9e0c38 113int snd_hdac_codec_modalias(struct hdac_device *hdac, char *buf, size_t size);
7639a06c 114
9780ded3 115int snd_hdac_refresh_widgets(struct hdac_device *codec, bool sysfs);
7639a06c
TI		 116
117unsigned int snd_hdac_make_cmd(struct hdac_device *codec, hda_nid_t nid,
118 unsigned int verb, unsigned int parm);
05852448
TI		 119int snd_hdac_exec_verb(struct hdac_device *codec, unsigned int cmd,
120 unsigned int flags, unsigned int *res);
7639a06c
TI		 121int snd_hdac_read(struct hdac_device *codec, hda_nid_t nid,
122 unsigned int verb, unsigned int parm, unsigned int *res);
01ed3c06
TI		 123int _snd_hdac_read_parm(struct hdac_device *codec, hda_nid_t nid, int parm,
124 unsigned int *res);
9ba17b4d
TI		 125int snd_hdac_read_parm_uncached(struct hdac_device *codec, hda_nid_t nid,
126 int parm);
faa75f8a
TI		 127int snd_hdac_override_parm(struct hdac_device *codec, hda_nid_t nid,
128 unsigned int parm, unsigned int val);
7639a06c
TI		 129int snd_hdac_get_connections(struct hdac_device *codec, hda_nid_t nid,
130 hda_nid_t *conn_list, int max_conns);
131int snd_hdac_get_sub_nodes(struct hdac_device *codec, hda_nid_t nid,
132 hda_nid_t *start_id);
b7d023e1
TI		 133unsigned int snd_hdac_calc_stream_format(unsigned int rate,
134 unsigned int channels,
135 unsigned int format,
136 unsigned int maxbps,
137 unsigned short spdif_ctls);
138int snd_hdac_query_supported_pcm(struct hdac_device *codec, hda_nid_t nid,
139 u32 *ratesp, u64 *formatsp, unsigned int *bpsp);
140bool snd_hdac_is_supported_format(struct hdac_device *codec, hda_nid_t nid,
141 unsigned int format);
7639a06c 142
1b5e6167
SP		 143int snd_hdac_codec_read(struct hdac_device *hdac, hda_nid_t nid,
144 int flags, unsigned int verb, unsigned int parm);
145int snd_hdac_codec_write(struct hdac_device *hdac, hda_nid_t nid,
146 int flags, unsigned int verb, unsigned int parm);
147bool snd_hdac_check_power_state(struct hdac_device *hdac,
148 hda_nid_t nid, unsigned int target_state);
01ed3c06
TI		 149/**
150 * snd_hdac_read_parm - read a codec parameter
151 * @codec: the codec object
152 * @nid: NID to read a parameter
153 * @parm: parameter to read
154 *
155 * Returns -1 for error. If you need to distinguish the error more
156 * strictly, use _snd_hdac_read_parm() directly.
157 */
158static inline int snd_hdac_read_parm(struct hdac_device *codec, hda_nid_t nid,
159 int parm)
160{
161 unsigned int val;
162
163 return _snd_hdac_read_parm(codec, nid, parm, &val) < 0 ? -1 : val;
164}
165
7639a06c 166#ifdef CONFIG_PM
fbce23a0
TI		 167int snd_hdac_power_up(struct hdac_device *codec);
168int snd_hdac_power_down(struct hdac_device *codec);
169int snd_hdac_power_up_pm(struct hdac_device *codec);
170int snd_hdac_power_down_pm(struct hdac_device *codec);
fc4f000b 171int snd_hdac_keep_power_up(struct hdac_device *codec);
7639a06c 172#else
fbce23a0
TI		 173static inline int snd_hdac_power_up(struct hdac_device *codec) { return 0; }
174static inline int snd_hdac_power_down(struct hdac_device *codec) { return 0; }
175static inline int snd_hdac_power_up_pm(struct hdac_device *codec) { return 0; }
176static inline int snd_hdac_power_down_pm(struct hdac_device *codec) { return 0; }
fc4f000b 177static inline int snd_hdac_keep_power_up(struct hdac_device *codec) { return 0; }
7639a06c
TI		 178#endif
179
e3d280fc
TI		 180/*
181 * HD-audio codec base driver
182 */
183struct hdac_driver {
184 struct device_driver driver;
185 int type;
ec71efc9 186 const struct hda_device_id *id_table;
e3d280fc 187 int (*match)(struct hdac_device *dev, struct hdac_driver *drv);
d068ebc2 188 void (*unsol_event)(struct hdac_device *dev, unsigned int event);
e3d280fc
TI		 189};
190
191#define drv_to_hdac_driver(_drv) container_of(_drv, struct hdac_driver, driver)
192
ec71efc9
VK		 193const struct hda_device_id *
194hdac_get_device_id(struct hdac_device *hdev, struct hdac_driver *drv);
195
d068ebc2 196/*
14752412 197 * Bus verb operators
d068ebc2
TI		 198 */
199struct hdac_bus_ops {
200 /* send a single command */
201 int (*command)(struct hdac_bus *bus, unsigned int cmd);
202 /* get a response from the last command */
203 int (*get_response)(struct hdac_bus *bus, unsigned int addr,
204 unsigned int *res);
a5e7e07c
ML		 205 /* control the link power */
206 int (*link_power)(struct hdac_bus *bus, bool enable);
d068ebc2
TI		 207};
208
14752412
TI		 209/*
210 * Lowlevel I/O operators
211 */
212struct hdac_io_ops {
213 /* mapped register accesses */
214 void (*reg_writel)(u32 value, u32 __iomem *addr);
215 u32 (*reg_readl)(u32 __iomem *addr);
216 void (*reg_writew)(u16 value, u16 __iomem *addr);
217 u16 (*reg_readw)(u16 __iomem *addr);
218 void (*reg_writeb)(u8 value, u8 __iomem *addr);
219 u8 (*reg_readb)(u8 __iomem *addr);
8f3f600b
TI		 220 /* Allocation ops */
221 int (*dma_alloc_pages)(struct hdac_bus *bus, int type, size_t size,
222 struct snd_dma_buffer *buf);
223 void (*dma_free_pages)(struct hdac_bus *bus,
224 struct snd_dma_buffer *buf);
14752412
TI		 225};
226
d068ebc2 227#define HDA_UNSOL_QUEUE_SIZE 64
14752412
TI		 228#define HDA_MAX_CODECS 8 /* limit by controller side */
229
230/* HD Audio class code */
231#define PCI_CLASS_MULTIMEDIA_HD_AUDIO 0x0403
232
233/*
234 * CORB/RIRB
235 *
236 * Each CORB entry is 4byte, RIRB is 8byte
237 */
238struct hdac_rb {
239 __le32 *buf; /* virtual address of CORB/RIRB buffer */
240 dma_addr_t addr; /* physical address of CORB/RIRB buffer */
241 unsigned short rp, wp; /* RIRB read/write pointers */
242 int cmds[HDA_MAX_CODECS]; /* number of pending requests */
243 u32 res[HDA_MAX_CODECS]; /* last read value */
244};
d068ebc2 245
14752412
TI		 246/*
247 * HD-audio bus base driver
6720b384
VK		 248 *
249 * @ppcap: pp capabilities pointer
250 * @spbcap: SPIB capabilities pointer
251 * @mlcap: MultiLink capabilities pointer
252 * @gtscap: gts capabilities pointer
253 * @drsmcap: dma resume capabilities pointer
14752412 254 */
d068ebc2
TI		 255struct hdac_bus {
256 struct device *dev;
257 const struct hdac_bus_ops *ops;
14752412
TI		 258 const struct hdac_io_ops *io_ops;
259
260 /* h/w resources */
261 unsigned long addr;
262 void __iomem *remap_addr;
263 int irq;
d068ebc2 264
6720b384
VK		 265 void __iomem *ppcap;
266 void __iomem *spbcap;
267 void __iomem *mlcap;
268 void __iomem *gtscap;
269 void __iomem *drsmcap;
270
d068ebc2
TI		 271 /* codec linked list */
272 struct list_head codec_list;
273 unsigned int num_codecs;
274
275 /* link caddr -> codec */
276 struct hdac_device *caddr_tbl[HDA_MAX_CODEC_ADDRESS + 1];
277
278 /* unsolicited event queue */
279 u32 unsol_queue[HDA_UNSOL_QUEUE_SIZE * 2]; /* ring buffer */
280 unsigned int unsol_rp, unsol_wp;
281 struct work_struct unsol_work;
282
14752412
TI		 283 /* bit flags of detected codecs */
284 unsigned long codec_mask;
285
d068ebc2
TI		 286 /* bit flags of powered codecs */
287 unsigned long codec_powered;
288
14752412
TI		 289 /* CORB/RIRB */
290 struct hdac_rb corb;
291 struct hdac_rb rirb;
292 unsigned int last_cmd[HDA_MAX_CODECS]; /* last sent command */
293
294 /* CORB/RIRB and position buffers */
295 struct snd_dma_buffer rb;
296 struct snd_dma_buffer posbuf;
297
298 /* hdac_stream linked list */
299 struct list_head stream_list;
300
301 /* operation state */
302 bool chip_init:1; /* h/w initialized */
303
304 /* behavior flags */
d068ebc2 305 bool sync_write:1; /* sync after verb write */
14752412
TI		 306 bool use_posbuf:1; /* use position buffer */
307 bool snoop:1; /* enable snooping */
308 bool align_bdle_4k:1; /* BDLE align 4K boundary */
309 bool reverse_assign:1; /* assign devices in reverse order */
310 bool corbrp_self_clear:1; /* CORBRP clears itself after reset */
311
312 int bdl_pos_adj; /* BDL position adjustment */
d068ebc2
TI		 313
314 /* locks */
14752412 315 spinlock_t reg_lock;
d068ebc2 316 struct mutex cmd_mutex;
98d8fc6c
ML		 317
318 /* i915 component interface */
319 struct i915_audio_component *audio_component;
320 int i915_power_refcount;
d068ebc2
TI		 321};
322
323int snd_hdac_bus_init(struct hdac_bus *bus, struct device *dev,
14752412
TI		 324 const struct hdac_bus_ops *ops,
325 const struct hdac_io_ops *io_ops);
d068ebc2
TI		 326void snd_hdac_bus_exit(struct hdac_bus *bus);
327int snd_hdac_bus_exec_verb(struct hdac_bus *bus, unsigned int addr,
328 unsigned int cmd, unsigned int *res);
329int snd_hdac_bus_exec_verb_unlocked(struct hdac_bus *bus, unsigned int addr,
330 unsigned int cmd, unsigned int *res);
331void snd_hdac_bus_queue_event(struct hdac_bus *bus, u32 res, u32 res_ex);
332
333int snd_hdac_bus_add_device(struct hdac_bus *bus, struct hdac_device *codec);
334void snd_hdac_bus_remove_device(struct hdac_bus *bus,
335 struct hdac_device *codec);
336
7639a06c
TI		 337static inline void snd_hdac_codec_link_up(struct hdac_device *codec)
338{
339 set_bit(codec->addr, &codec->bus->codec_powered);
340}
341
342static inline void snd_hdac_codec_link_down(struct hdac_device *codec)
343{
344 clear_bit(codec->addr, &codec->bus->codec_powered);
345}
346
14752412
TI		 347int snd_hdac_bus_send_cmd(struct hdac_bus *bus, unsigned int val);
348int snd_hdac_bus_get_response(struct hdac_bus *bus, unsigned int addr,
349 unsigned int *res);
6720b384 350int snd_hdac_bus_parse_capabilities(struct hdac_bus *bus);
a5e7e07c 351int snd_hdac_link_power(struct hdac_device *codec, bool enable);
14752412
TI		 352
353bool snd_hdac_bus_init_chip(struct hdac_bus *bus, bool full_reset);
354void snd_hdac_bus_stop_chip(struct hdac_bus *bus);
355void snd_hdac_bus_init_cmd_io(struct hdac_bus *bus);
356void snd_hdac_bus_stop_cmd_io(struct hdac_bus *bus);
357void snd_hdac_bus_enter_link_reset(struct hdac_bus *bus);
358void snd_hdac_bus_exit_link_reset(struct hdac_bus *bus);
cd38f4f2 359int snd_hdac_bus_reset_link(struct hdac_bus *bus, bool full_reset);
14752412
TI		 360
361void snd_hdac_bus_update_rirb(struct hdac_bus *bus);
473f4145 362int snd_hdac_bus_handle_stream_irq(struct hdac_bus *bus, unsigned int status,
14752412
TI		 363 void (*ack)(struct hdac_bus *,
364 struct hdac_stream *));
365
304dad30
JK		 366int snd_hdac_bus_alloc_stream_pages(struct hdac_bus *bus);
367void snd_hdac_bus_free_stream_pages(struct hdac_bus *bus);
368
14752412
TI		 369/*
370 * macros for easy use
371 */
2c1f8138
TI		 372#define _snd_hdac_chip_writeb(chip, reg, value) \
373 ((chip)->io_ops->reg_writeb(value, (chip)->remap_addr + (reg)))
374#define _snd_hdac_chip_readb(chip, reg) \
375 ((chip)->io_ops->reg_readb((chip)->remap_addr + (reg)))
376#define _snd_hdac_chip_writew(chip, reg, value) \
377 ((chip)->io_ops->reg_writew(value, (chip)->remap_addr + (reg)))
378#define _snd_hdac_chip_readw(chip, reg) \
379 ((chip)->io_ops->reg_readw((chip)->remap_addr + (reg)))
380#define _snd_hdac_chip_writel(chip, reg, value) \
381 ((chip)->io_ops->reg_writel(value, (chip)->remap_addr + (reg)))
382#define _snd_hdac_chip_readl(chip, reg) \
383 ((chip)->io_ops->reg_readl((chip)->remap_addr + (reg)))
14752412
TI		 384
385/* read/write a register, pass without AZX_REG_ prefix */
386#define snd_hdac_chip_writel(chip, reg, value) \
2c1f8138 387 _snd_hdac_chip_writel(chip, AZX_REG_ ## reg, value)
14752412 388#define snd_hdac_chip_writew(chip, reg, value) \
2c1f8138 389 _snd_hdac_chip_writew(chip, AZX_REG_ ## reg, value)
14752412 390#define snd_hdac_chip_writeb(chip, reg, value) \
2c1f8138 391 _snd_hdac_chip_writeb(chip, AZX_REG_ ## reg, value)
14752412 392#define snd_hdac_chip_readl(chip, reg) \
2c1f8138 393 _snd_hdac_chip_readl(chip, AZX_REG_ ## reg)
14752412 394#define snd_hdac_chip_readw(chip, reg) \
2c1f8138 395 _snd_hdac_chip_readw(chip, AZX_REG_ ## reg)
14752412 396#define snd_hdac_chip_readb(chip, reg) \
2c1f8138 397 _snd_hdac_chip_readb(chip, AZX_REG_ ## reg)
14752412
TI		 398
399/* update a register, pass without AZX_REG_ prefix */
400#define snd_hdac_chip_updatel(chip, reg, mask, val) \
401 snd_hdac_chip_writel(chip, reg, \
402 (snd_hdac_chip_readl(chip, reg) & ~(mask)) | (val))
403#define snd_hdac_chip_updatew(chip, reg, mask, val) \
404 snd_hdac_chip_writew(chip, reg, \
405 (snd_hdac_chip_readw(chip, reg) & ~(mask)) | (val))
406#define snd_hdac_chip_updateb(chip, reg, mask, val) \
407 snd_hdac_chip_writeb(chip, reg, \
408 (snd_hdac_chip_readb(chip, reg) & ~(mask)) | (val))
409
410/*
411 * HD-audio stream
412 */
413struct hdac_stream {
414 struct hdac_bus *bus;
415 struct snd_dma_buffer bdl; /* BDL buffer */
416 __le32 *posbuf; /* position buffer pointer */
417 int direction; /* playback / capture (SNDRV_PCM_STREAM_*) */
418
419 unsigned int bufsize; /* size of the play buffer in bytes */
420 unsigned int period_bytes; /* size of the period in bytes */
421 unsigned int frags; /* number for period in the play buffer */
422 unsigned int fifo_size; /* FIFO size */
423
424 void __iomem *sd_addr; /* stream descriptor pointer */
425
426 u32 sd_int_sta_mask; /* stream int status mask */
427
428 /* pcm support */
429 struct snd_pcm_substream *substream; /* assigned substream,
430 * set in PCM open
431 */
432 unsigned int format_val; /* format value to be set in the
433 * controller and the codec
434 */
435 unsigned char stream_tag; /* assigned stream */
436 unsigned char index; /* stream index */
437 int assigned_key; /* last device# key assigned to */
438
439 bool opened:1;
440 bool running:1;
6d23c8f5 441 bool prepared:1;
14752412 442 bool no_period_wakeup:1;
8f3f600b 443 bool locked:1;
14752412
TI		 444
445 /* timestamp */
446 unsigned long start_wallclk; /* start + minimum wallclk */
447 unsigned long period_wallclk; /* wallclk for period */
448 struct timecounter tc;
449 struct cyclecounter cc;
450 int delay_negative_threshold;
451
452 struct list_head list;
8f3f600b
TI		 453#ifdef CONFIG_SND_HDA_DSP_LOADER
454 /* DSP access mutex */
455 struct mutex dsp_mutex;
456#endif
14752412
TI		 457};
458
459void snd_hdac_stream_init(struct hdac_bus *bus, struct hdac_stream *azx_dev,
460 int idx, int direction, int tag);
461struct hdac_stream *snd_hdac_stream_assign(struct hdac_bus *bus,
462 struct snd_pcm_substream *substream);
463void snd_hdac_stream_release(struct hdac_stream *azx_dev);
4308c9b0
JK		 464struct hdac_stream *snd_hdac_get_stream(struct hdac_bus *bus,
465 int dir, int stream_tag);
14752412
TI		 466
467int snd_hdac_stream_setup(struct hdac_stream *azx_dev);
468void snd_hdac_stream_cleanup(struct hdac_stream *azx_dev);
469int snd_hdac_stream_setup_periods(struct hdac_stream *azx_dev);
86f6501b
JK		 470int snd_hdac_stream_set_params(struct hdac_stream *azx_dev,
471 unsigned int format_val);
14752412
TI		 472void snd_hdac_stream_start(struct hdac_stream *azx_dev, bool fresh_start);
473void snd_hdac_stream_clear(struct hdac_stream *azx_dev);
474void snd_hdac_stream_stop(struct hdac_stream *azx_dev);
475void snd_hdac_stream_reset(struct hdac_stream *azx_dev);
476void snd_hdac_stream_sync_trigger(struct hdac_stream *azx_dev, bool set,
477 unsigned int streams, unsigned int reg);
478void snd_hdac_stream_sync(struct hdac_stream *azx_dev, bool start,
479 unsigned int streams);
480void snd_hdac_stream_timecounter_init(struct hdac_stream *azx_dev,
481 unsigned int streams);
482/*
483 * macros for easy use
484 */
485#define _snd_hdac_stream_write(type, dev, reg, value) \
486 ((dev)->bus->io_ops->reg_write ## type(value, (dev)->sd_addr + (reg)))
487#define _snd_hdac_stream_read(type, dev, reg) \
488 ((dev)->bus->io_ops->reg_read ## type((dev)->sd_addr + (reg)))
489
490/* read/write a register, pass without AZX_REG_ prefix */
491#define snd_hdac_stream_writel(dev, reg, value) \
492 _snd_hdac_stream_write(l, dev, AZX_REG_ ## reg, value)
493#define snd_hdac_stream_writew(dev, reg, value) \
494 _snd_hdac_stream_write(w, dev, AZX_REG_ ## reg, value)
495#define snd_hdac_stream_writeb(dev, reg, value) \
496 _snd_hdac_stream_write(b, dev, AZX_REG_ ## reg, value)
497#define snd_hdac_stream_readl(dev, reg) \
498 _snd_hdac_stream_read(l, dev, AZX_REG_ ## reg)
499#define snd_hdac_stream_readw(dev, reg) \
500 _snd_hdac_stream_read(w, dev, AZX_REG_ ## reg)
501#define snd_hdac_stream_readb(dev, reg) \
502 _snd_hdac_stream_read(b, dev, AZX_REG_ ## reg)
503
504/* update a register, pass without AZX_REG_ prefix */
505#define snd_hdac_stream_updatel(dev, reg, mask, val) \
506 snd_hdac_stream_writel(dev, reg, \
507 (snd_hdac_stream_readl(dev, reg) & \
508 ~(mask)) | (val))
509#define snd_hdac_stream_updatew(dev, reg, mask, val) \
510 snd_hdac_stream_writew(dev, reg, \
511 (snd_hdac_stream_readw(dev, reg) & \
512 ~(mask)) | (val))
513#define snd_hdac_stream_updateb(dev, reg, mask, val) \
514 snd_hdac_stream_writeb(dev, reg, \
515 (snd_hdac_stream_readb(dev, reg) & \
516 ~(mask)) | (val))
517
8f3f600b
TI		 518#ifdef CONFIG_SND_HDA_DSP_LOADER
519/* DSP lock helpers */
520#define snd_hdac_dsp_lock_init(dev) mutex_init(&(dev)->dsp_mutex)
521#define snd_hdac_dsp_lock(dev) mutex_lock(&(dev)->dsp_mutex)
522#define snd_hdac_dsp_unlock(dev) mutex_unlock(&(dev)->dsp_mutex)
523#define snd_hdac_stream_is_locked(dev) ((dev)->locked)
524/* DSP loader helpers */
525int snd_hdac_dsp_prepare(struct hdac_stream *azx_dev, unsigned int format,
526 unsigned int byte_size, struct snd_dma_buffer *bufp);
527void snd_hdac_dsp_trigger(struct hdac_stream *azx_dev, bool start);
528void snd_hdac_dsp_cleanup(struct hdac_stream *azx_dev,
529 struct snd_dma_buffer *dmab);
530#else /* CONFIG_SND_HDA_DSP_LOADER */
531#define snd_hdac_dsp_lock_init(dev) do {} while (0)
532#define snd_hdac_dsp_lock(dev) do {} while (0)
533#define snd_hdac_dsp_unlock(dev) do {} while (0)
534#define snd_hdac_stream_is_locked(dev) 0
535
536static inline int
537snd_hdac_dsp_prepare(struct hdac_stream *azx_dev, unsigned int format,
538 unsigned int byte_size, struct snd_dma_buffer *bufp)
539{
540 return 0;
541}
542
543static inline void snd_hdac_dsp_trigger(struct hdac_stream *azx_dev, bool start)
544{
545}
546
547static inline void snd_hdac_dsp_cleanup(struct hdac_stream *azx_dev,
548 struct snd_dma_buffer *dmab)
549{
550}
551#endif /* CONFIG_SND_HDA_DSP_LOADER */
552
553
71fc4c7e
TI		 554/*
555 * generic array helpers
556 */
557void *snd_array_new(struct snd_array *array);
558void snd_array_free(struct snd_array *array);
559static inline void snd_array_init(struct snd_array *array, unsigned int size,
560 unsigned int align)
561{
562 array->elem_size = size;
563 array->alloc_align = align;
564}
565
566static inline void *snd_array_elem(struct snd_array *array, unsigned int idx)
567{
568 return array->list + idx * array->elem_size;
569}
570
571static inline unsigned int snd_array_index(struct snd_array *array, void *ptr)
572{
573 return (unsigned long)(ptr - array->list) / array->elem_size;
574}
575
e3d280fc 576#endif /* __SOUND_HDAUDIO_H */
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