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Commit | Line | Data |
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e3d280fc TI |
1 | /* |
2 | * HD-audio core stuff | |
3 | */ | |
4 | ||
5 | #ifndef __SOUND_HDAUDIO_H | |
6 | #define __SOUND_HDAUDIO_H | |
7 | ||
8 | #include <linux/device.h> | |
14752412 TI |
9 | #include <linux/interrupt.h> |
10 | #include <linux/timecounter.h> | |
11 | #include <sound/core.h> | |
12 | #include <sound/memalloc.h> | |
d068ebc2 | 13 | #include <sound/hda_verbs.h> |
98d8fc6c | 14 | #include <drm/i915_component.h> |
d068ebc2 | 15 | |
7639a06c TI |
16 | /* codec node id */ |
17 | typedef u16 hda_nid_t; | |
18 | ||
d068ebc2 | 19 | struct hdac_bus; |
14752412 | 20 | struct hdac_stream; |
d068ebc2 TI |
21 | struct hdac_device; |
22 | struct hdac_driver; | |
3256be65 | 23 | struct hdac_widget_tree; |
e3d280fc TI |
24 | |
25 | /* | |
26 | * exported bus type | |
27 | */ | |
28 | extern struct bus_type snd_hda_bus_type; | |
29 | ||
ec71efc9 VK |
30 | /* |
31 | * HDA device table | |
32 | */ | |
33 | struct hda_device_id { | |
34 | __u32 vendor_id; | |
35 | __u32 rev_id; | |
36 | const char *name; | |
37 | unsigned long driver_data; | |
38 | }; | |
39 | ||
71fc4c7e TI |
40 | /* |
41 | * generic arrays | |
42 | */ | |
43 | struct snd_array { | |
44 | unsigned int used; | |
45 | unsigned int alloced; | |
46 | unsigned int elem_size; | |
47 | unsigned int alloc_align; | |
48 | void *list; | |
49 | }; | |
50 | ||
e3d280fc TI |
51 | /* |
52 | * HD-audio codec base device | |
53 | */ | |
54 | struct hdac_device { | |
55 | struct device dev; | |
56 | int type; | |
d068ebc2 TI |
57 | struct hdac_bus *bus; |
58 | unsigned int addr; /* codec address */ | |
59 | struct list_head list; /* list point for bus codec_list */ | |
7639a06c TI |
60 | |
61 | hda_nid_t afg; /* AFG node id */ | |
62 | hda_nid_t mfg; /* MFG node id */ | |
63 | ||
64 | /* ids */ | |
65 | unsigned int vendor_id; | |
66 | unsigned int subsystem_id; | |
67 | unsigned int revision_id; | |
68 | unsigned int afg_function_id; | |
69 | unsigned int mfg_function_id; | |
70 | unsigned int afg_unsol:1; | |
71 | unsigned int mfg_unsol:1; | |
72 | ||
73 | unsigned int power_caps; /* FG power caps */ | |
74 | ||
75 | const char *vendor_name; /* codec vendor name */ | |
76 | const char *chip_name; /* codec chip name */ | |
77 | ||
05852448 TI |
78 | /* verb exec op override */ |
79 | int (*exec_verb)(struct hdac_device *dev, unsigned int cmd, | |
80 | unsigned int flags, unsigned int *res); | |
81 | ||
7639a06c TI |
82 | /* widgets */ |
83 | unsigned int num_nodes; | |
84 | hda_nid_t start_nid, end_nid; | |
85 | ||
86 | /* misc flags */ | |
87 | atomic_t in_pm; /* suspend/resume being performed */ | |
a5e7e07c | 88 | bool link_power_control:1; |
3256be65 TI |
89 | |
90 | /* sysfs */ | |
91 | struct hdac_widget_tree *widgets; | |
4d75faa0 TI |
92 | |
93 | /* regmap */ | |
94 | struct regmap *regmap; | |
5e56bcea | 95 | struct snd_array vendor_verbs; |
4d75faa0 | 96 | bool lazy_cache:1; /* don't wake up for writes */ |
faa75f8a | 97 | bool caps_overwriting:1; /* caps overwrite being in process */ |
40ba66a7 | 98 | bool cache_coef:1; /* cache COEF read/write too */ |
e3d280fc TI |
99 | }; |
100 | ||
101 | /* device/driver type used for matching */ | |
102 | enum { | |
103 | HDA_DEV_CORE, | |
104 | HDA_DEV_LEGACY, | |
c1cc18b1 | 105 | HDA_DEV_ASOC, |
e3d280fc TI |
106 | }; |
107 | ||
7639a06c TI |
108 | /* direction */ |
109 | enum { | |
110 | HDA_INPUT, HDA_OUTPUT | |
111 | }; | |
112 | ||
e3d280fc TI |
113 | #define dev_to_hdac_dev(_dev) container_of(_dev, struct hdac_device, dev) |
114 | ||
7639a06c TI |
115 | int snd_hdac_device_init(struct hdac_device *dev, struct hdac_bus *bus, |
116 | const char *name, unsigned int addr); | |
117 | void snd_hdac_device_exit(struct hdac_device *dev); | |
3256be65 TI |
118 | int snd_hdac_device_register(struct hdac_device *codec); |
119 | void snd_hdac_device_unregister(struct hdac_device *codec); | |
7639a06c TI |
120 | |
121 | int snd_hdac_refresh_widgets(struct hdac_device *codec); | |
18dfd79d | 122 | int snd_hdac_refresh_widget_sysfs(struct hdac_device *codec); |
7639a06c TI |
123 | |
124 | unsigned int snd_hdac_make_cmd(struct hdac_device *codec, hda_nid_t nid, | |
125 | unsigned int verb, unsigned int parm); | |
05852448 TI |
126 | int snd_hdac_exec_verb(struct hdac_device *codec, unsigned int cmd, |
127 | unsigned int flags, unsigned int *res); | |
7639a06c TI |
128 | int snd_hdac_read(struct hdac_device *codec, hda_nid_t nid, |
129 | unsigned int verb, unsigned int parm, unsigned int *res); | |
01ed3c06 TI |
130 | int _snd_hdac_read_parm(struct hdac_device *codec, hda_nid_t nid, int parm, |
131 | unsigned int *res); | |
9ba17b4d TI |
132 | int snd_hdac_read_parm_uncached(struct hdac_device *codec, hda_nid_t nid, |
133 | int parm); | |
faa75f8a TI |
134 | int snd_hdac_override_parm(struct hdac_device *codec, hda_nid_t nid, |
135 | unsigned int parm, unsigned int val); | |
7639a06c TI |
136 | int snd_hdac_get_connections(struct hdac_device *codec, hda_nid_t nid, |
137 | hda_nid_t *conn_list, int max_conns); | |
138 | int snd_hdac_get_sub_nodes(struct hdac_device *codec, hda_nid_t nid, | |
139 | hda_nid_t *start_id); | |
b7d023e1 TI |
140 | unsigned int snd_hdac_calc_stream_format(unsigned int rate, |
141 | unsigned int channels, | |
142 | unsigned int format, | |
143 | unsigned int maxbps, | |
144 | unsigned short spdif_ctls); | |
145 | int snd_hdac_query_supported_pcm(struct hdac_device *codec, hda_nid_t nid, | |
146 | u32 *ratesp, u64 *formatsp, unsigned int *bpsp); | |
147 | bool snd_hdac_is_supported_format(struct hdac_device *codec, hda_nid_t nid, | |
148 | unsigned int format); | |
7639a06c | 149 | |
01ed3c06 TI |
150 | /** |
151 | * snd_hdac_read_parm - read a codec parameter | |
152 | * @codec: the codec object | |
153 | * @nid: NID to read a parameter | |
154 | * @parm: parameter to read | |
155 | * | |
156 | * Returns -1 for error. If you need to distinguish the error more | |
157 | * strictly, use _snd_hdac_read_parm() directly. | |
158 | */ | |
159 | static inline int snd_hdac_read_parm(struct hdac_device *codec, hda_nid_t nid, | |
160 | int parm) | |
161 | { | |
162 | unsigned int val; | |
163 | ||
164 | return _snd_hdac_read_parm(codec, nid, parm, &val) < 0 ? -1 : val; | |
165 | } | |
166 | ||
7639a06c | 167 | #ifdef CONFIG_PM |
fbce23a0 TI |
168 | int snd_hdac_power_up(struct hdac_device *codec); |
169 | int snd_hdac_power_down(struct hdac_device *codec); | |
170 | int snd_hdac_power_up_pm(struct hdac_device *codec); | |
171 | int snd_hdac_power_down_pm(struct hdac_device *codec); | |
7639a06c | 172 | #else |
fbce23a0 TI |
173 | static inline int snd_hdac_power_up(struct hdac_device *codec) { return 0; } |
174 | static inline int snd_hdac_power_down(struct hdac_device *codec) { return 0; } | |
175 | static inline int snd_hdac_power_up_pm(struct hdac_device *codec) { return 0; } | |
176 | static inline int snd_hdac_power_down_pm(struct hdac_device *codec) { return 0; } | |
7639a06c TI |
177 | #endif |
178 | ||
e3d280fc TI |
179 | /* |
180 | * HD-audio codec base driver | |
181 | */ | |
182 | struct hdac_driver { | |
183 | struct device_driver driver; | |
184 | int type; | |
ec71efc9 | 185 | const struct hda_device_id *id_table; |
e3d280fc | 186 | int (*match)(struct hdac_device *dev, struct hdac_driver *drv); |
d068ebc2 | 187 | void (*unsol_event)(struct hdac_device *dev, unsigned int event); |
e3d280fc TI |
188 | }; |
189 | ||
190 | #define drv_to_hdac_driver(_drv) container_of(_drv, struct hdac_driver, driver) | |
191 | ||
ec71efc9 VK |
192 | const struct hda_device_id * |
193 | hdac_get_device_id(struct hdac_device *hdev, struct hdac_driver *drv); | |
194 | ||
d068ebc2 | 195 | /* |
14752412 | 196 | * Bus verb operators |
d068ebc2 TI |
197 | */ |
198 | struct hdac_bus_ops { | |
199 | /* send a single command */ | |
200 | int (*command)(struct hdac_bus *bus, unsigned int cmd); | |
201 | /* get a response from the last command */ | |
202 | int (*get_response)(struct hdac_bus *bus, unsigned int addr, | |
203 | unsigned int *res); | |
a5e7e07c ML |
204 | /* control the link power */ |
205 | int (*link_power)(struct hdac_bus *bus, bool enable); | |
d068ebc2 TI |
206 | }; |
207 | ||
14752412 TI |
208 | /* |
209 | * Lowlevel I/O operators | |
210 | */ | |
211 | struct hdac_io_ops { | |
212 | /* mapped register accesses */ | |
213 | void (*reg_writel)(u32 value, u32 __iomem *addr); | |
214 | u32 (*reg_readl)(u32 __iomem *addr); | |
215 | void (*reg_writew)(u16 value, u16 __iomem *addr); | |
216 | u16 (*reg_readw)(u16 __iomem *addr); | |
217 | void (*reg_writeb)(u8 value, u8 __iomem *addr); | |
218 | u8 (*reg_readb)(u8 __iomem *addr); | |
8f3f600b TI |
219 | /* Allocation ops */ |
220 | int (*dma_alloc_pages)(struct hdac_bus *bus, int type, size_t size, | |
221 | struct snd_dma_buffer *buf); | |
222 | void (*dma_free_pages)(struct hdac_bus *bus, | |
223 | struct snd_dma_buffer *buf); | |
14752412 TI |
224 | }; |
225 | ||
d068ebc2 | 226 | #define HDA_UNSOL_QUEUE_SIZE 64 |
14752412 TI |
227 | #define HDA_MAX_CODECS 8 /* limit by controller side */ |
228 | ||
229 | /* HD Audio class code */ | |
230 | #define PCI_CLASS_MULTIMEDIA_HD_AUDIO 0x0403 | |
231 | ||
232 | /* | |
233 | * CORB/RIRB | |
234 | * | |
235 | * Each CORB entry is 4byte, RIRB is 8byte | |
236 | */ | |
237 | struct hdac_rb { | |
238 | __le32 *buf; /* virtual address of CORB/RIRB buffer */ | |
239 | dma_addr_t addr; /* physical address of CORB/RIRB buffer */ | |
240 | unsigned short rp, wp; /* RIRB read/write pointers */ | |
241 | int cmds[HDA_MAX_CODECS]; /* number of pending requests */ | |
242 | u32 res[HDA_MAX_CODECS]; /* last read value */ | |
243 | }; | |
d068ebc2 | 244 | |
14752412 TI |
245 | /* |
246 | * HD-audio bus base driver | |
247 | */ | |
d068ebc2 TI |
248 | struct hdac_bus { |
249 | struct device *dev; | |
250 | const struct hdac_bus_ops *ops; | |
14752412 TI |
251 | const struct hdac_io_ops *io_ops; |
252 | ||
253 | /* h/w resources */ | |
254 | unsigned long addr; | |
255 | void __iomem *remap_addr; | |
256 | int irq; | |
d068ebc2 TI |
257 | |
258 | /* codec linked list */ | |
259 | struct list_head codec_list; | |
260 | unsigned int num_codecs; | |
261 | ||
262 | /* link caddr -> codec */ | |
263 | struct hdac_device *caddr_tbl[HDA_MAX_CODEC_ADDRESS + 1]; | |
264 | ||
265 | /* unsolicited event queue */ | |
266 | u32 unsol_queue[HDA_UNSOL_QUEUE_SIZE * 2]; /* ring buffer */ | |
267 | unsigned int unsol_rp, unsol_wp; | |
268 | struct work_struct unsol_work; | |
269 | ||
14752412 TI |
270 | /* bit flags of detected codecs */ |
271 | unsigned long codec_mask; | |
272 | ||
d068ebc2 TI |
273 | /* bit flags of powered codecs */ |
274 | unsigned long codec_powered; | |
275 | ||
14752412 TI |
276 | /* CORB/RIRB */ |
277 | struct hdac_rb corb; | |
278 | struct hdac_rb rirb; | |
279 | unsigned int last_cmd[HDA_MAX_CODECS]; /* last sent command */ | |
280 | ||
281 | /* CORB/RIRB and position buffers */ | |
282 | struct snd_dma_buffer rb; | |
283 | struct snd_dma_buffer posbuf; | |
284 | ||
285 | /* hdac_stream linked list */ | |
286 | struct list_head stream_list; | |
287 | ||
288 | /* operation state */ | |
289 | bool chip_init:1; /* h/w initialized */ | |
290 | ||
291 | /* behavior flags */ | |
d068ebc2 | 292 | bool sync_write:1; /* sync after verb write */ |
14752412 TI |
293 | bool use_posbuf:1; /* use position buffer */ |
294 | bool snoop:1; /* enable snooping */ | |
295 | bool align_bdle_4k:1; /* BDLE align 4K boundary */ | |
296 | bool reverse_assign:1; /* assign devices in reverse order */ | |
297 | bool corbrp_self_clear:1; /* CORBRP clears itself after reset */ | |
298 | ||
299 | int bdl_pos_adj; /* BDL position adjustment */ | |
d068ebc2 TI |
300 | |
301 | /* locks */ | |
14752412 | 302 | spinlock_t reg_lock; |
d068ebc2 | 303 | struct mutex cmd_mutex; |
98d8fc6c ML |
304 | |
305 | /* i915 component interface */ | |
306 | struct i915_audio_component *audio_component; | |
307 | int i915_power_refcount; | |
d068ebc2 TI |
308 | }; |
309 | ||
310 | int snd_hdac_bus_init(struct hdac_bus *bus, struct device *dev, | |
14752412 TI |
311 | const struct hdac_bus_ops *ops, |
312 | const struct hdac_io_ops *io_ops); | |
d068ebc2 TI |
313 | void snd_hdac_bus_exit(struct hdac_bus *bus); |
314 | int snd_hdac_bus_exec_verb(struct hdac_bus *bus, unsigned int addr, | |
315 | unsigned int cmd, unsigned int *res); | |
316 | int snd_hdac_bus_exec_verb_unlocked(struct hdac_bus *bus, unsigned int addr, | |
317 | unsigned int cmd, unsigned int *res); | |
318 | void snd_hdac_bus_queue_event(struct hdac_bus *bus, u32 res, u32 res_ex); | |
319 | ||
320 | int snd_hdac_bus_add_device(struct hdac_bus *bus, struct hdac_device *codec); | |
321 | void snd_hdac_bus_remove_device(struct hdac_bus *bus, | |
322 | struct hdac_device *codec); | |
323 | ||
7639a06c TI |
324 | static inline void snd_hdac_codec_link_up(struct hdac_device *codec) |
325 | { | |
326 | set_bit(codec->addr, &codec->bus->codec_powered); | |
327 | } | |
328 | ||
329 | static inline void snd_hdac_codec_link_down(struct hdac_device *codec) | |
330 | { | |
331 | clear_bit(codec->addr, &codec->bus->codec_powered); | |
332 | } | |
333 | ||
14752412 TI |
334 | int snd_hdac_bus_send_cmd(struct hdac_bus *bus, unsigned int val); |
335 | int snd_hdac_bus_get_response(struct hdac_bus *bus, unsigned int addr, | |
336 | unsigned int *res); | |
a5e7e07c | 337 | int snd_hdac_link_power(struct hdac_device *codec, bool enable); |
14752412 TI |
338 | |
339 | bool snd_hdac_bus_init_chip(struct hdac_bus *bus, bool full_reset); | |
340 | void snd_hdac_bus_stop_chip(struct hdac_bus *bus); | |
341 | void snd_hdac_bus_init_cmd_io(struct hdac_bus *bus); | |
342 | void snd_hdac_bus_stop_cmd_io(struct hdac_bus *bus); | |
343 | void snd_hdac_bus_enter_link_reset(struct hdac_bus *bus); | |
344 | void snd_hdac_bus_exit_link_reset(struct hdac_bus *bus); | |
345 | ||
346 | void snd_hdac_bus_update_rirb(struct hdac_bus *bus); | |
347 | void snd_hdac_bus_handle_stream_irq(struct hdac_bus *bus, unsigned int status, | |
348 | void (*ack)(struct hdac_bus *, | |
349 | struct hdac_stream *)); | |
350 | ||
304dad30 JK |
351 | int snd_hdac_bus_alloc_stream_pages(struct hdac_bus *bus); |
352 | void snd_hdac_bus_free_stream_pages(struct hdac_bus *bus); | |
353 | ||
14752412 TI |
354 | /* |
355 | * macros for easy use | |
356 | */ | |
357 | #define _snd_hdac_chip_write(type, chip, reg, value) \ | |
358 | ((chip)->io_ops->reg_write ## type(value, (chip)->remap_addr + (reg))) | |
359 | #define _snd_hdac_chip_read(type, chip, reg) \ | |
360 | ((chip)->io_ops->reg_read ## type((chip)->remap_addr + (reg))) | |
361 | ||
362 | /* read/write a register, pass without AZX_REG_ prefix */ | |
363 | #define snd_hdac_chip_writel(chip, reg, value) \ | |
364 | _snd_hdac_chip_write(l, chip, AZX_REG_ ## reg, value) | |
365 | #define snd_hdac_chip_writew(chip, reg, value) \ | |
366 | _snd_hdac_chip_write(w, chip, AZX_REG_ ## reg, value) | |
367 | #define snd_hdac_chip_writeb(chip, reg, value) \ | |
368 | _snd_hdac_chip_write(b, chip, AZX_REG_ ## reg, value) | |
369 | #define snd_hdac_chip_readl(chip, reg) \ | |
370 | _snd_hdac_chip_read(l, chip, AZX_REG_ ## reg) | |
371 | #define snd_hdac_chip_readw(chip, reg) \ | |
372 | _snd_hdac_chip_read(w, chip, AZX_REG_ ## reg) | |
373 | #define snd_hdac_chip_readb(chip, reg) \ | |
374 | _snd_hdac_chip_read(b, chip, AZX_REG_ ## reg) | |
375 | ||
376 | /* update a register, pass without AZX_REG_ prefix */ | |
377 | #define snd_hdac_chip_updatel(chip, reg, mask, val) \ | |
378 | snd_hdac_chip_writel(chip, reg, \ | |
379 | (snd_hdac_chip_readl(chip, reg) & ~(mask)) | (val)) | |
380 | #define snd_hdac_chip_updatew(chip, reg, mask, val) \ | |
381 | snd_hdac_chip_writew(chip, reg, \ | |
382 | (snd_hdac_chip_readw(chip, reg) & ~(mask)) | (val)) | |
383 | #define snd_hdac_chip_updateb(chip, reg, mask, val) \ | |
384 | snd_hdac_chip_writeb(chip, reg, \ | |
385 | (snd_hdac_chip_readb(chip, reg) & ~(mask)) | (val)) | |
386 | ||
387 | /* | |
388 | * HD-audio stream | |
389 | */ | |
390 | struct hdac_stream { | |
391 | struct hdac_bus *bus; | |
392 | struct snd_dma_buffer bdl; /* BDL buffer */ | |
393 | __le32 *posbuf; /* position buffer pointer */ | |
394 | int direction; /* playback / capture (SNDRV_PCM_STREAM_*) */ | |
395 | ||
396 | unsigned int bufsize; /* size of the play buffer in bytes */ | |
397 | unsigned int period_bytes; /* size of the period in bytes */ | |
398 | unsigned int frags; /* number for period in the play buffer */ | |
399 | unsigned int fifo_size; /* FIFO size */ | |
400 | ||
401 | void __iomem *sd_addr; /* stream descriptor pointer */ | |
402 | ||
403 | u32 sd_int_sta_mask; /* stream int status mask */ | |
404 | ||
405 | /* pcm support */ | |
406 | struct snd_pcm_substream *substream; /* assigned substream, | |
407 | * set in PCM open | |
408 | */ | |
409 | unsigned int format_val; /* format value to be set in the | |
410 | * controller and the codec | |
411 | */ | |
412 | unsigned char stream_tag; /* assigned stream */ | |
413 | unsigned char index; /* stream index */ | |
414 | int assigned_key; /* last device# key assigned to */ | |
415 | ||
416 | bool opened:1; | |
417 | bool running:1; | |
6d23c8f5 | 418 | bool prepared:1; |
14752412 | 419 | bool no_period_wakeup:1; |
8f3f600b | 420 | bool locked:1; |
14752412 TI |
421 | |
422 | /* timestamp */ | |
423 | unsigned long start_wallclk; /* start + minimum wallclk */ | |
424 | unsigned long period_wallclk; /* wallclk for period */ | |
425 | struct timecounter tc; | |
426 | struct cyclecounter cc; | |
427 | int delay_negative_threshold; | |
428 | ||
429 | struct list_head list; | |
8f3f600b TI |
430 | #ifdef CONFIG_SND_HDA_DSP_LOADER |
431 | /* DSP access mutex */ | |
432 | struct mutex dsp_mutex; | |
433 | #endif | |
14752412 TI |
434 | }; |
435 | ||
436 | void snd_hdac_stream_init(struct hdac_bus *bus, struct hdac_stream *azx_dev, | |
437 | int idx, int direction, int tag); | |
438 | struct hdac_stream *snd_hdac_stream_assign(struct hdac_bus *bus, | |
439 | struct snd_pcm_substream *substream); | |
440 | void snd_hdac_stream_release(struct hdac_stream *azx_dev); | |
4308c9b0 JK |
441 | struct hdac_stream *snd_hdac_get_stream(struct hdac_bus *bus, |
442 | int dir, int stream_tag); | |
14752412 TI |
443 | |
444 | int snd_hdac_stream_setup(struct hdac_stream *azx_dev); | |
445 | void snd_hdac_stream_cleanup(struct hdac_stream *azx_dev); | |
446 | int snd_hdac_stream_setup_periods(struct hdac_stream *azx_dev); | |
86f6501b JK |
447 | int snd_hdac_stream_set_params(struct hdac_stream *azx_dev, |
448 | unsigned int format_val); | |
14752412 TI |
449 | void snd_hdac_stream_start(struct hdac_stream *azx_dev, bool fresh_start); |
450 | void snd_hdac_stream_clear(struct hdac_stream *azx_dev); | |
451 | void snd_hdac_stream_stop(struct hdac_stream *azx_dev); | |
452 | void snd_hdac_stream_reset(struct hdac_stream *azx_dev); | |
453 | void snd_hdac_stream_sync_trigger(struct hdac_stream *azx_dev, bool set, | |
454 | unsigned int streams, unsigned int reg); | |
455 | void snd_hdac_stream_sync(struct hdac_stream *azx_dev, bool start, | |
456 | unsigned int streams); | |
457 | void snd_hdac_stream_timecounter_init(struct hdac_stream *azx_dev, | |
458 | unsigned int streams); | |
459 | /* | |
460 | * macros for easy use | |
461 | */ | |
462 | #define _snd_hdac_stream_write(type, dev, reg, value) \ | |
463 | ((dev)->bus->io_ops->reg_write ## type(value, (dev)->sd_addr + (reg))) | |
464 | #define _snd_hdac_stream_read(type, dev, reg) \ | |
465 | ((dev)->bus->io_ops->reg_read ## type((dev)->sd_addr + (reg))) | |
466 | ||
467 | /* read/write a register, pass without AZX_REG_ prefix */ | |
468 | #define snd_hdac_stream_writel(dev, reg, value) \ | |
469 | _snd_hdac_stream_write(l, dev, AZX_REG_ ## reg, value) | |
470 | #define snd_hdac_stream_writew(dev, reg, value) \ | |
471 | _snd_hdac_stream_write(w, dev, AZX_REG_ ## reg, value) | |
472 | #define snd_hdac_stream_writeb(dev, reg, value) \ | |
473 | _snd_hdac_stream_write(b, dev, AZX_REG_ ## reg, value) | |
474 | #define snd_hdac_stream_readl(dev, reg) \ | |
475 | _snd_hdac_stream_read(l, dev, AZX_REG_ ## reg) | |
476 | #define snd_hdac_stream_readw(dev, reg) \ | |
477 | _snd_hdac_stream_read(w, dev, AZX_REG_ ## reg) | |
478 | #define snd_hdac_stream_readb(dev, reg) \ | |
479 | _snd_hdac_stream_read(b, dev, AZX_REG_ ## reg) | |
480 | ||
481 | /* update a register, pass without AZX_REG_ prefix */ | |
482 | #define snd_hdac_stream_updatel(dev, reg, mask, val) \ | |
483 | snd_hdac_stream_writel(dev, reg, \ | |
484 | (snd_hdac_stream_readl(dev, reg) & \ | |
485 | ~(mask)) | (val)) | |
486 | #define snd_hdac_stream_updatew(dev, reg, mask, val) \ | |
487 | snd_hdac_stream_writew(dev, reg, \ | |
488 | (snd_hdac_stream_readw(dev, reg) & \ | |
489 | ~(mask)) | (val)) | |
490 | #define snd_hdac_stream_updateb(dev, reg, mask, val) \ | |
491 | snd_hdac_stream_writeb(dev, reg, \ | |
492 | (snd_hdac_stream_readb(dev, reg) & \ | |
493 | ~(mask)) | (val)) | |
494 | ||
8f3f600b TI |
495 | #ifdef CONFIG_SND_HDA_DSP_LOADER |
496 | /* DSP lock helpers */ | |
497 | #define snd_hdac_dsp_lock_init(dev) mutex_init(&(dev)->dsp_mutex) | |
498 | #define snd_hdac_dsp_lock(dev) mutex_lock(&(dev)->dsp_mutex) | |
499 | #define snd_hdac_dsp_unlock(dev) mutex_unlock(&(dev)->dsp_mutex) | |
500 | #define snd_hdac_stream_is_locked(dev) ((dev)->locked) | |
501 | /* DSP loader helpers */ | |
502 | int snd_hdac_dsp_prepare(struct hdac_stream *azx_dev, unsigned int format, | |
503 | unsigned int byte_size, struct snd_dma_buffer *bufp); | |
504 | void snd_hdac_dsp_trigger(struct hdac_stream *azx_dev, bool start); | |
505 | void snd_hdac_dsp_cleanup(struct hdac_stream *azx_dev, | |
506 | struct snd_dma_buffer *dmab); | |
507 | #else /* CONFIG_SND_HDA_DSP_LOADER */ | |
508 | #define snd_hdac_dsp_lock_init(dev) do {} while (0) | |
509 | #define snd_hdac_dsp_lock(dev) do {} while (0) | |
510 | #define snd_hdac_dsp_unlock(dev) do {} while (0) | |
511 | #define snd_hdac_stream_is_locked(dev) 0 | |
512 | ||
513 | static inline int | |
514 | snd_hdac_dsp_prepare(struct hdac_stream *azx_dev, unsigned int format, | |
515 | unsigned int byte_size, struct snd_dma_buffer *bufp) | |
516 | { | |
517 | return 0; | |
518 | } | |
519 | ||
520 | static inline void snd_hdac_dsp_trigger(struct hdac_stream *azx_dev, bool start) | |
521 | { | |
522 | } | |
523 | ||
524 | static inline void snd_hdac_dsp_cleanup(struct hdac_stream *azx_dev, | |
525 | struct snd_dma_buffer *dmab) | |
526 | { | |
527 | } | |
528 | #endif /* CONFIG_SND_HDA_DSP_LOADER */ | |
529 | ||
530 | ||
71fc4c7e TI |
531 | /* |
532 | * generic array helpers | |
533 | */ | |
534 | void *snd_array_new(struct snd_array *array); | |
535 | void snd_array_free(struct snd_array *array); | |
536 | static inline void snd_array_init(struct snd_array *array, unsigned int size, | |
537 | unsigned int align) | |
538 | { | |
539 | array->elem_size = size; | |
540 | array->alloc_align = align; | |
541 | } | |
542 | ||
543 | static inline void *snd_array_elem(struct snd_array *array, unsigned int idx) | |
544 | { | |
545 | return array->list + idx * array->elem_size; | |
546 | } | |
547 | ||
548 | static inline unsigned int snd_array_index(struct snd_array *array, void *ptr) | |
549 | { | |
550 | return (unsigned long)(ptr - array->list) / array->elem_size; | |
551 | } | |
552 | ||
e3d280fc | 553 | #endif /* __SOUND_HDAUDIO_H */ |