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[mirror_ubuntu-bionic-kernel.git] / include / sound / hdaudio.h
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1/*
2 * HD-audio core stuff
3 */
4
5#ifndef __SOUND_HDAUDIO_H
6#define __SOUND_HDAUDIO_H
7
8#include <linux/device.h>
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9#include <linux/interrupt.h>
10#include <linux/timecounter.h>
11#include <sound/core.h>
12#include <sound/memalloc.h>
d068ebc2 13#include <sound/hda_verbs.h>
98d8fc6c 14#include <drm/i915_component.h>
d068ebc2 15
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16/* codec node id */
17typedef u16 hda_nid_t;
18
d068ebc2 19struct hdac_bus;
14752412 20struct hdac_stream;
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21struct hdac_device;
22struct hdac_driver;
3256be65 23struct hdac_widget_tree;
da23ac1e 24struct hda_device_id;
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25
26/*
27 * exported bus type
28 */
29extern struct bus_type snd_hda_bus_type;
30
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31/*
32 * generic arrays
33 */
34struct snd_array {
35 unsigned int used;
36 unsigned int alloced;
37 unsigned int elem_size;
38 unsigned int alloc_align;
39 void *list;
40};
41
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42/*
43 * HD-audio codec base device
44 */
45struct hdac_device {
46 struct device dev;
47 int type;
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48 struct hdac_bus *bus;
49 unsigned int addr; /* codec address */
50 struct list_head list; /* list point for bus codec_list */
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51
52 hda_nid_t afg; /* AFG node id */
53 hda_nid_t mfg; /* MFG node id */
54
55 /* ids */
56 unsigned int vendor_id;
57 unsigned int subsystem_id;
58 unsigned int revision_id;
59 unsigned int afg_function_id;
60 unsigned int mfg_function_id;
61 unsigned int afg_unsol:1;
62 unsigned int mfg_unsol:1;
63
64 unsigned int power_caps; /* FG power caps */
65
66 const char *vendor_name; /* codec vendor name */
67 const char *chip_name; /* codec chip name */
68
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69 /* verb exec op override */
70 int (*exec_verb)(struct hdac_device *dev, unsigned int cmd,
71 unsigned int flags, unsigned int *res);
72
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73 /* widgets */
74 unsigned int num_nodes;
75 hda_nid_t start_nid, end_nid;
76
77 /* misc flags */
78 atomic_t in_pm; /* suspend/resume being performed */
a5e7e07c 79 bool link_power_control:1;
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80
81 /* sysfs */
82 struct hdac_widget_tree *widgets;
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83
84 /* regmap */
85 struct regmap *regmap;
5e56bcea 86 struct snd_array vendor_verbs;
4d75faa0 87 bool lazy_cache:1; /* don't wake up for writes */
faa75f8a 88 bool caps_overwriting:1; /* caps overwrite being in process */
40ba66a7 89 bool cache_coef:1; /* cache COEF read/write too */
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90};
91
92/* device/driver type used for matching */
93enum {
94 HDA_DEV_CORE,
95 HDA_DEV_LEGACY,
c1cc18b1 96 HDA_DEV_ASOC,
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97};
98
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99/* direction */
100enum {
101 HDA_INPUT, HDA_OUTPUT
102};
103
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104#define dev_to_hdac_dev(_dev) container_of(_dev, struct hdac_device, dev)
105
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106int snd_hdac_device_init(struct hdac_device *dev, struct hdac_bus *bus,
107 const char *name, unsigned int addr);
108void snd_hdac_device_exit(struct hdac_device *dev);
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109int snd_hdac_device_register(struct hdac_device *codec);
110void snd_hdac_device_unregister(struct hdac_device *codec);
ded255be 111int snd_hdac_device_set_chip_name(struct hdac_device *codec, const char *name);
4f9e0c38 112int snd_hdac_codec_modalias(struct hdac_device *hdac, char *buf, size_t size);
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113
114int snd_hdac_refresh_widgets(struct hdac_device *codec);
18dfd79d 115int snd_hdac_refresh_widget_sysfs(struct hdac_device *codec);
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116
117unsigned int snd_hdac_make_cmd(struct hdac_device *codec, hda_nid_t nid,
118 unsigned int verb, unsigned int parm);
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119int snd_hdac_exec_verb(struct hdac_device *codec, unsigned int cmd,
120 unsigned int flags, unsigned int *res);
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121int snd_hdac_read(struct hdac_device *codec, hda_nid_t nid,
122 unsigned int verb, unsigned int parm, unsigned int *res);
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123int _snd_hdac_read_parm(struct hdac_device *codec, hda_nid_t nid, int parm,
124 unsigned int *res);
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125int snd_hdac_read_parm_uncached(struct hdac_device *codec, hda_nid_t nid,
126 int parm);
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127int snd_hdac_override_parm(struct hdac_device *codec, hda_nid_t nid,
128 unsigned int parm, unsigned int val);
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129int snd_hdac_get_connections(struct hdac_device *codec, hda_nid_t nid,
130 hda_nid_t *conn_list, int max_conns);
131int snd_hdac_get_sub_nodes(struct hdac_device *codec, hda_nid_t nid,
132 hda_nid_t *start_id);
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133unsigned int snd_hdac_calc_stream_format(unsigned int rate,
134 unsigned int channels,
135 unsigned int format,
136 unsigned int maxbps,
137 unsigned short spdif_ctls);
138int snd_hdac_query_supported_pcm(struct hdac_device *codec, hda_nid_t nid,
139 u32 *ratesp, u64 *formatsp, unsigned int *bpsp);
140bool snd_hdac_is_supported_format(struct hdac_device *codec, hda_nid_t nid,
141 unsigned int format);
7639a06c 142
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143int snd_hdac_codec_read(struct hdac_device *hdac, hda_nid_t nid,
144 int flags, unsigned int verb, unsigned int parm);
145int snd_hdac_codec_write(struct hdac_device *hdac, hda_nid_t nid,
146 int flags, unsigned int verb, unsigned int parm);
147bool snd_hdac_check_power_state(struct hdac_device *hdac,
148 hda_nid_t nid, unsigned int target_state);
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149/**
150 * snd_hdac_read_parm - read a codec parameter
151 * @codec: the codec object
152 * @nid: NID to read a parameter
153 * @parm: parameter to read
154 *
155 * Returns -1 for error. If you need to distinguish the error more
156 * strictly, use _snd_hdac_read_parm() directly.
157 */
158static inline int snd_hdac_read_parm(struct hdac_device *codec, hda_nid_t nid,
159 int parm)
160{
161 unsigned int val;
162
163 return _snd_hdac_read_parm(codec, nid, parm, &val) < 0 ? -1 : val;
164}
165
7639a06c 166#ifdef CONFIG_PM
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167int snd_hdac_power_up(struct hdac_device *codec);
168int snd_hdac_power_down(struct hdac_device *codec);
169int snd_hdac_power_up_pm(struct hdac_device *codec);
170int snd_hdac_power_down_pm(struct hdac_device *codec);
7639a06c 171#else
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172static inline int snd_hdac_power_up(struct hdac_device *codec) { return 0; }
173static inline int snd_hdac_power_down(struct hdac_device *codec) { return 0; }
174static inline int snd_hdac_power_up_pm(struct hdac_device *codec) { return 0; }
175static inline int snd_hdac_power_down_pm(struct hdac_device *codec) { return 0; }
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176#endif
177
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178/*
179 * HD-audio codec base driver
180 */
181struct hdac_driver {
182 struct device_driver driver;
183 int type;
ec71efc9 184 const struct hda_device_id *id_table;
e3d280fc 185 int (*match)(struct hdac_device *dev, struct hdac_driver *drv);
d068ebc2 186 void (*unsol_event)(struct hdac_device *dev, unsigned int event);
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187};
188
189#define drv_to_hdac_driver(_drv) container_of(_drv, struct hdac_driver, driver)
190
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191const struct hda_device_id *
192hdac_get_device_id(struct hdac_device *hdev, struct hdac_driver *drv);
193
d068ebc2 194/*
14752412 195 * Bus verb operators
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196 */
197struct hdac_bus_ops {
198 /* send a single command */
199 int (*command)(struct hdac_bus *bus, unsigned int cmd);
200 /* get a response from the last command */
201 int (*get_response)(struct hdac_bus *bus, unsigned int addr,
202 unsigned int *res);
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203 /* control the link power */
204 int (*link_power)(struct hdac_bus *bus, bool enable);
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205};
206
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207/*
208 * Lowlevel I/O operators
209 */
210struct hdac_io_ops {
211 /* mapped register accesses */
212 void (*reg_writel)(u32 value, u32 __iomem *addr);
213 u32 (*reg_readl)(u32 __iomem *addr);
214 void (*reg_writew)(u16 value, u16 __iomem *addr);
215 u16 (*reg_readw)(u16 __iomem *addr);
216 void (*reg_writeb)(u8 value, u8 __iomem *addr);
217 u8 (*reg_readb)(u8 __iomem *addr);
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218 /* Allocation ops */
219 int (*dma_alloc_pages)(struct hdac_bus *bus, int type, size_t size,
220 struct snd_dma_buffer *buf);
221 void (*dma_free_pages)(struct hdac_bus *bus,
222 struct snd_dma_buffer *buf);
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223};
224
d068ebc2 225#define HDA_UNSOL_QUEUE_SIZE 64
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226#define HDA_MAX_CODECS 8 /* limit by controller side */
227
228/* HD Audio class code */
229#define PCI_CLASS_MULTIMEDIA_HD_AUDIO 0x0403
230
231/*
232 * CORB/RIRB
233 *
234 * Each CORB entry is 4byte, RIRB is 8byte
235 */
236struct hdac_rb {
237 __le32 *buf; /* virtual address of CORB/RIRB buffer */
238 dma_addr_t addr; /* physical address of CORB/RIRB buffer */
239 unsigned short rp, wp; /* RIRB read/write pointers */
240 int cmds[HDA_MAX_CODECS]; /* number of pending requests */
241 u32 res[HDA_MAX_CODECS]; /* last read value */
242};
d068ebc2 243
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244/*
245 * HD-audio bus base driver
246 */
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247struct hdac_bus {
248 struct device *dev;
249 const struct hdac_bus_ops *ops;
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250 const struct hdac_io_ops *io_ops;
251
252 /* h/w resources */
253 unsigned long addr;
254 void __iomem *remap_addr;
255 int irq;
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256
257 /* codec linked list */
258 struct list_head codec_list;
259 unsigned int num_codecs;
260
261 /* link caddr -> codec */
262 struct hdac_device *caddr_tbl[HDA_MAX_CODEC_ADDRESS + 1];
263
264 /* unsolicited event queue */
265 u32 unsol_queue[HDA_UNSOL_QUEUE_SIZE * 2]; /* ring buffer */
266 unsigned int unsol_rp, unsol_wp;
267 struct work_struct unsol_work;
268
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269 /* bit flags of detected codecs */
270 unsigned long codec_mask;
271
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272 /* bit flags of powered codecs */
273 unsigned long codec_powered;
274
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275 /* CORB/RIRB */
276 struct hdac_rb corb;
277 struct hdac_rb rirb;
278 unsigned int last_cmd[HDA_MAX_CODECS]; /* last sent command */
279
280 /* CORB/RIRB and position buffers */
281 struct snd_dma_buffer rb;
282 struct snd_dma_buffer posbuf;
283
284 /* hdac_stream linked list */
285 struct list_head stream_list;
286
287 /* operation state */
288 bool chip_init:1; /* h/w initialized */
289
290 /* behavior flags */
d068ebc2 291 bool sync_write:1; /* sync after verb write */
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292 bool use_posbuf:1; /* use position buffer */
293 bool snoop:1; /* enable snooping */
294 bool align_bdle_4k:1; /* BDLE align 4K boundary */
295 bool reverse_assign:1; /* assign devices in reverse order */
296 bool corbrp_self_clear:1; /* CORBRP clears itself after reset */
297
298 int bdl_pos_adj; /* BDL position adjustment */
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299
300 /* locks */
14752412 301 spinlock_t reg_lock;
d068ebc2 302 struct mutex cmd_mutex;
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303
304 /* i915 component interface */
305 struct i915_audio_component *audio_component;
306 int i915_power_refcount;
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307};
308
309int snd_hdac_bus_init(struct hdac_bus *bus, struct device *dev,
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310 const struct hdac_bus_ops *ops,
311 const struct hdac_io_ops *io_ops);
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312void snd_hdac_bus_exit(struct hdac_bus *bus);
313int snd_hdac_bus_exec_verb(struct hdac_bus *bus, unsigned int addr,
314 unsigned int cmd, unsigned int *res);
315int snd_hdac_bus_exec_verb_unlocked(struct hdac_bus *bus, unsigned int addr,
316 unsigned int cmd, unsigned int *res);
317void snd_hdac_bus_queue_event(struct hdac_bus *bus, u32 res, u32 res_ex);
318
319int snd_hdac_bus_add_device(struct hdac_bus *bus, struct hdac_device *codec);
320void snd_hdac_bus_remove_device(struct hdac_bus *bus,
321 struct hdac_device *codec);
322
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323static inline void snd_hdac_codec_link_up(struct hdac_device *codec)
324{
325 set_bit(codec->addr, &codec->bus->codec_powered);
326}
327
328static inline void snd_hdac_codec_link_down(struct hdac_device *codec)
329{
330 clear_bit(codec->addr, &codec->bus->codec_powered);
331}
332
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333int snd_hdac_bus_send_cmd(struct hdac_bus *bus, unsigned int val);
334int snd_hdac_bus_get_response(struct hdac_bus *bus, unsigned int addr,
335 unsigned int *res);
a5e7e07c 336int snd_hdac_link_power(struct hdac_device *codec, bool enable);
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337
338bool snd_hdac_bus_init_chip(struct hdac_bus *bus, bool full_reset);
339void snd_hdac_bus_stop_chip(struct hdac_bus *bus);
340void snd_hdac_bus_init_cmd_io(struct hdac_bus *bus);
341void snd_hdac_bus_stop_cmd_io(struct hdac_bus *bus);
342void snd_hdac_bus_enter_link_reset(struct hdac_bus *bus);
343void snd_hdac_bus_exit_link_reset(struct hdac_bus *bus);
344
345void snd_hdac_bus_update_rirb(struct hdac_bus *bus);
473f4145 346int snd_hdac_bus_handle_stream_irq(struct hdac_bus *bus, unsigned int status,
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347 void (*ack)(struct hdac_bus *,
348 struct hdac_stream *));
349
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350int snd_hdac_bus_alloc_stream_pages(struct hdac_bus *bus);
351void snd_hdac_bus_free_stream_pages(struct hdac_bus *bus);
352
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353/*
354 * macros for easy use
355 */
356#define _snd_hdac_chip_write(type, chip, reg, value) \
357 ((chip)->io_ops->reg_write ## type(value, (chip)->remap_addr + (reg)))
358#define _snd_hdac_chip_read(type, chip, reg) \
359 ((chip)->io_ops->reg_read ## type((chip)->remap_addr + (reg)))
360
361/* read/write a register, pass without AZX_REG_ prefix */
362#define snd_hdac_chip_writel(chip, reg, value) \
363 _snd_hdac_chip_write(l, chip, AZX_REG_ ## reg, value)
364#define snd_hdac_chip_writew(chip, reg, value) \
365 _snd_hdac_chip_write(w, chip, AZX_REG_ ## reg, value)
366#define snd_hdac_chip_writeb(chip, reg, value) \
367 _snd_hdac_chip_write(b, chip, AZX_REG_ ## reg, value)
368#define snd_hdac_chip_readl(chip, reg) \
369 _snd_hdac_chip_read(l, chip, AZX_REG_ ## reg)
370#define snd_hdac_chip_readw(chip, reg) \
371 _snd_hdac_chip_read(w, chip, AZX_REG_ ## reg)
372#define snd_hdac_chip_readb(chip, reg) \
373 _snd_hdac_chip_read(b, chip, AZX_REG_ ## reg)
374
375/* update a register, pass without AZX_REG_ prefix */
376#define snd_hdac_chip_updatel(chip, reg, mask, val) \
377 snd_hdac_chip_writel(chip, reg, \
378 (snd_hdac_chip_readl(chip, reg) & ~(mask)) | (val))
379#define snd_hdac_chip_updatew(chip, reg, mask, val) \
380 snd_hdac_chip_writew(chip, reg, \
381 (snd_hdac_chip_readw(chip, reg) & ~(mask)) | (val))
382#define snd_hdac_chip_updateb(chip, reg, mask, val) \
383 snd_hdac_chip_writeb(chip, reg, \
384 (snd_hdac_chip_readb(chip, reg) & ~(mask)) | (val))
385
386/*
387 * HD-audio stream
388 */
389struct hdac_stream {
390 struct hdac_bus *bus;
391 struct snd_dma_buffer bdl; /* BDL buffer */
392 __le32 *posbuf; /* position buffer pointer */
393 int direction; /* playback / capture (SNDRV_PCM_STREAM_*) */
394
395 unsigned int bufsize; /* size of the play buffer in bytes */
396 unsigned int period_bytes; /* size of the period in bytes */
397 unsigned int frags; /* number for period in the play buffer */
398 unsigned int fifo_size; /* FIFO size */
399
400 void __iomem *sd_addr; /* stream descriptor pointer */
401
402 u32 sd_int_sta_mask; /* stream int status mask */
403
404 /* pcm support */
405 struct snd_pcm_substream *substream; /* assigned substream,
406 * set in PCM open
407 */
408 unsigned int format_val; /* format value to be set in the
409 * controller and the codec
410 */
411 unsigned char stream_tag; /* assigned stream */
412 unsigned char index; /* stream index */
413 int assigned_key; /* last device# key assigned to */
414
415 bool opened:1;
416 bool running:1;
6d23c8f5 417 bool prepared:1;
14752412 418 bool no_period_wakeup:1;
8f3f600b 419 bool locked:1;
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420
421 /* timestamp */
422 unsigned long start_wallclk; /* start + minimum wallclk */
423 unsigned long period_wallclk; /* wallclk for period */
424 struct timecounter tc;
425 struct cyclecounter cc;
426 int delay_negative_threshold;
427
428 struct list_head list;
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429#ifdef CONFIG_SND_HDA_DSP_LOADER
430 /* DSP access mutex */
431 struct mutex dsp_mutex;
432#endif
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433};
434
435void snd_hdac_stream_init(struct hdac_bus *bus, struct hdac_stream *azx_dev,
436 int idx, int direction, int tag);
437struct hdac_stream *snd_hdac_stream_assign(struct hdac_bus *bus,
438 struct snd_pcm_substream *substream);
439void snd_hdac_stream_release(struct hdac_stream *azx_dev);
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440struct hdac_stream *snd_hdac_get_stream(struct hdac_bus *bus,
441 int dir, int stream_tag);
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442
443int snd_hdac_stream_setup(struct hdac_stream *azx_dev);
444void snd_hdac_stream_cleanup(struct hdac_stream *azx_dev);
445int snd_hdac_stream_setup_periods(struct hdac_stream *azx_dev);
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446int snd_hdac_stream_set_params(struct hdac_stream *azx_dev,
447 unsigned int format_val);
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448void snd_hdac_stream_start(struct hdac_stream *azx_dev, bool fresh_start);
449void snd_hdac_stream_clear(struct hdac_stream *azx_dev);
450void snd_hdac_stream_stop(struct hdac_stream *azx_dev);
451void snd_hdac_stream_reset(struct hdac_stream *azx_dev);
452void snd_hdac_stream_sync_trigger(struct hdac_stream *azx_dev, bool set,
453 unsigned int streams, unsigned int reg);
454void snd_hdac_stream_sync(struct hdac_stream *azx_dev, bool start,
455 unsigned int streams);
456void snd_hdac_stream_timecounter_init(struct hdac_stream *azx_dev,
457 unsigned int streams);
458/*
459 * macros for easy use
460 */
461#define _snd_hdac_stream_write(type, dev, reg, value) \
462 ((dev)->bus->io_ops->reg_write ## type(value, (dev)->sd_addr + (reg)))
463#define _snd_hdac_stream_read(type, dev, reg) \
464 ((dev)->bus->io_ops->reg_read ## type((dev)->sd_addr + (reg)))
465
466/* read/write a register, pass without AZX_REG_ prefix */
467#define snd_hdac_stream_writel(dev, reg, value) \
468 _snd_hdac_stream_write(l, dev, AZX_REG_ ## reg, value)
469#define snd_hdac_stream_writew(dev, reg, value) \
470 _snd_hdac_stream_write(w, dev, AZX_REG_ ## reg, value)
471#define snd_hdac_stream_writeb(dev, reg, value) \
472 _snd_hdac_stream_write(b, dev, AZX_REG_ ## reg, value)
473#define snd_hdac_stream_readl(dev, reg) \
474 _snd_hdac_stream_read(l, dev, AZX_REG_ ## reg)
475#define snd_hdac_stream_readw(dev, reg) \
476 _snd_hdac_stream_read(w, dev, AZX_REG_ ## reg)
477#define snd_hdac_stream_readb(dev, reg) \
478 _snd_hdac_stream_read(b, dev, AZX_REG_ ## reg)
479
480/* update a register, pass without AZX_REG_ prefix */
481#define snd_hdac_stream_updatel(dev, reg, mask, val) \
482 snd_hdac_stream_writel(dev, reg, \
483 (snd_hdac_stream_readl(dev, reg) & \
484 ~(mask)) | (val))
485#define snd_hdac_stream_updatew(dev, reg, mask, val) \
486 snd_hdac_stream_writew(dev, reg, \
487 (snd_hdac_stream_readw(dev, reg) & \
488 ~(mask)) | (val))
489#define snd_hdac_stream_updateb(dev, reg, mask, val) \
490 snd_hdac_stream_writeb(dev, reg, \
491 (snd_hdac_stream_readb(dev, reg) & \
492 ~(mask)) | (val))
493
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494#ifdef CONFIG_SND_HDA_DSP_LOADER
495/* DSP lock helpers */
496#define snd_hdac_dsp_lock_init(dev) mutex_init(&(dev)->dsp_mutex)
497#define snd_hdac_dsp_lock(dev) mutex_lock(&(dev)->dsp_mutex)
498#define snd_hdac_dsp_unlock(dev) mutex_unlock(&(dev)->dsp_mutex)
499#define snd_hdac_stream_is_locked(dev) ((dev)->locked)
500/* DSP loader helpers */
501int snd_hdac_dsp_prepare(struct hdac_stream *azx_dev, unsigned int format,
502 unsigned int byte_size, struct snd_dma_buffer *bufp);
503void snd_hdac_dsp_trigger(struct hdac_stream *azx_dev, bool start);
504void snd_hdac_dsp_cleanup(struct hdac_stream *azx_dev,
505 struct snd_dma_buffer *dmab);
506#else /* CONFIG_SND_HDA_DSP_LOADER */
507#define snd_hdac_dsp_lock_init(dev) do {} while (0)
508#define snd_hdac_dsp_lock(dev) do {} while (0)
509#define snd_hdac_dsp_unlock(dev) do {} while (0)
510#define snd_hdac_stream_is_locked(dev) 0
511
512static inline int
513snd_hdac_dsp_prepare(struct hdac_stream *azx_dev, unsigned int format,
514 unsigned int byte_size, struct snd_dma_buffer *bufp)
515{
516 return 0;
517}
518
519static inline void snd_hdac_dsp_trigger(struct hdac_stream *azx_dev, bool start)
520{
521}
522
523static inline void snd_hdac_dsp_cleanup(struct hdac_stream *azx_dev,
524 struct snd_dma_buffer *dmab)
525{
526}
527#endif /* CONFIG_SND_HDA_DSP_LOADER */
528
529
71fc4c7e
TI
530/*
531 * generic array helpers
532 */
533void *snd_array_new(struct snd_array *array);
534void snd_array_free(struct snd_array *array);
535static inline void snd_array_init(struct snd_array *array, unsigned int size,
536 unsigned int align)
537{
538 array->elem_size = size;
539 array->alloc_align = align;
540}
541
542static inline void *snd_array_elem(struct snd_array *array, unsigned int idx)
543{
544 return array->list + idx * array->elem_size;
545}
546
547static inline unsigned int snd_array_index(struct snd_array *array, void *ptr)
548{
549 return (unsigned long)(ptr - array->list) / array->elem_size;
550}
551
e3d280fc 552#endif /* __SOUND_HDAUDIO_H */