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ad96090a BS |
1 | #ifndef QEMU_ARCH_INIT_H |
2 | #define QEMU_ARCH_INIT_H | |
3 | ||
76b64a7a | 4 | |
ad96090a BS |
5 | enum { |
6 | QEMU_ARCH_ALL = -1, | |
7e3d5238 BK |
7 | QEMU_ARCH_ALPHA = (1 << 0), |
8 | QEMU_ARCH_ARM = (1 << 1), | |
9 | QEMU_ARCH_CRIS = (1 << 2), | |
10 | QEMU_ARCH_I386 = (1 << 3), | |
11 | QEMU_ARCH_M68K = (1 << 4), | |
7e3d5238 BK |
12 | QEMU_ARCH_MICROBLAZE = (1 << 6), |
13 | QEMU_ARCH_MIPS = (1 << 7), | |
14 | QEMU_ARCH_PPC = (1 << 8), | |
15 | QEMU_ARCH_S390X = (1 << 9), | |
16 | QEMU_ARCH_SH4 = (1 << 10), | |
17 | QEMU_ARCH_SPARC = (1 << 11), | |
18 | QEMU_ARCH_XTENSA = (1 << 12), | |
19 | QEMU_ARCH_OPENRISC = (1 << 13), | |
7e3d5238 | 20 | QEMU_ARCH_TRICORE = (1 << 16), |
e671711c | 21 | QEMU_ARCH_NIOS2 = (1 << 17), |
813dff13 | 22 | QEMU_ARCH_HPPA = (1 << 18), |
25fa194b | 23 | QEMU_ARCH_RISCV = (1 << 19), |
c8c35e5f | 24 | QEMU_ARCH_RX = (1 << 20), |
42f3ff00 | 25 | QEMU_ARCH_AVR = (1 << 21), |
cc68292e | 26 | QEMU_ARCH_HEXAGON = (1 << 22), |
ad96090a BS |
27 | }; |
28 | ||
29 | extern const uint32_t arch_type; | |
30 | ||
ad96090a | 31 | #endif |