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244ab90e AL |
1 | /* |
2 | * DMA helper functions | |
3 | * | |
4 | * Copyright (c) 2009 Red Hat | |
5 | * | |
6 | * This work is licensed under the terms of the GNU General Public License | |
7 | * (GNU GPL), version 2 or later. | |
8 | */ | |
9 | ||
10 | #ifndef DMA_H | |
11 | #define DMA_H | |
12 | ||
13 | #include <stdio.h> | |
022c62cb | 14 | #include "exec/memory.h" |
df32fd1c | 15 | #include "exec/address-spaces.h" |
1ad2134f | 16 | #include "hw/hw.h" |
737e150e | 17 | #include "block/block.h" |
5e5a94b6 | 18 | #include "block/accounting.h" |
9c17d615 | 19 | #include "sysemu/kvm.h" |
244ab90e | 20 | |
10dc8aef PB |
21 | typedef struct ScatterGatherEntry ScatterGatherEntry; |
22 | ||
43cf8ae6 DG |
23 | typedef enum { |
24 | DMA_DIRECTION_TO_DEVICE = 0, | |
25 | DMA_DIRECTION_FROM_DEVICE = 1, | |
26 | } DMADirection; | |
27 | ||
fead0c24 PB |
28 | struct QEMUSGList { |
29 | ScatterGatherEntry *sg; | |
30 | int nsg; | |
31 | int nalloc; | |
32 | size_t size; | |
f487b677 | 33 | DeviceState *dev; |
df32fd1c | 34 | AddressSpace *as; |
fead0c24 PB |
35 | }; |
36 | ||
4be403c8 | 37 | #ifndef CONFIG_USER_ONLY |
d9d1055e | 38 | |
e5332e63 DG |
39 | /* |
40 | * When an IOMMU is present, bus addresses become distinct from | |
41 | * CPU/memory physical addresses and may be a different size. Because | |
42 | * the IOVA size depends more on the bus than on the platform, we more | |
43 | * or less have to treat these as 64-bit always to cover all (or at | |
44 | * least most) cases. | |
45 | */ | |
46 | typedef uint64_t dma_addr_t; | |
47 | ||
48 | #define DMA_ADDR_BITS 64 | |
49 | #define DMA_ADDR_FMT "%" PRIx64 | |
50 | ||
df32fd1c | 51 | static inline void dma_barrier(AddressSpace *as, DMADirection dir) |
7a0bac4d BH |
52 | { |
53 | /* | |
54 | * This is called before DMA read and write operations | |
55 | * unless the _relaxed form is used and is responsible | |
56 | * for providing some sane ordering of accesses vs | |
57 | * concurrently running VCPUs. | |
58 | * | |
59 | * Users of map(), unmap() or lower level st/ld_* | |
60 | * operations are responsible for providing their own | |
61 | * ordering via barriers. | |
62 | * | |
63 | * This primitive implementation does a simple smp_mb() | |
64 | * before each operation which provides pretty much full | |
65 | * ordering. | |
66 | * | |
67 | * A smarter implementation can be devised if needed to | |
68 | * use lighter barriers based on the direction of the | |
69 | * transfer, the DMA context, etc... | |
70 | */ | |
71 | if (kvm_enabled()) { | |
72 | smp_mb(); | |
73 | } | |
74 | } | |
75 | ||
d86a77f8 DG |
76 | /* Checks that the given range of addresses is valid for DMA. This is |
77 | * useful for certain cases, but usually you should just use | |
78 | * dma_memory_{read,write}() and check for errors */ | |
df32fd1c | 79 | static inline bool dma_memory_valid(AddressSpace *as, |
e5332e63 DG |
80 | dma_addr_t addr, dma_addr_t len, |
81 | DMADirection dir) | |
d86a77f8 | 82 | { |
df32fd1c | 83 | return address_space_access_valid(as, addr, len, |
24addbc7 | 84 | dir == DMA_DIRECTION_FROM_DEVICE); |
d86a77f8 DG |
85 | } |
86 | ||
df32fd1c | 87 | static inline int dma_memory_rw_relaxed(AddressSpace *as, dma_addr_t addr, |
7a0bac4d BH |
88 | void *buf, dma_addr_t len, |
89 | DMADirection dir) | |
d86a77f8 | 90 | { |
df32fd1c | 91 | return address_space_rw(as, addr, buf, len, dir == DMA_DIRECTION_FROM_DEVICE); |
d86a77f8 DG |
92 | } |
93 | ||
df32fd1c | 94 | static inline int dma_memory_read_relaxed(AddressSpace *as, dma_addr_t addr, |
7a0bac4d BH |
95 | void *buf, dma_addr_t len) |
96 | { | |
df32fd1c | 97 | return dma_memory_rw_relaxed(as, addr, buf, len, DMA_DIRECTION_TO_DEVICE); |
7a0bac4d BH |
98 | } |
99 | ||
df32fd1c | 100 | static inline int dma_memory_write_relaxed(AddressSpace *as, dma_addr_t addr, |
7a0bac4d BH |
101 | const void *buf, dma_addr_t len) |
102 | { | |
df32fd1c | 103 | return dma_memory_rw_relaxed(as, addr, (void *)buf, len, |
7a0bac4d BH |
104 | DMA_DIRECTION_FROM_DEVICE); |
105 | } | |
106 | ||
df32fd1c | 107 | static inline int dma_memory_rw(AddressSpace *as, dma_addr_t addr, |
7a0bac4d BH |
108 | void *buf, dma_addr_t len, |
109 | DMADirection dir) | |
110 | { | |
df32fd1c | 111 | dma_barrier(as, dir); |
7a0bac4d | 112 | |
df32fd1c | 113 | return dma_memory_rw_relaxed(as, addr, buf, len, dir); |
7a0bac4d BH |
114 | } |
115 | ||
df32fd1c | 116 | static inline int dma_memory_read(AddressSpace *as, dma_addr_t addr, |
d86a77f8 DG |
117 | void *buf, dma_addr_t len) |
118 | { | |
df32fd1c | 119 | return dma_memory_rw(as, addr, buf, len, DMA_DIRECTION_TO_DEVICE); |
d86a77f8 DG |
120 | } |
121 | ||
df32fd1c | 122 | static inline int dma_memory_write(AddressSpace *as, dma_addr_t addr, |
d86a77f8 DG |
123 | const void *buf, dma_addr_t len) |
124 | { | |
df32fd1c | 125 | return dma_memory_rw(as, addr, (void *)buf, len, |
d86a77f8 DG |
126 | DMA_DIRECTION_FROM_DEVICE); |
127 | } | |
128 | ||
df32fd1c | 129 | int dma_memory_set(AddressSpace *as, dma_addr_t addr, uint8_t c, dma_addr_t len); |
d86a77f8 | 130 | |
df32fd1c | 131 | static inline void *dma_memory_map(AddressSpace *as, |
d86a77f8 DG |
132 | dma_addr_t addr, dma_addr_t *len, |
133 | DMADirection dir) | |
134 | { | |
24addbc7 PB |
135 | hwaddr xlen = *len; |
136 | void *p; | |
137 | ||
df32fd1c | 138 | p = address_space_map(as, addr, &xlen, dir == DMA_DIRECTION_FROM_DEVICE); |
24addbc7 PB |
139 | *len = xlen; |
140 | return p; | |
d86a77f8 DG |
141 | } |
142 | ||
df32fd1c | 143 | static inline void dma_memory_unmap(AddressSpace *as, |
d86a77f8 DG |
144 | void *buffer, dma_addr_t len, |
145 | DMADirection dir, dma_addr_t access_len) | |
146 | { | |
df32fd1c | 147 | address_space_unmap(as, buffer, (hwaddr)len, |
24addbc7 | 148 | dir == DMA_DIRECTION_FROM_DEVICE, access_len); |
d86a77f8 DG |
149 | } |
150 | ||
151 | #define DEFINE_LDST_DMA(_lname, _sname, _bits, _end) \ | |
df32fd1c | 152 | static inline uint##_bits##_t ld##_lname##_##_end##_dma(AddressSpace *as, \ |
d86a77f8 DG |
153 | dma_addr_t addr) \ |
154 | { \ | |
155 | uint##_bits##_t val; \ | |
df32fd1c | 156 | dma_memory_read(as, addr, &val, (_bits) / 8); \ |
d86a77f8 DG |
157 | return _end##_bits##_to_cpu(val); \ |
158 | } \ | |
df32fd1c | 159 | static inline void st##_sname##_##_end##_dma(AddressSpace *as, \ |
d86a77f8 DG |
160 | dma_addr_t addr, \ |
161 | uint##_bits##_t val) \ | |
162 | { \ | |
163 | val = cpu_to_##_end##_bits(val); \ | |
df32fd1c | 164 | dma_memory_write(as, addr, &val, (_bits) / 8); \ |
d86a77f8 DG |
165 | } |
166 | ||
df32fd1c | 167 | static inline uint8_t ldub_dma(AddressSpace *as, dma_addr_t addr) |
d86a77f8 DG |
168 | { |
169 | uint8_t val; | |
170 | ||
df32fd1c | 171 | dma_memory_read(as, addr, &val, 1); |
d86a77f8 DG |
172 | return val; |
173 | } | |
174 | ||
df32fd1c | 175 | static inline void stb_dma(AddressSpace *as, dma_addr_t addr, uint8_t val) |
d86a77f8 | 176 | { |
df32fd1c | 177 | dma_memory_write(as, addr, &val, 1); |
d86a77f8 DG |
178 | } |
179 | ||
180 | DEFINE_LDST_DMA(uw, w, 16, le); | |
181 | DEFINE_LDST_DMA(l, l, 32, le); | |
182 | DEFINE_LDST_DMA(q, q, 64, le); | |
183 | DEFINE_LDST_DMA(uw, w, 16, be); | |
184 | DEFINE_LDST_DMA(l, l, 32, be); | |
185 | DEFINE_LDST_DMA(q, q, 64, be); | |
186 | ||
187 | #undef DEFINE_LDST_DMA | |
188 | ||
10dc8aef | 189 | struct ScatterGatherEntry { |
d3231181 DG |
190 | dma_addr_t base; |
191 | dma_addr_t len; | |
10dc8aef | 192 | }; |
244ab90e | 193 | |
f487b677 PB |
194 | void qemu_sglist_init(QEMUSGList *qsg, DeviceState *dev, int alloc_hint, |
195 | AddressSpace *as); | |
d3231181 | 196 | void qemu_sglist_add(QEMUSGList *qsg, dma_addr_t base, dma_addr_t len); |
244ab90e | 197 | void qemu_sglist_destroy(QEMUSGList *qsg); |
10dc8aef | 198 | #endif |
244ab90e | 199 | |
7c84b1b8 MA |
200 | typedef BlockAIOCB *DMAIOFunc(BlockDriverState *bs, int64_t sector_num, |
201 | QEMUIOVector *iov, int nb_sectors, | |
202 | BlockDriverCompletionFunc *cb, void *opaque); | |
203 | ||
204 | BlockAIOCB *dma_bdrv_io(BlockDriverState *bs, | |
205 | QEMUSGList *sg, uint64_t sector_num, | |
206 | DMAIOFunc *io_func, BlockDriverCompletionFunc *cb, | |
207 | void *opaque, DMADirection dir); | |
208 | BlockAIOCB *dma_bdrv_read(BlockDriverState *bs, | |
209 | QEMUSGList *sg, uint64_t sector, | |
210 | BlockDriverCompletionFunc *cb, void *opaque); | |
211 | BlockAIOCB *dma_bdrv_write(BlockDriverState *bs, | |
212 | QEMUSGList *sg, uint64_t sector, | |
213 | BlockDriverCompletionFunc *cb, void *opaque); | |
8171ee35 PB |
214 | uint64_t dma_buf_read(uint8_t *ptr, int32_t len, QEMUSGList *sg); |
215 | uint64_t dma_buf_write(uint8_t *ptr, int32_t len, QEMUSGList *sg); | |
216 | ||
84a69356 PB |
217 | void dma_acct_start(BlockDriverState *bs, BlockAcctCookie *cookie, |
218 | QEMUSGList *sg, enum BlockAcctType type); | |
219 | ||
244ab90e | 220 | #endif |