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Commit | Line | Data |
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ad3d0e4d | 1 | /* SPDX-License-Identifier: MIT */ |
c896fe29 | 2 | /* |
ad3d0e4d | 3 | * Target dependent opcode generation functions. |
c896fe29 FB |
4 | * |
5 | * Copyright (c) 2008 Fabrice Bellard | |
c896fe29 | 6 | */ |
951c6300 | 7 | |
a7ce790a PM |
8 | #ifndef TCG_TCG_OP_H |
9 | #define TCG_TCG_OP_H | |
10 | ||
ad3d0e4d | 11 | #include "tcg/tcg-op-common.h" |
c896fe29 | 12 | |
951c6300 RH |
13 | #ifndef TARGET_LONG_BITS |
14 | #error must include QEMU headers | |
15 | #endif | |
c896fe29 | 16 | |
ff0c61bf RH |
17 | #if TARGET_LONG_BITS == 32 |
18 | # define TCG_TYPE_TL TCG_TYPE_I32 | |
19 | #elif TARGET_LONG_BITS == 64 | |
20 | # define TCG_TYPE_TL TCG_TYPE_I64 | |
21 | #else | |
22 | # error | |
23 | #endif | |
24 | ||
747bd69d | 25 | #ifndef TARGET_INSN_START_EXTRA_WORDS |
9aef40ed | 26 | static inline void tcg_gen_insn_start(target_ulong pc) |
c896fe29 | 27 | { |
c9ad8d27 RH |
28 | TCGOp *op = tcg_emit_op(INDEX_op_insn_start, 64 / TCG_TARGET_REG_BITS); |
29 | tcg_set_insn_start_param(op, 0, pc); | |
9aef40ed | 30 | } |
747bd69d | 31 | #elif TARGET_INSN_START_EXTRA_WORDS == 1 |
9aef40ed RH |
32 | static inline void tcg_gen_insn_start(target_ulong pc, target_ulong a1) |
33 | { | |
c9ad8d27 RH |
34 | TCGOp *op = tcg_emit_op(INDEX_op_insn_start, 2 * 64 / TCG_TARGET_REG_BITS); |
35 | tcg_set_insn_start_param(op, 0, pc); | |
36 | tcg_set_insn_start_param(op, 1, a1); | |
9aef40ed | 37 | } |
747bd69d | 38 | #elif TARGET_INSN_START_EXTRA_WORDS == 2 |
9aef40ed RH |
39 | static inline void tcg_gen_insn_start(target_ulong pc, target_ulong a1, |
40 | target_ulong a2) | |
41 | { | |
c9ad8d27 RH |
42 | TCGOp *op = tcg_emit_op(INDEX_op_insn_start, 3 * 64 / TCG_TARGET_REG_BITS); |
43 | tcg_set_insn_start_param(op, 0, pc); | |
44 | tcg_set_insn_start_param(op, 1, a1); | |
45 | tcg_set_insn_start_param(op, 2, a2); | |
9aef40ed | 46 | } |
951c6300 | 47 | #else |
747bd69d | 48 | #error Unhandled TARGET_INSN_START_EXTRA_WORDS value |
951c6300 | 49 | #endif |
c896fe29 | 50 | |
a7812ae4 | 51 | #if TARGET_LONG_BITS == 32 |
f15f8935 | 52 | typedef TCGv_i32 TCGv; |
a7812ae4 | 53 | #define tcg_temp_new() tcg_temp_new_i32() |
a7812ae4 | 54 | #define tcg_global_mem_new tcg_global_mem_new_i32 |
d5920b72 | 55 | #define tcgv_tl_temp tcgv_i32_temp |
f713d6ad RH |
56 | #define tcg_gen_qemu_ld_tl tcg_gen_qemu_ld_i32 |
57 | #define tcg_gen_qemu_st_tl tcg_gen_qemu_st_i32 | |
f15f8935 RH |
58 | #elif TARGET_LONG_BITS == 64 |
59 | typedef TCGv_i64 TCGv; | |
a7812ae4 | 60 | #define tcg_temp_new() tcg_temp_new_i64() |
a7812ae4 | 61 | #define tcg_global_mem_new tcg_global_mem_new_i64 |
d5920b72 | 62 | #define tcgv_tl_temp tcgv_i64_temp |
f713d6ad RH |
63 | #define tcg_gen_qemu_ld_tl tcg_gen_qemu_ld_i64 |
64 | #define tcg_gen_qemu_st_tl tcg_gen_qemu_st_i64 | |
f15f8935 RH |
65 | #else |
66 | #error Unhandled TARGET_LONG_BITS value | |
a7812ae4 PB |
67 | #endif |
68 | ||
d5920b72 RH |
69 | static inline void |
70 | tcg_gen_qemu_ld_i32(TCGv_i32 v, TCGv a, TCGArg i, MemOp m) | |
71 | { | |
72 | tcg_gen_qemu_ld_i32_chk(v, tcgv_tl_temp(a), i, m, TCG_TYPE_TL); | |
73 | } | |
74 | ||
75 | static inline void | |
76 | tcg_gen_qemu_st_i32(TCGv_i32 v, TCGv a, TCGArg i, MemOp m) | |
77 | { | |
78 | tcg_gen_qemu_st_i32_chk(v, tcgv_tl_temp(a), i, m, TCG_TYPE_TL); | |
79 | } | |
80 | ||
81 | static inline void | |
82 | tcg_gen_qemu_ld_i64(TCGv_i64 v, TCGv a, TCGArg i, MemOp m) | |
83 | { | |
84 | tcg_gen_qemu_ld_i64_chk(v, tcgv_tl_temp(a), i, m, TCG_TYPE_TL); | |
85 | } | |
86 | ||
87 | static inline void | |
88 | tcg_gen_qemu_st_i64(TCGv_i64 v, TCGv a, TCGArg i, MemOp m) | |
89 | { | |
90 | tcg_gen_qemu_st_i64_chk(v, tcgv_tl_temp(a), i, m, TCG_TYPE_TL); | |
91 | } | |
92 | ||
93 | static inline void | |
94 | tcg_gen_qemu_ld_i128(TCGv_i128 v, TCGv a, TCGArg i, MemOp m) | |
95 | { | |
96 | tcg_gen_qemu_ld_i128_chk(v, tcgv_tl_temp(a), i, m, TCG_TYPE_TL); | |
97 | } | |
98 | ||
99 | static inline void | |
100 | tcg_gen_qemu_st_i128(TCGv_i128 v, TCGv a, TCGArg i, MemOp m) | |
101 | { | |
102 | tcg_gen_qemu_st_i128_chk(v, tcgv_tl_temp(a), i, m, TCG_TYPE_TL); | |
103 | } | |
c896fe29 | 104 | |
0700ceb3 RH |
105 | #define DEF_ATOMIC2(N, S) \ |
106 | static inline void N##_##S(TCGv_##S r, TCGv a, TCGv_##S v, \ | |
107 | TCGArg i, MemOp m) \ | |
108 | { N##_##S##_chk(r, tcgv_tl_temp(a), v, i, m, TCG_TYPE_TL); } | |
109 | ||
110 | #define DEF_ATOMIC3(N, S) \ | |
111 | static inline void N##_##S(TCGv_##S r, TCGv a, TCGv_##S o, \ | |
112 | TCGv_##S n, TCGArg i, MemOp m) \ | |
113 | { N##_##S##_chk(r, tcgv_tl_temp(a), o, n, i, m, TCG_TYPE_TL); } | |
114 | ||
115 | DEF_ATOMIC3(tcg_gen_atomic_cmpxchg, i32) | |
116 | DEF_ATOMIC3(tcg_gen_atomic_cmpxchg, i64) | |
117 | DEF_ATOMIC3(tcg_gen_atomic_cmpxchg, i128) | |
118 | ||
119 | DEF_ATOMIC3(tcg_gen_nonatomic_cmpxchg, i32) | |
120 | DEF_ATOMIC3(tcg_gen_nonatomic_cmpxchg, i64) | |
121 | DEF_ATOMIC3(tcg_gen_nonatomic_cmpxchg, i128) | |
122 | ||
123 | DEF_ATOMIC2(tcg_gen_atomic_xchg, i32) | |
124 | DEF_ATOMIC2(tcg_gen_atomic_xchg, i64) | |
125 | ||
126 | DEF_ATOMIC2(tcg_gen_atomic_fetch_add, i32) | |
127 | DEF_ATOMIC2(tcg_gen_atomic_fetch_add, i64) | |
128 | DEF_ATOMIC2(tcg_gen_atomic_fetch_and, i32) | |
129 | DEF_ATOMIC2(tcg_gen_atomic_fetch_and, i64) | |
130 | DEF_ATOMIC2(tcg_gen_atomic_fetch_or, i32) | |
131 | DEF_ATOMIC2(tcg_gen_atomic_fetch_or, i64) | |
132 | DEF_ATOMIC2(tcg_gen_atomic_fetch_xor, i32) | |
133 | DEF_ATOMIC2(tcg_gen_atomic_fetch_xor, i64) | |
134 | DEF_ATOMIC2(tcg_gen_atomic_fetch_smin, i32) | |
135 | DEF_ATOMIC2(tcg_gen_atomic_fetch_smin, i64) | |
136 | DEF_ATOMIC2(tcg_gen_atomic_fetch_umin, i32) | |
137 | DEF_ATOMIC2(tcg_gen_atomic_fetch_umin, i64) | |
138 | DEF_ATOMIC2(tcg_gen_atomic_fetch_smax, i32) | |
139 | DEF_ATOMIC2(tcg_gen_atomic_fetch_smax, i64) | |
140 | DEF_ATOMIC2(tcg_gen_atomic_fetch_umax, i32) | |
141 | DEF_ATOMIC2(tcg_gen_atomic_fetch_umax, i64) | |
142 | ||
143 | DEF_ATOMIC2(tcg_gen_atomic_add_fetch, i32) | |
144 | DEF_ATOMIC2(tcg_gen_atomic_add_fetch, i64) | |
145 | DEF_ATOMIC2(tcg_gen_atomic_and_fetch, i32) | |
146 | DEF_ATOMIC2(tcg_gen_atomic_and_fetch, i64) | |
147 | DEF_ATOMIC2(tcg_gen_atomic_or_fetch, i32) | |
148 | DEF_ATOMIC2(tcg_gen_atomic_or_fetch, i64) | |
149 | DEF_ATOMIC2(tcg_gen_atomic_xor_fetch, i32) | |
150 | DEF_ATOMIC2(tcg_gen_atomic_xor_fetch, i64) | |
151 | DEF_ATOMIC2(tcg_gen_atomic_smin_fetch, i32) | |
152 | DEF_ATOMIC2(tcg_gen_atomic_smin_fetch, i64) | |
153 | DEF_ATOMIC2(tcg_gen_atomic_umin_fetch, i32) | |
154 | DEF_ATOMIC2(tcg_gen_atomic_umin_fetch, i64) | |
155 | DEF_ATOMIC2(tcg_gen_atomic_smax_fetch, i32) | |
156 | DEF_ATOMIC2(tcg_gen_atomic_smax_fetch, i64) | |
157 | DEF_ATOMIC2(tcg_gen_atomic_umax_fetch, i32) | |
158 | DEF_ATOMIC2(tcg_gen_atomic_umax_fetch, i64) | |
159 | ||
160 | #undef DEF_ATOMIC2 | |
161 | #undef DEF_ATOMIC3 | |
c482cb11 | 162 | |
f8422f52 | 163 | #if TARGET_LONG_BITS == 64 |
f8422f52 BS |
164 | #define tcg_gen_movi_tl tcg_gen_movi_i64 |
165 | #define tcg_gen_mov_tl tcg_gen_mov_i64 | |
166 | #define tcg_gen_ld8u_tl tcg_gen_ld8u_i64 | |
167 | #define tcg_gen_ld8s_tl tcg_gen_ld8s_i64 | |
168 | #define tcg_gen_ld16u_tl tcg_gen_ld16u_i64 | |
169 | #define tcg_gen_ld16s_tl tcg_gen_ld16s_i64 | |
170 | #define tcg_gen_ld32u_tl tcg_gen_ld32u_i64 | |
171 | #define tcg_gen_ld32s_tl tcg_gen_ld32s_i64 | |
172 | #define tcg_gen_ld_tl tcg_gen_ld_i64 | |
173 | #define tcg_gen_st8_tl tcg_gen_st8_i64 | |
174 | #define tcg_gen_st16_tl tcg_gen_st16_i64 | |
175 | #define tcg_gen_st32_tl tcg_gen_st32_i64 | |
176 | #define tcg_gen_st_tl tcg_gen_st_i64 | |
177 | #define tcg_gen_add_tl tcg_gen_add_i64 | |
178 | #define tcg_gen_addi_tl tcg_gen_addi_i64 | |
179 | #define tcg_gen_sub_tl tcg_gen_sub_i64 | |
390efc54 | 180 | #define tcg_gen_neg_tl tcg_gen_neg_i64 |
ff1f11f7 | 181 | #define tcg_gen_abs_tl tcg_gen_abs_i64 |
10460c8a | 182 | #define tcg_gen_subfi_tl tcg_gen_subfi_i64 |
f8422f52 BS |
183 | #define tcg_gen_subi_tl tcg_gen_subi_i64 |
184 | #define tcg_gen_and_tl tcg_gen_and_i64 | |
185 | #define tcg_gen_andi_tl tcg_gen_andi_i64 | |
186 | #define tcg_gen_or_tl tcg_gen_or_i64 | |
187 | #define tcg_gen_ori_tl tcg_gen_ori_i64 | |
188 | #define tcg_gen_xor_tl tcg_gen_xor_i64 | |
189 | #define tcg_gen_xori_tl tcg_gen_xori_i64 | |
0b6ce4cf | 190 | #define tcg_gen_not_tl tcg_gen_not_i64 |
f8422f52 BS |
191 | #define tcg_gen_shl_tl tcg_gen_shl_i64 |
192 | #define tcg_gen_shli_tl tcg_gen_shli_i64 | |
193 | #define tcg_gen_shr_tl tcg_gen_shr_i64 | |
194 | #define tcg_gen_shri_tl tcg_gen_shri_i64 | |
195 | #define tcg_gen_sar_tl tcg_gen_sar_i64 | |
196 | #define tcg_gen_sari_tl tcg_gen_sari_i64 | |
0cf767d6 | 197 | #define tcg_gen_brcond_tl tcg_gen_brcond_i64 |
cb63669a | 198 | #define tcg_gen_brcondi_tl tcg_gen_brcondi_i64 |
be210acb | 199 | #define tcg_gen_setcond_tl tcg_gen_setcond_i64 |
add1e7ea | 200 | #define tcg_gen_setcondi_tl tcg_gen_setcondi_i64 |
3635502d | 201 | #define tcg_gen_negsetcond_tl tcg_gen_negsetcond_i64 |
93c86ecd | 202 | #define tcg_gen_negsetcondi_tl tcg_gen_negsetcondi_i64 |
f730fd27 TS |
203 | #define tcg_gen_mul_tl tcg_gen_mul_i64 |
204 | #define tcg_gen_muli_tl tcg_gen_muli_i64 | |
ab36421e AJ |
205 | #define tcg_gen_div_tl tcg_gen_div_i64 |
206 | #define tcg_gen_rem_tl tcg_gen_rem_i64 | |
864951af AJ |
207 | #define tcg_gen_divu_tl tcg_gen_divu_i64 |
208 | #define tcg_gen_remu_tl tcg_gen_remu_i64 | |
a768e4b2 | 209 | #define tcg_gen_discard_tl tcg_gen_discard_i64 |
ecc7b3aa | 210 | #define tcg_gen_trunc_tl_i32 tcg_gen_extrl_i64_i32 |
e429073d BS |
211 | #define tcg_gen_trunc_i64_tl tcg_gen_mov_i64 |
212 | #define tcg_gen_extu_i32_tl tcg_gen_extu_i32_i64 | |
213 | #define tcg_gen_ext_i32_tl tcg_gen_ext_i32_i64 | |
214 | #define tcg_gen_extu_tl_i64 tcg_gen_mov_i64 | |
215 | #define tcg_gen_ext_tl_i64 tcg_gen_mov_i64 | |
0b6ce4cf FB |
216 | #define tcg_gen_ext8u_tl tcg_gen_ext8u_i64 |
217 | #define tcg_gen_ext8s_tl tcg_gen_ext8s_i64 | |
218 | #define tcg_gen_ext16u_tl tcg_gen_ext16u_i64 | |
219 | #define tcg_gen_ext16s_tl tcg_gen_ext16s_i64 | |
220 | #define tcg_gen_ext32u_tl tcg_gen_ext32u_i64 | |
221 | #define tcg_gen_ext32s_tl tcg_gen_ext32s_i64 | |
f1c29532 | 222 | #define tcg_gen_ext_tl tcg_gen_ext_i64 |
911d79ba AJ |
223 | #define tcg_gen_bswap16_tl tcg_gen_bswap16_i64 |
224 | #define tcg_gen_bswap32_tl tcg_gen_bswap32_i64 | |
225 | #define tcg_gen_bswap64_tl tcg_gen_bswap64_i64 | |
a66424ba | 226 | #define tcg_gen_bswap_tl tcg_gen_bswap64_i64 |
46be8425 RH |
227 | #define tcg_gen_hswap_tl tcg_gen_hswap_i64 |
228 | #define tcg_gen_wswap_tl tcg_gen_wswap_i64 | |
945ca823 | 229 | #define tcg_gen_concat_tl_i64 tcg_gen_concat32_i64 |
3c51a985 | 230 | #define tcg_gen_extr_i64_tl tcg_gen_extr32_i64 |
f24cb33e AJ |
231 | #define tcg_gen_andc_tl tcg_gen_andc_i64 |
232 | #define tcg_gen_eqv_tl tcg_gen_eqv_i64 | |
233 | #define tcg_gen_nand_tl tcg_gen_nand_i64 | |
234 | #define tcg_gen_nor_tl tcg_gen_nor_i64 | |
235 | #define tcg_gen_orc_tl tcg_gen_orc_i64 | |
0e28d006 RH |
236 | #define tcg_gen_clz_tl tcg_gen_clz_i64 |
237 | #define tcg_gen_ctz_tl tcg_gen_ctz_i64 | |
238 | #define tcg_gen_clzi_tl tcg_gen_clzi_i64 | |
239 | #define tcg_gen_ctzi_tl tcg_gen_ctzi_i64 | |
086920c2 | 240 | #define tcg_gen_clrsb_tl tcg_gen_clrsb_i64 |
a768e4e9 | 241 | #define tcg_gen_ctpop_tl tcg_gen_ctpop_i64 |
15824571 AJ |
242 | #define tcg_gen_rotl_tl tcg_gen_rotl_i64 |
243 | #define tcg_gen_rotli_tl tcg_gen_rotli_i64 | |
244 | #define tcg_gen_rotr_tl tcg_gen_rotr_i64 | |
245 | #define tcg_gen_rotri_tl tcg_gen_rotri_i64 | |
b7767f0f | 246 | #define tcg_gen_deposit_tl tcg_gen_deposit_i64 |
07cc68d5 | 247 | #define tcg_gen_deposit_z_tl tcg_gen_deposit_z_i64 |
7ec8bab3 RH |
248 | #define tcg_gen_extract_tl tcg_gen_extract_i64 |
249 | #define tcg_gen_sextract_tl tcg_gen_sextract_i64 | |
2089fcc9 | 250 | #define tcg_gen_extract2_tl tcg_gen_extract2_i64 |
4d87fcdd | 251 | #define tcg_constant_tl tcg_constant_i64 |
ffc5ea09 | 252 | #define tcg_gen_movcond_tl tcg_gen_movcond_i64 |
f6953a73 RH |
253 | #define tcg_gen_add2_tl tcg_gen_add2_i64 |
254 | #define tcg_gen_sub2_tl tcg_gen_sub2_i64 | |
696a8be6 RH |
255 | #define tcg_gen_mulu2_tl tcg_gen_mulu2_i64 |
256 | #define tcg_gen_muls2_tl tcg_gen_muls2_i64 | |
5087abfb | 257 | #define tcg_gen_mulsu2_tl tcg_gen_mulsu2_i64 |
b87fb8cd RH |
258 | #define tcg_gen_smin_tl tcg_gen_smin_i64 |
259 | #define tcg_gen_umin_tl tcg_gen_umin_i64 | |
260 | #define tcg_gen_smax_tl tcg_gen_smax_i64 | |
261 | #define tcg_gen_umax_tl tcg_gen_umax_i64 | |
c482cb11 RH |
262 | #define tcg_gen_atomic_cmpxchg_tl tcg_gen_atomic_cmpxchg_i64 |
263 | #define tcg_gen_atomic_xchg_tl tcg_gen_atomic_xchg_i64 | |
264 | #define tcg_gen_atomic_fetch_add_tl tcg_gen_atomic_fetch_add_i64 | |
265 | #define tcg_gen_atomic_fetch_and_tl tcg_gen_atomic_fetch_and_i64 | |
266 | #define tcg_gen_atomic_fetch_or_tl tcg_gen_atomic_fetch_or_i64 | |
267 | #define tcg_gen_atomic_fetch_xor_tl tcg_gen_atomic_fetch_xor_i64 | |
5507c2bf RH |
268 | #define tcg_gen_atomic_fetch_smin_tl tcg_gen_atomic_fetch_smin_i64 |
269 | #define tcg_gen_atomic_fetch_umin_tl tcg_gen_atomic_fetch_umin_i64 | |
270 | #define tcg_gen_atomic_fetch_smax_tl tcg_gen_atomic_fetch_smax_i64 | |
271 | #define tcg_gen_atomic_fetch_umax_tl tcg_gen_atomic_fetch_umax_i64 | |
c482cb11 RH |
272 | #define tcg_gen_atomic_add_fetch_tl tcg_gen_atomic_add_fetch_i64 |
273 | #define tcg_gen_atomic_and_fetch_tl tcg_gen_atomic_and_fetch_i64 | |
274 | #define tcg_gen_atomic_or_fetch_tl tcg_gen_atomic_or_fetch_i64 | |
275 | #define tcg_gen_atomic_xor_fetch_tl tcg_gen_atomic_xor_fetch_i64 | |
5507c2bf RH |
276 | #define tcg_gen_atomic_smin_fetch_tl tcg_gen_atomic_smin_fetch_i64 |
277 | #define tcg_gen_atomic_umin_fetch_tl tcg_gen_atomic_umin_fetch_i64 | |
278 | #define tcg_gen_atomic_smax_fetch_tl tcg_gen_atomic_smax_fetch_i64 | |
279 | #define tcg_gen_atomic_umax_fetch_tl tcg_gen_atomic_umax_fetch_i64 | |
d2fd745f | 280 | #define tcg_gen_dup_tl_vec tcg_gen_dup_i64_vec |
614dd4f3 | 281 | #define tcg_gen_dup_tl tcg_gen_dup_i64 |
f15f8935 | 282 | #define dup_const_tl dup_const |
f8422f52 | 283 | #else |
f8422f52 BS |
284 | #define tcg_gen_movi_tl tcg_gen_movi_i32 |
285 | #define tcg_gen_mov_tl tcg_gen_mov_i32 | |
286 | #define tcg_gen_ld8u_tl tcg_gen_ld8u_i32 | |
287 | #define tcg_gen_ld8s_tl tcg_gen_ld8s_i32 | |
288 | #define tcg_gen_ld16u_tl tcg_gen_ld16u_i32 | |
289 | #define tcg_gen_ld16s_tl tcg_gen_ld16s_i32 | |
290 | #define tcg_gen_ld32u_tl tcg_gen_ld_i32 | |
291 | #define tcg_gen_ld32s_tl tcg_gen_ld_i32 | |
292 | #define tcg_gen_ld_tl tcg_gen_ld_i32 | |
293 | #define tcg_gen_st8_tl tcg_gen_st8_i32 | |
294 | #define tcg_gen_st16_tl tcg_gen_st16_i32 | |
295 | #define tcg_gen_st32_tl tcg_gen_st_i32 | |
296 | #define tcg_gen_st_tl tcg_gen_st_i32 | |
297 | #define tcg_gen_add_tl tcg_gen_add_i32 | |
298 | #define tcg_gen_addi_tl tcg_gen_addi_i32 | |
299 | #define tcg_gen_sub_tl tcg_gen_sub_i32 | |
390efc54 | 300 | #define tcg_gen_neg_tl tcg_gen_neg_i32 |
ff1f11f7 | 301 | #define tcg_gen_abs_tl tcg_gen_abs_i32 |
0045734a | 302 | #define tcg_gen_subfi_tl tcg_gen_subfi_i32 |
f8422f52 BS |
303 | #define tcg_gen_subi_tl tcg_gen_subi_i32 |
304 | #define tcg_gen_and_tl tcg_gen_and_i32 | |
305 | #define tcg_gen_andi_tl tcg_gen_andi_i32 | |
306 | #define tcg_gen_or_tl tcg_gen_or_i32 | |
307 | #define tcg_gen_ori_tl tcg_gen_ori_i32 | |
308 | #define tcg_gen_xor_tl tcg_gen_xor_i32 | |
309 | #define tcg_gen_xori_tl tcg_gen_xori_i32 | |
0b6ce4cf | 310 | #define tcg_gen_not_tl tcg_gen_not_i32 |
f8422f52 BS |
311 | #define tcg_gen_shl_tl tcg_gen_shl_i32 |
312 | #define tcg_gen_shli_tl tcg_gen_shli_i32 | |
313 | #define tcg_gen_shr_tl tcg_gen_shr_i32 | |
314 | #define tcg_gen_shri_tl tcg_gen_shri_i32 | |
315 | #define tcg_gen_sar_tl tcg_gen_sar_i32 | |
316 | #define tcg_gen_sari_tl tcg_gen_sari_i32 | |
0cf767d6 | 317 | #define tcg_gen_brcond_tl tcg_gen_brcond_i32 |
cb63669a | 318 | #define tcg_gen_brcondi_tl tcg_gen_brcondi_i32 |
be210acb | 319 | #define tcg_gen_setcond_tl tcg_gen_setcond_i32 |
add1e7ea | 320 | #define tcg_gen_setcondi_tl tcg_gen_setcondi_i32 |
3635502d | 321 | #define tcg_gen_negsetcond_tl tcg_gen_negsetcond_i32 |
93c86ecd | 322 | #define tcg_gen_negsetcondi_tl tcg_gen_negsetcondi_i32 |
f730fd27 TS |
323 | #define tcg_gen_mul_tl tcg_gen_mul_i32 |
324 | #define tcg_gen_muli_tl tcg_gen_muli_i32 | |
ab36421e AJ |
325 | #define tcg_gen_div_tl tcg_gen_div_i32 |
326 | #define tcg_gen_rem_tl tcg_gen_rem_i32 | |
864951af AJ |
327 | #define tcg_gen_divu_tl tcg_gen_divu_i32 |
328 | #define tcg_gen_remu_tl tcg_gen_remu_i32 | |
a768e4b2 | 329 | #define tcg_gen_discard_tl tcg_gen_discard_i32 |
e429073d | 330 | #define tcg_gen_trunc_tl_i32 tcg_gen_mov_i32 |
ecc7b3aa | 331 | #define tcg_gen_trunc_i64_tl tcg_gen_extrl_i64_i32 |
e429073d BS |
332 | #define tcg_gen_extu_i32_tl tcg_gen_mov_i32 |
333 | #define tcg_gen_ext_i32_tl tcg_gen_mov_i32 | |
334 | #define tcg_gen_extu_tl_i64 tcg_gen_extu_i32_i64 | |
335 | #define tcg_gen_ext_tl_i64 tcg_gen_ext_i32_i64 | |
0b6ce4cf FB |
336 | #define tcg_gen_ext8u_tl tcg_gen_ext8u_i32 |
337 | #define tcg_gen_ext8s_tl tcg_gen_ext8s_i32 | |
338 | #define tcg_gen_ext16u_tl tcg_gen_ext16u_i32 | |
339 | #define tcg_gen_ext16s_tl tcg_gen_ext16s_i32 | |
340 | #define tcg_gen_ext32u_tl tcg_gen_mov_i32 | |
341 | #define tcg_gen_ext32s_tl tcg_gen_mov_i32 | |
f1c29532 | 342 | #define tcg_gen_ext_tl tcg_gen_ext_i32 |
911d79ba | 343 | #define tcg_gen_bswap16_tl tcg_gen_bswap16_i32 |
2b836c2a | 344 | #define tcg_gen_bswap32_tl(D, S, F) tcg_gen_bswap32_i32(D, S) |
a66424ba | 345 | #define tcg_gen_bswap_tl tcg_gen_bswap32_i32 |
46be8425 | 346 | #define tcg_gen_hswap_tl tcg_gen_hswap_i32 |
945ca823 | 347 | #define tcg_gen_concat_tl_i64 tcg_gen_concat_i32_i64 |
e3eb9806 | 348 | #define tcg_gen_extr_i64_tl tcg_gen_extr_i64_i32 |
f24cb33e AJ |
349 | #define tcg_gen_andc_tl tcg_gen_andc_i32 |
350 | #define tcg_gen_eqv_tl tcg_gen_eqv_i32 | |
351 | #define tcg_gen_nand_tl tcg_gen_nand_i32 | |
352 | #define tcg_gen_nor_tl tcg_gen_nor_i32 | |
353 | #define tcg_gen_orc_tl tcg_gen_orc_i32 | |
0e28d006 RH |
354 | #define tcg_gen_clz_tl tcg_gen_clz_i32 |
355 | #define tcg_gen_ctz_tl tcg_gen_ctz_i32 | |
356 | #define tcg_gen_clzi_tl tcg_gen_clzi_i32 | |
357 | #define tcg_gen_ctzi_tl tcg_gen_ctzi_i32 | |
086920c2 | 358 | #define tcg_gen_clrsb_tl tcg_gen_clrsb_i32 |
a768e4e9 | 359 | #define tcg_gen_ctpop_tl tcg_gen_ctpop_i32 |
15824571 AJ |
360 | #define tcg_gen_rotl_tl tcg_gen_rotl_i32 |
361 | #define tcg_gen_rotli_tl tcg_gen_rotli_i32 | |
362 | #define tcg_gen_rotr_tl tcg_gen_rotr_i32 | |
363 | #define tcg_gen_rotri_tl tcg_gen_rotri_i32 | |
b7767f0f | 364 | #define tcg_gen_deposit_tl tcg_gen_deposit_i32 |
07cc68d5 | 365 | #define tcg_gen_deposit_z_tl tcg_gen_deposit_z_i32 |
7ec8bab3 RH |
366 | #define tcg_gen_extract_tl tcg_gen_extract_i32 |
367 | #define tcg_gen_sextract_tl tcg_gen_sextract_i32 | |
2089fcc9 | 368 | #define tcg_gen_extract2_tl tcg_gen_extract2_i32 |
4d87fcdd | 369 | #define tcg_constant_tl tcg_constant_i32 |
ffc5ea09 | 370 | #define tcg_gen_movcond_tl tcg_gen_movcond_i32 |
f6953a73 RH |
371 | #define tcg_gen_add2_tl tcg_gen_add2_i32 |
372 | #define tcg_gen_sub2_tl tcg_gen_sub2_i32 | |
696a8be6 RH |
373 | #define tcg_gen_mulu2_tl tcg_gen_mulu2_i32 |
374 | #define tcg_gen_muls2_tl tcg_gen_muls2_i32 | |
5087abfb | 375 | #define tcg_gen_mulsu2_tl tcg_gen_mulsu2_i32 |
b87fb8cd RH |
376 | #define tcg_gen_smin_tl tcg_gen_smin_i32 |
377 | #define tcg_gen_umin_tl tcg_gen_umin_i32 | |
378 | #define tcg_gen_smax_tl tcg_gen_smax_i32 | |
379 | #define tcg_gen_umax_tl tcg_gen_umax_i32 | |
c482cb11 RH |
380 | #define tcg_gen_atomic_cmpxchg_tl tcg_gen_atomic_cmpxchg_i32 |
381 | #define tcg_gen_atomic_xchg_tl tcg_gen_atomic_xchg_i32 | |
382 | #define tcg_gen_atomic_fetch_add_tl tcg_gen_atomic_fetch_add_i32 | |
383 | #define tcg_gen_atomic_fetch_and_tl tcg_gen_atomic_fetch_and_i32 | |
384 | #define tcg_gen_atomic_fetch_or_tl tcg_gen_atomic_fetch_or_i32 | |
385 | #define tcg_gen_atomic_fetch_xor_tl tcg_gen_atomic_fetch_xor_i32 | |
5507c2bf RH |
386 | #define tcg_gen_atomic_fetch_smin_tl tcg_gen_atomic_fetch_smin_i32 |
387 | #define tcg_gen_atomic_fetch_umin_tl tcg_gen_atomic_fetch_umin_i32 | |
388 | #define tcg_gen_atomic_fetch_smax_tl tcg_gen_atomic_fetch_smax_i32 | |
389 | #define tcg_gen_atomic_fetch_umax_tl tcg_gen_atomic_fetch_umax_i32 | |
c482cb11 RH |
390 | #define tcg_gen_atomic_add_fetch_tl tcg_gen_atomic_add_fetch_i32 |
391 | #define tcg_gen_atomic_and_fetch_tl tcg_gen_atomic_and_fetch_i32 | |
392 | #define tcg_gen_atomic_or_fetch_tl tcg_gen_atomic_or_fetch_i32 | |
393 | #define tcg_gen_atomic_xor_fetch_tl tcg_gen_atomic_xor_fetch_i32 | |
5507c2bf RH |
394 | #define tcg_gen_atomic_smin_fetch_tl tcg_gen_atomic_smin_fetch_i32 |
395 | #define tcg_gen_atomic_umin_fetch_tl tcg_gen_atomic_umin_fetch_i32 | |
396 | #define tcg_gen_atomic_smax_fetch_tl tcg_gen_atomic_smax_fetch_i32 | |
397 | #define tcg_gen_atomic_umax_fetch_tl tcg_gen_atomic_umax_fetch_i32 | |
d2fd745f | 398 | #define tcg_gen_dup_tl_vec tcg_gen_dup_i32_vec |
614dd4f3 | 399 | #define tcg_gen_dup_tl tcg_gen_dup_i32 |
f15f8935 RH |
400 | |
401 | #define dup_const_tl(VECE, C) \ | |
402 | (__builtin_constant_p(VECE) \ | |
403 | ? ( (VECE) == MO_8 ? 0x01010101ul * (uint8_t)(C) \ | |
404 | : (VECE) == MO_16 ? 0x00010001ul * (uint16_t)(C) \ | |
405 | : (VECE) == MO_32 ? 0x00000001ul * (uint32_t)(C) \ | |
406 | : (qemu_build_not_reached_always(), 0)) \ | |
407 | : (target_long)dup_const(VECE, C)) | |
a7ce790a | 408 | |
ad3d0e4d | 409 | #endif /* TARGET_LONG_BITS == 64 */ |
a7ce790a | 410 | #endif /* TCG_TCG_OP_H */ |