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c896fe29
FB		 1/*
2 * Tiny Code Generator for QEMU
3 *
4 * Copyright (c) 2008 Fabrice Bellard
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
22 * THE SOFTWARE.
23 */
951c6300 24
a7ce790a
PM		 25#ifndef TCG_TCG_OP_H
26#define TCG_TCG_OP_H
27
dcb32f1d 28#include "tcg/tcg.h"
944eea96 29#include "exec/helper-proto.h"
c017230d
RH		 30#include "exec/helper-gen.h"
31
951c6300 32/* Basic output routines. Not for general consumption. */
c896fe29 33
b7e8b17a
RH		 34void tcg_gen_op1(TCGOpcode, TCGArg);
35void tcg_gen_op2(TCGOpcode, TCGArg, TCGArg);
36void tcg_gen_op3(TCGOpcode, TCGArg, TCGArg, TCGArg);
37void tcg_gen_op4(TCGOpcode, TCGArg, TCGArg, TCGArg, TCGArg);
38void tcg_gen_op5(TCGOpcode, TCGArg, TCGArg, TCGArg, TCGArg, TCGArg);
39void tcg_gen_op6(TCGOpcode, TCGArg, TCGArg, TCGArg, TCGArg, TCGArg, TCGArg);
951c6300 40
d2fd745f
RH		 41void vec_gen_2(TCGOpcode, TCGType, unsigned, TCGArg, TCGArg);
42void vec_gen_3(TCGOpcode, TCGType, unsigned, TCGArg, TCGArg, TCGArg);
43void vec_gen_4(TCGOpcode, TCGType, unsigned, TCGArg, TCGArg, TCGArg, TCGArg);
44
951c6300 45static inline void tcg_gen_op1_i32(TCGOpcode opc, TCGv_i32 a1)
c896fe29 46{
ae8b75dc 47 tcg_gen_op1(opc, tcgv_i32_arg(a1));
a7812ae4
PB		 48}
49
951c6300 50static inline void tcg_gen_op1_i64(TCGOpcode opc, TCGv_i64 a1)
a7812ae4 51{
ae8b75dc 52 tcg_gen_op1(opc, tcgv_i64_arg(a1));
c896fe29
FB		 53}
54
951c6300 55static inline void tcg_gen_op1i(TCGOpcode opc, TCGArg a1)
c896fe29 56{
b7e8b17a 57 tcg_gen_op1(opc, a1);
c896fe29
FB		 58}
59
951c6300 60static inline void tcg_gen_op2_i32(TCGOpcode opc, TCGv_i32 a1, TCGv_i32 a2)
a7812ae4 61{
ae8b75dc 62 tcg_gen_op2(opc, tcgv_i32_arg(a1), tcgv_i32_arg(a2));
a7812ae4
PB		 63}
64
951c6300 65static inline void tcg_gen_op2_i64(TCGOpcode opc, TCGv_i64 a1, TCGv_i64 a2)
a7812ae4 66{
ae8b75dc 67 tcg_gen_op2(opc, tcgv_i64_arg(a1), tcgv_i64_arg(a2));
a7812ae4
PB		 68}
69
951c6300 70static inline void tcg_gen_op2i_i32(TCGOpcode opc, TCGv_i32 a1, TCGArg a2)
c896fe29 71{
ae8b75dc 72 tcg_gen_op2(opc, tcgv_i32_arg(a1), a2);
c896fe29
FB		 73}
74
951c6300 75static inline void tcg_gen_op2i_i64(TCGOpcode opc, TCGv_i64 a1, TCGArg a2)
c896fe29 76{
ae8b75dc 77 tcg_gen_op2(opc, tcgv_i64_arg(a1), a2);
ac56dd48
PB		 78}
79
951c6300 80static inline void tcg_gen_op2ii(TCGOpcode opc, TCGArg a1, TCGArg a2)
bcb0126f 81{
b7e8b17a 82 tcg_gen_op2(opc, a1, a2);
bcb0126f
PB		 83}
84
951c6300
RH		 85static inline void tcg_gen_op3_i32(TCGOpcode opc, TCGv_i32 a1,
86 TCGv_i32 a2, TCGv_i32 a3)
a7812ae4 87{
ae8b75dc 88 tcg_gen_op3(opc, tcgv_i32_arg(a1), tcgv_i32_arg(a2), tcgv_i32_arg(a3));
a7812ae4
PB		 89}
90
951c6300
RH		 91static inline void tcg_gen_op3_i64(TCGOpcode opc, TCGv_i64 a1,
92 TCGv_i64 a2, TCGv_i64 a3)
a7812ae4 93{
ae8b75dc 94 tcg_gen_op3(opc, tcgv_i64_arg(a1), tcgv_i64_arg(a2), tcgv_i64_arg(a3));
a7812ae4
PB		 95}
96
951c6300
RH		 97static inline void tcg_gen_op3i_i32(TCGOpcode opc, TCGv_i32 a1,
98 TCGv_i32 a2, TCGArg a3)
ac56dd48 99{
ae8b75dc 100 tcg_gen_op3(opc, tcgv_i32_arg(a1), tcgv_i32_arg(a2), a3);
ac56dd48
PB		 101}
102
951c6300
RH		 103static inline void tcg_gen_op3i_i64(TCGOpcode opc, TCGv_i64 a1,
104 TCGv_i64 a2, TCGArg a3)
ac56dd48 105{
ae8b75dc 106 tcg_gen_op3(opc, tcgv_i64_arg(a1), tcgv_i64_arg(a2), a3);
ac56dd48
PB		 107}
108
a9751609
RH		 109static inline void tcg_gen_ldst_op_i32(TCGOpcode opc, TCGv_i32 val,
110 TCGv_ptr base, TCGArg offset)
a7812ae4 111{
ae8b75dc 112 tcg_gen_op3(opc, tcgv_i32_arg(val), tcgv_ptr_arg(base), offset);
a7812ae4
PB		 113}
114
a9751609
RH		 115static inline void tcg_gen_ldst_op_i64(TCGOpcode opc, TCGv_i64 val,
116 TCGv_ptr base, TCGArg offset)
a7812ae4 117{
ae8b75dc 118 tcg_gen_op3(opc, tcgv_i64_arg(val), tcgv_ptr_arg(base), offset);
a7812ae4
PB		 119}
120
951c6300
RH		 121static inline void tcg_gen_op4_i32(TCGOpcode opc, TCGv_i32 a1, TCGv_i32 a2,
122 TCGv_i32 a3, TCGv_i32 a4)
a7812ae4 123{
ae8b75dc
RH		 124 tcg_gen_op4(opc, tcgv_i32_arg(a1), tcgv_i32_arg(a2),
125 tcgv_i32_arg(a3), tcgv_i32_arg(a4));
a7812ae4
PB		 126}
127
951c6300
RH		 128static inline void tcg_gen_op4_i64(TCGOpcode opc, TCGv_i64 a1, TCGv_i64 a2,
129 TCGv_i64 a3, TCGv_i64 a4)
a7812ae4 130{
ae8b75dc
RH		 131 tcg_gen_op4(opc, tcgv_i64_arg(a1), tcgv_i64_arg(a2),
132 tcgv_i64_arg(a3), tcgv_i64_arg(a4));
a7812ae4
PB		 133}
134
951c6300
RH		 135static inline void tcg_gen_op4i_i32(TCGOpcode opc, TCGv_i32 a1, TCGv_i32 a2,
136 TCGv_i32 a3, TCGArg a4)
a7812ae4 137{
ae8b75dc
RH		 138 tcg_gen_op4(opc, tcgv_i32_arg(a1), tcgv_i32_arg(a2),
139 tcgv_i32_arg(a3), a4);
a7812ae4
PB		 140}
141
951c6300
RH		 142static inline void tcg_gen_op4i_i64(TCGOpcode opc, TCGv_i64 a1, TCGv_i64 a2,
143 TCGv_i64 a3, TCGArg a4)
ac56dd48 144{
ae8b75dc
RH		 145 tcg_gen_op4(opc, tcgv_i64_arg(a1), tcgv_i64_arg(a2),
146 tcgv_i64_arg(a3), a4);
ac56dd48
PB		 147}
148
951c6300
RH		 149static inline void tcg_gen_op4ii_i32(TCGOpcode opc, TCGv_i32 a1, TCGv_i32 a2,
150 TCGArg a3, TCGArg a4)
ac56dd48 151{
ae8b75dc 152 tcg_gen_op4(opc, tcgv_i32_arg(a1), tcgv_i32_arg(a2), a3, a4);
c896fe29
FB		 153}
154
951c6300
RH		 155static inline void tcg_gen_op4ii_i64(TCGOpcode opc, TCGv_i64 a1, TCGv_i64 a2,
156 TCGArg a3, TCGArg a4)
c896fe29 157{
ae8b75dc 158 tcg_gen_op4(opc, tcgv_i64_arg(a1), tcgv_i64_arg(a2), a3, a4);
ac56dd48
PB		 159}
160
951c6300
RH		 161static inline void tcg_gen_op5_i32(TCGOpcode opc, TCGv_i32 a1, TCGv_i32 a2,
162 TCGv_i32 a3, TCGv_i32 a4, TCGv_i32 a5)
a7812ae4 163{
ae8b75dc
RH		 164 tcg_gen_op5(opc, tcgv_i32_arg(a1), tcgv_i32_arg(a2),
165 tcgv_i32_arg(a3), tcgv_i32_arg(a4), tcgv_i32_arg(a5));
a7812ae4
PB		 166}
167
951c6300
RH		 168static inline void tcg_gen_op5_i64(TCGOpcode opc, TCGv_i64 a1, TCGv_i64 a2,
169 TCGv_i64 a3, TCGv_i64 a4, TCGv_i64 a5)
a7812ae4 170{
ae8b75dc
RH		 171 tcg_gen_op5(opc, tcgv_i64_arg(a1), tcgv_i64_arg(a2),
172 tcgv_i64_arg(a3), tcgv_i64_arg(a4), tcgv_i64_arg(a5));
a7812ae4
PB		 173}
174
951c6300
RH		 175static inline void tcg_gen_op5i_i32(TCGOpcode opc, TCGv_i32 a1, TCGv_i32 a2,
176 TCGv_i32 a3, TCGv_i32 a4, TCGArg a5)
ac56dd48 177{
ae8b75dc
RH		 178 tcg_gen_op5(opc, tcgv_i32_arg(a1), tcgv_i32_arg(a2),
179 tcgv_i32_arg(a3), tcgv_i32_arg(a4), a5);
ac56dd48
PB		 180}
181
951c6300
RH		 182static inline void tcg_gen_op5i_i64(TCGOpcode opc, TCGv_i64 a1, TCGv_i64 a2,
183 TCGv_i64 a3, TCGv_i64 a4, TCGArg a5)
ac56dd48 184{
ae8b75dc
RH		 185 tcg_gen_op5(opc, tcgv_i64_arg(a1), tcgv_i64_arg(a2),
186 tcgv_i64_arg(a3), tcgv_i64_arg(a4), a5);
c896fe29
FB		 187}
188
951c6300
RH		 189static inline void tcg_gen_op5ii_i32(TCGOpcode opc, TCGv_i32 a1, TCGv_i32 a2,
190 TCGv_i32 a3, TCGArg a4, TCGArg a5)
b7767f0f 191{
ae8b75dc
RH		 192 tcg_gen_op5(opc, tcgv_i32_arg(a1), tcgv_i32_arg(a2),
193 tcgv_i32_arg(a3), a4, a5);
b7767f0f
RH		 194}
195
951c6300
RH		 196static inline void tcg_gen_op5ii_i64(TCGOpcode opc, TCGv_i64 a1, TCGv_i64 a2,
197 TCGv_i64 a3, TCGArg a4, TCGArg a5)
b7767f0f 198{
ae8b75dc
RH		 199 tcg_gen_op5(opc, tcgv_i64_arg(a1), tcgv_i64_arg(a2),
200 tcgv_i64_arg(a3), a4, a5);
b7767f0f
RH		 201}
202
951c6300
RH		 203static inline void tcg_gen_op6_i32(TCGOpcode opc, TCGv_i32 a1, TCGv_i32 a2,
204 TCGv_i32 a3, TCGv_i32 a4,
205 TCGv_i32 a5, TCGv_i32 a6)
a7812ae4 206{
ae8b75dc
RH		 207 tcg_gen_op6(opc, tcgv_i32_arg(a1), tcgv_i32_arg(a2),
208 tcgv_i32_arg(a3), tcgv_i32_arg(a4), tcgv_i32_arg(a5),
209 tcgv_i32_arg(a6));
a7812ae4
PB		 210}
211
951c6300
RH		 212static inline void tcg_gen_op6_i64(TCGOpcode opc, TCGv_i64 a1, TCGv_i64 a2,
213 TCGv_i64 a3, TCGv_i64 a4,
214 TCGv_i64 a5, TCGv_i64 a6)
c896fe29 215{
ae8b75dc
RH		 216 tcg_gen_op6(opc, tcgv_i64_arg(a1), tcgv_i64_arg(a2),
217 tcgv_i64_arg(a3), tcgv_i64_arg(a4), tcgv_i64_arg(a5),
218 tcgv_i64_arg(a6));
ac56dd48
PB		 219}
220
951c6300
RH		 221static inline void tcg_gen_op6i_i32(TCGOpcode opc, TCGv_i32 a1, TCGv_i32 a2,
222 TCGv_i32 a3, TCGv_i32 a4,
223 TCGv_i32 a5, TCGArg a6)
be210acb 224{
ae8b75dc
RH		 225 tcg_gen_op6(opc, tcgv_i32_arg(a1), tcgv_i32_arg(a2),
226 tcgv_i32_arg(a3), tcgv_i32_arg(a4), tcgv_i32_arg(a5), a6);
be210acb
RH		 227}
228
951c6300
RH		 229static inline void tcg_gen_op6i_i64(TCGOpcode opc, TCGv_i64 a1, TCGv_i64 a2,
230 TCGv_i64 a3, TCGv_i64 a4,
231 TCGv_i64 a5, TCGArg a6)
be210acb 232{
ae8b75dc
RH		 233 tcg_gen_op6(opc, tcgv_i64_arg(a1), tcgv_i64_arg(a2),
234 tcgv_i64_arg(a3), tcgv_i64_arg(a4), tcgv_i64_arg(a5), a6);
be210acb
RH		 235}
236
951c6300
RH		 237static inline void tcg_gen_op6ii_i32(TCGOpcode opc, TCGv_i32 a1, TCGv_i32 a2,
238 TCGv_i32 a3, TCGv_i32 a4,
239 TCGArg a5, TCGArg a6)
ac56dd48 240{
ae8b75dc
RH		 241 tcg_gen_op6(opc, tcgv_i32_arg(a1), tcgv_i32_arg(a2),
242 tcgv_i32_arg(a3), tcgv_i32_arg(a4), a5, a6);
a7812ae4
PB		 243}
244
951c6300
RH		 245static inline void tcg_gen_op6ii_i64(TCGOpcode opc, TCGv_i64 a1, TCGv_i64 a2,
246 TCGv_i64 a3, TCGv_i64 a4,
247 TCGArg a5, TCGArg a6)
a7812ae4 248{
ae8b75dc
RH		 249 tcg_gen_op6(opc, tcgv_i64_arg(a1), tcgv_i64_arg(a2),
250 tcgv_i64_arg(a3), tcgv_i64_arg(a4), a5, a6);
c896fe29
FB		 251}
252
f713d6ad 253
951c6300
RH		 254/* Generic ops. */
255
42a268c2 256static inline void gen_set_label(TCGLabel *l)
c896fe29 257{
bef16ab4 258 l->present = 1;
b7e8b17a 259 tcg_gen_op1(INDEX_op_set_label, label_arg(l));
c896fe29
FB		 260}
261
f85b1fc4 262void tcg_gen_br(TCGLabel *l);
f65e19bc
PK		 263void tcg_gen_mb(TCGBar);
264
951c6300
RH		 265/* Helper calls. */
266
267/* 32 bit ops */
268
11d11d61 269void tcg_gen_movi_i32(TCGv_i32 ret, int32_t arg);
951c6300
RH		 270void tcg_gen_addi_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2);
271void tcg_gen_subfi_i32(TCGv_i32 ret, int32_t arg1, TCGv_i32 arg2);
272void tcg_gen_subi_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2);
474b2e8f 273void tcg_gen_andi_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2);
951c6300
RH		 274void tcg_gen_ori_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2);
275void tcg_gen_xori_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2);
474b2e8f
RH		 276void tcg_gen_shli_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2);
277void tcg_gen_shri_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2);
278void tcg_gen_sari_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2);
951c6300
RH		 279void tcg_gen_muli_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2);
280void tcg_gen_div_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2);
281void tcg_gen_rem_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2);
282void tcg_gen_divu_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2);
283void tcg_gen_remu_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2);
284void tcg_gen_andc_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2);
285void tcg_gen_eqv_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2);
286void tcg_gen_nand_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2);
287void tcg_gen_nor_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2);
288void tcg_gen_orc_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2);
0e28d006
RH		 289void tcg_gen_clz_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2);
290void tcg_gen_ctz_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2);
291void tcg_gen_clzi_i32(TCGv_i32 ret, TCGv_i32 arg1, uint32_t arg2);
292void tcg_gen_ctzi_i32(TCGv_i32 ret, TCGv_i32 arg1, uint32_t arg2);
086920c2 293void tcg_gen_clrsb_i32(TCGv_i32 ret, TCGv_i32 arg);
a768e4e9 294void tcg_gen_ctpop_i32(TCGv_i32 a1, TCGv_i32 a2);
951c6300 295void tcg_gen_rotl_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2);
07dada03 296void tcg_gen_rotli_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2);
951c6300 297void tcg_gen_rotr_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2);
07dada03 298void tcg_gen_rotri_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2);
951c6300
RH		 299void tcg_gen_deposit_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2,
300 unsigned int ofs, unsigned int len);
07cc68d5
RH		 301void tcg_gen_deposit_z_i32(TCGv_i32 ret, TCGv_i32 arg,
302 unsigned int ofs, unsigned int len);
7ec8bab3
RH		 303void tcg_gen_extract_i32(TCGv_i32 ret, TCGv_i32 arg,
304 unsigned int ofs, unsigned int len);
305void tcg_gen_sextract_i32(TCGv_i32 ret, TCGv_i32 arg,
306 unsigned int ofs, unsigned int len);
2089fcc9
DH		 307void tcg_gen_extract2_i32(TCGv_i32 ret, TCGv_i32 al, TCGv_i32 ah,
308 unsigned int ofs);
42a268c2
RH		 309void tcg_gen_brcond_i32(TCGCond cond, TCGv_i32 arg1, TCGv_i32 arg2, TCGLabel *);
310void tcg_gen_brcondi_i32(TCGCond cond, TCGv_i32 arg1, int32_t arg2, TCGLabel *);
951c6300
RH		 311void tcg_gen_setcond_i32(TCGCond cond, TCGv_i32 ret,
312 TCGv_i32 arg1, TCGv_i32 arg2);
313void tcg_gen_setcondi_i32(TCGCond cond, TCGv_i32 ret,
314 TCGv_i32 arg1, int32_t arg2);
315void tcg_gen_movcond_i32(TCGCond cond, TCGv_i32 ret, TCGv_i32 c1,
316 TCGv_i32 c2, TCGv_i32 v1, TCGv_i32 v2);
317void tcg_gen_add2_i32(TCGv_i32 rl, TCGv_i32 rh, TCGv_i32 al,
318 TCGv_i32 ah, TCGv_i32 bl, TCGv_i32 bh);
319void tcg_gen_sub2_i32(TCGv_i32 rl, TCGv_i32 rh, TCGv_i32 al,
320 TCGv_i32 ah, TCGv_i32 bl, TCGv_i32 bh);
321void tcg_gen_mulu2_i32(TCGv_i32 rl, TCGv_i32 rh, TCGv_i32 arg1, TCGv_i32 arg2);
322void tcg_gen_muls2_i32(TCGv_i32 rl, TCGv_i32 rh, TCGv_i32 arg1, TCGv_i32 arg2);
5087abfb 323void tcg_gen_mulsu2_i32(TCGv_i32 rl, TCGv_i32 rh, TCGv_i32 arg1, TCGv_i32 arg2);
951c6300
RH		 324void tcg_gen_ext8s_i32(TCGv_i32 ret, TCGv_i32 arg);
325void tcg_gen_ext16s_i32(TCGv_i32 ret, TCGv_i32 arg);
326void tcg_gen_ext8u_i32(TCGv_i32 ret, TCGv_i32 arg);
327void tcg_gen_ext16u_i32(TCGv_i32 ret, TCGv_i32 arg);
2b836c2a 328void tcg_gen_bswap16_i32(TCGv_i32 ret, TCGv_i32 arg, int flags);
951c6300 329void tcg_gen_bswap32_i32(TCGv_i32 ret, TCGv_i32 arg);
46be8425 330void tcg_gen_hswap_i32(TCGv_i32 ret, TCGv_i32 arg);
b87fb8cd
RH		 331void tcg_gen_smin_i32(TCGv_i32, TCGv_i32 arg1, TCGv_i32 arg2);
332void tcg_gen_smax_i32(TCGv_i32, TCGv_i32 arg1, TCGv_i32 arg2);
333void tcg_gen_umin_i32(TCGv_i32, TCGv_i32 arg1, TCGv_i32 arg2);
334void tcg_gen_umax_i32(TCGv_i32, TCGv_i32 arg1, TCGv_i32 arg2);
ff1f11f7 335void tcg_gen_abs_i32(TCGv_i32, TCGv_i32);
951c6300 336
614dd4f3
PM		 337/* Replicate a value of size @vece from @in to all the lanes in @out */
338void tcg_gen_dup_i32(unsigned vece, TCGv_i32 out, TCGv_i32 in);
339
951c6300
RH		 340static inline void tcg_gen_discard_i32(TCGv_i32 arg)
341{
342 tcg_gen_op1_i32(INDEX_op_discard, arg);
fb50d413
BS		 343}
344
a7812ae4 345static inline void tcg_gen_mov_i32(TCGv_i32 ret, TCGv_i32 arg)
c896fe29 346{
11f4e8f8 347 if (ret != arg) {
a7812ae4 348 tcg_gen_op2_i32(INDEX_op_mov_i32, ret, arg);
951c6300 349 }
c896fe29
FB		 350}
351
951c6300
RH		 352static inline void tcg_gen_ld8u_i32(TCGv_i32 ret, TCGv_ptr arg2,
353 tcg_target_long offset)
c896fe29 354{
a7812ae4 355 tcg_gen_ldst_op_i32(INDEX_op_ld8u_i32, ret, arg2, offset);
c896fe29
FB		 356}
357
951c6300
RH		 358static inline void tcg_gen_ld8s_i32(TCGv_i32 ret, TCGv_ptr arg2,
359 tcg_target_long offset)
c896fe29 360{
a7812ae4 361 tcg_gen_ldst_op_i32(INDEX_op_ld8s_i32, ret, arg2, offset);
c896fe29
FB		 362}
363
951c6300
RH		 364static inline void tcg_gen_ld16u_i32(TCGv_i32 ret, TCGv_ptr arg2,
365 tcg_target_long offset)
c896fe29 366{
a7812ae4 367 tcg_gen_ldst_op_i32(INDEX_op_ld16u_i32, ret, arg2, offset);
c896fe29
FB		 368}
369
951c6300
RH		 370static inline void tcg_gen_ld16s_i32(TCGv_i32 ret, TCGv_ptr arg2,
371 tcg_target_long offset)
c896fe29 372{
a7812ae4 373 tcg_gen_ldst_op_i32(INDEX_op_ld16s_i32, ret, arg2, offset);
c896fe29
FB		 374}
375
951c6300
RH		 376static inline void tcg_gen_ld_i32(TCGv_i32 ret, TCGv_ptr arg2,
377 tcg_target_long offset)
c896fe29 378{
a7812ae4 379 tcg_gen_ldst_op_i32(INDEX_op_ld_i32, ret, arg2, offset);
c896fe29
FB		 380}
381
951c6300
RH		 382static inline void tcg_gen_st8_i32(TCGv_i32 arg1, TCGv_ptr arg2,
383 tcg_target_long offset)
c896fe29 384{
a7812ae4 385 tcg_gen_ldst_op_i32(INDEX_op_st8_i32, arg1, arg2, offset);
c896fe29
FB		 386}
387
951c6300
RH		 388static inline void tcg_gen_st16_i32(TCGv_i32 arg1, TCGv_ptr arg2,
389 tcg_target_long offset)
c896fe29 390{
a7812ae4 391 tcg_gen_ldst_op_i32(INDEX_op_st16_i32, arg1, arg2, offset);
c896fe29
FB		 392}
393
951c6300
RH		 394static inline void tcg_gen_st_i32(TCGv_i32 arg1, TCGv_ptr arg2,
395 tcg_target_long offset)
c896fe29 396{
a7812ae4 397 tcg_gen_ldst_op_i32(INDEX_op_st_i32, arg1, arg2, offset);
c896fe29
FB		 398}
399
a7812ae4 400static inline void tcg_gen_add_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
c896fe29 401{
a7812ae4 402 tcg_gen_op3_i32(INDEX_op_add_i32, ret, arg1, arg2);
c896fe29
FB		 403}
404
a7812ae4 405static inline void tcg_gen_sub_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
c896fe29 406{
a7812ae4 407 tcg_gen_op3_i32(INDEX_op_sub_i32, ret, arg1, arg2);
c896fe29
FB		 408}
409
a7812ae4 410static inline void tcg_gen_and_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
c896fe29 411{
951c6300 412 tcg_gen_op3_i32(INDEX_op_and_i32, ret, arg1, arg2);
c896fe29
FB		 413}
414
a7812ae4 415static inline void tcg_gen_or_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
c896fe29 416{
951c6300 417 tcg_gen_op3_i32(INDEX_op_or_i32, ret, arg1, arg2);
c896fe29
FB		 418}
419
a7812ae4 420static inline void tcg_gen_xor_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
c896fe29 421{
951c6300 422 tcg_gen_op3_i32(INDEX_op_xor_i32, ret, arg1, arg2);
c896fe29
FB		 423}
424
a7812ae4 425static inline void tcg_gen_shl_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
c896fe29 426{
a7812ae4 427 tcg_gen_op3_i32(INDEX_op_shl_i32, ret, arg1, arg2);
c896fe29
FB		 428}
429
a7812ae4 430static inline void tcg_gen_shr_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
c896fe29 431{
a7812ae4 432 tcg_gen_op3_i32(INDEX_op_shr_i32, ret, arg1, arg2);
c896fe29
FB		 433}
434
a7812ae4 435static inline void tcg_gen_sar_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
c896fe29 436{
a7812ae4 437 tcg_gen_op3_i32(INDEX_op_sar_i32, ret, arg1, arg2);
c896fe29
FB		 438}
439
a7812ae4 440static inline void tcg_gen_mul_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
c896fe29 441{
a7812ae4 442 tcg_gen_op3_i32(INDEX_op_mul_i32, ret, arg1, arg2);
c896fe29
FB		 443}
444
951c6300 445static inline void tcg_gen_neg_i32(TCGv_i32 ret, TCGv_i32 arg)
c896fe29 446{
951c6300
RH		 447 if (TCG_TARGET_HAS_neg_i32) {
448 tcg_gen_op2_i32(INDEX_op_neg_i32, ret, arg);
25c4d9cc 449 } else {
951c6300 450 tcg_gen_subfi_i32(ret, 0, arg);
25c4d9cc 451 }
31d66551
AJ		 452}
453
951c6300 454static inline void tcg_gen_not_i32(TCGv_i32 ret, TCGv_i32 arg)
31d66551 455{
951c6300
RH		 456 if (TCG_TARGET_HAS_not_i32) {
457 tcg_gen_op2_i32(INDEX_op_not_i32, ret, arg);
25c4d9cc 458 } else {
951c6300 459 tcg_gen_xori_i32(ret, arg, -1);
25c4d9cc 460 }
31d66551
AJ		 461}
462
951c6300
RH		 463/* 64 bit ops */
464
11d11d61 465void tcg_gen_movi_i64(TCGv_i64 ret, int64_t arg);
951c6300
RH		 466void tcg_gen_addi_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2);
467void tcg_gen_subfi_i64(TCGv_i64 ret, int64_t arg1, TCGv_i64 arg2);
468void tcg_gen_subi_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2);
474b2e8f 469void tcg_gen_andi_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2);
951c6300
RH		 470void tcg_gen_ori_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2);
471void tcg_gen_xori_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2);
474b2e8f
RH		 472void tcg_gen_shli_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2);
473void tcg_gen_shri_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2);
474void tcg_gen_sari_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2);
951c6300
RH		 475void tcg_gen_muli_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2);
476void tcg_gen_div_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2);
477void tcg_gen_rem_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2);
478void tcg_gen_divu_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2);
479void tcg_gen_remu_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2);
480void tcg_gen_andc_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2);
481void tcg_gen_eqv_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2);
482void tcg_gen_nand_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2);
483void tcg_gen_nor_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2);
484void tcg_gen_orc_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2);
0e28d006
RH		 485void tcg_gen_clz_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2);
486void tcg_gen_ctz_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2);
487void tcg_gen_clzi_i64(TCGv_i64 ret, TCGv_i64 arg1, uint64_t arg2);
488void tcg_gen_ctzi_i64(TCGv_i64 ret, TCGv_i64 arg1, uint64_t arg2);
086920c2 489void tcg_gen_clrsb_i64(TCGv_i64 ret, TCGv_i64 arg);
a768e4e9 490void tcg_gen_ctpop_i64(TCGv_i64 a1, TCGv_i64 a2);
951c6300 491void tcg_gen_rotl_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2);
07dada03 492void tcg_gen_rotli_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2);
951c6300 493void tcg_gen_rotr_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2);
07dada03 494void tcg_gen_rotri_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2);
951c6300
RH		 495void tcg_gen_deposit_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2,
496 unsigned int ofs, unsigned int len);
07cc68d5
RH		 497void tcg_gen_deposit_z_i64(TCGv_i64 ret, TCGv_i64 arg,
498 unsigned int ofs, unsigned int len);
7ec8bab3
RH		 499void tcg_gen_extract_i64(TCGv_i64 ret, TCGv_i64 arg,
500 unsigned int ofs, unsigned int len);
501void tcg_gen_sextract_i64(TCGv_i64 ret, TCGv_i64 arg,
502 unsigned int ofs, unsigned int len);
2089fcc9
DH		 503void tcg_gen_extract2_i64(TCGv_i64 ret, TCGv_i64 al, TCGv_i64 ah,
504 unsigned int ofs);
42a268c2
RH		 505void tcg_gen_brcond_i64(TCGCond cond, TCGv_i64 arg1, TCGv_i64 arg2, TCGLabel *);
506void tcg_gen_brcondi_i64(TCGCond cond, TCGv_i64 arg1, int64_t arg2, TCGLabel *);
951c6300
RH		 507void tcg_gen_setcond_i64(TCGCond cond, TCGv_i64 ret,
508 TCGv_i64 arg1, TCGv_i64 arg2);
509void tcg_gen_setcondi_i64(TCGCond cond, TCGv_i64 ret,
510 TCGv_i64 arg1, int64_t arg2);
511void tcg_gen_movcond_i64(TCGCond cond, TCGv_i64 ret, TCGv_i64 c1,
512 TCGv_i64 c2, TCGv_i64 v1, TCGv_i64 v2);
513void tcg_gen_add2_i64(TCGv_i64 rl, TCGv_i64 rh, TCGv_i64 al,
514 TCGv_i64 ah, TCGv_i64 bl, TCGv_i64 bh);
515void tcg_gen_sub2_i64(TCGv_i64 rl, TCGv_i64 rh, TCGv_i64 al,
516 TCGv_i64 ah, TCGv_i64 bl, TCGv_i64 bh);
517void tcg_gen_mulu2_i64(TCGv_i64 rl, TCGv_i64 rh, TCGv_i64 arg1, TCGv_i64 arg2);
518void tcg_gen_muls2_i64(TCGv_i64 rl, TCGv_i64 rh, TCGv_i64 arg1, TCGv_i64 arg2);
5087abfb 519void tcg_gen_mulsu2_i64(TCGv_i64 rl, TCGv_i64 rh, TCGv_i64 arg1, TCGv_i64 arg2);
951c6300
RH		 520void tcg_gen_not_i64(TCGv_i64 ret, TCGv_i64 arg);
521void tcg_gen_ext8s_i64(TCGv_i64 ret, TCGv_i64 arg);
522void tcg_gen_ext16s_i64(TCGv_i64 ret, TCGv_i64 arg);
523void tcg_gen_ext32s_i64(TCGv_i64 ret, TCGv_i64 arg);
524void tcg_gen_ext8u_i64(TCGv_i64 ret, TCGv_i64 arg);
525void tcg_gen_ext16u_i64(TCGv_i64 ret, TCGv_i64 arg);
526void tcg_gen_ext32u_i64(TCGv_i64 ret, TCGv_i64 arg);
2b836c2a
RH		 527void tcg_gen_bswap16_i64(TCGv_i64 ret, TCGv_i64 arg, int flags);
528void tcg_gen_bswap32_i64(TCGv_i64 ret, TCGv_i64 arg, int flags);
951c6300 529void tcg_gen_bswap64_i64(TCGv_i64 ret, TCGv_i64 arg);
46be8425
RH		 530void tcg_gen_hswap_i64(TCGv_i64 ret, TCGv_i64 arg);
531void tcg_gen_wswap_i64(TCGv_i64 ret, TCGv_i64 arg);
b87fb8cd
RH		 532void tcg_gen_smin_i64(TCGv_i64, TCGv_i64 arg1, TCGv_i64 arg2);
533void tcg_gen_smax_i64(TCGv_i64, TCGv_i64 arg1, TCGv_i64 arg2);
534void tcg_gen_umin_i64(TCGv_i64, TCGv_i64 arg1, TCGv_i64 arg2);
535void tcg_gen_umax_i64(TCGv_i64, TCGv_i64 arg1, TCGv_i64 arg2);
ff1f11f7 536void tcg_gen_abs_i64(TCGv_i64, TCGv_i64);
c896fe29 537
614dd4f3
PM		 538/* Replicate a value of size @vece from @in to all the lanes in @out */
539void tcg_gen_dup_i64(unsigned vece, TCGv_i64 out, TCGv_i64 in);
540
951c6300
RH		 541#if TCG_TARGET_REG_BITS == 64
542static inline void tcg_gen_discard_i64(TCGv_i64 arg)
543{
544 tcg_gen_op1_i64(INDEX_op_discard, arg);
545}
c896fe29 546
a7812ae4 547static inline void tcg_gen_mov_i64(TCGv_i64 ret, TCGv_i64 arg)
c896fe29 548{
11f4e8f8 549 if (ret != arg) {
951c6300 550 tcg_gen_op2_i64(INDEX_op_mov_i64, ret, arg);
4d07272d 551 }
c896fe29
FB		 552}
553
a7812ae4
PB		 554static inline void tcg_gen_ld8u_i64(TCGv_i64 ret, TCGv_ptr arg2,
555 tcg_target_long offset)
c896fe29 556{
951c6300 557 tcg_gen_ldst_op_i64(INDEX_op_ld8u_i64, ret, arg2, offset);
c896fe29
FB		 558}
559
a7812ae4
PB		 560static inline void tcg_gen_ld8s_i64(TCGv_i64 ret, TCGv_ptr arg2,
561 tcg_target_long offset)
c896fe29 562{
951c6300 563 tcg_gen_ldst_op_i64(INDEX_op_ld8s_i64, ret, arg2, offset);
c896fe29
FB		 564}
565
a7812ae4
PB		 566static inline void tcg_gen_ld16u_i64(TCGv_i64 ret, TCGv_ptr arg2,
567 tcg_target_long offset)
c896fe29 568{
951c6300 569 tcg_gen_ldst_op_i64(INDEX_op_ld16u_i64, ret, arg2, offset);
c896fe29
FB		 570}
571
a7812ae4
PB		 572static inline void tcg_gen_ld16s_i64(TCGv_i64 ret, TCGv_ptr arg2,
573 tcg_target_long offset)
c896fe29 574{
951c6300 575 tcg_gen_ldst_op_i64(INDEX_op_ld16s_i64, ret, arg2, offset);
c896fe29
FB		 576}
577
a7812ae4
PB		 578static inline void tcg_gen_ld32u_i64(TCGv_i64 ret, TCGv_ptr arg2,
579 tcg_target_long offset)
c896fe29 580{
951c6300 581 tcg_gen_ldst_op_i64(INDEX_op_ld32u_i64, ret, arg2, offset);
c896fe29
FB		 582}
583
a7812ae4
PB		 584static inline void tcg_gen_ld32s_i64(TCGv_i64 ret, TCGv_ptr arg2,
585 tcg_target_long offset)
c896fe29 586{
951c6300 587 tcg_gen_ldst_op_i64(INDEX_op_ld32s_i64, ret, arg2, offset);
c896fe29
FB		 588}
589
a7812ae4
PB		 590static inline void tcg_gen_ld_i64(TCGv_i64 ret, TCGv_ptr arg2,
591 tcg_target_long offset)
c896fe29 592{
951c6300 593 tcg_gen_ldst_op_i64(INDEX_op_ld_i64, ret, arg2, offset);
c896fe29
FB		 594}
595
a7812ae4
PB		 596static inline void tcg_gen_st8_i64(TCGv_i64 arg1, TCGv_ptr arg2,
597 tcg_target_long offset)
c896fe29 598{
951c6300 599 tcg_gen_ldst_op_i64(INDEX_op_st8_i64, arg1, arg2, offset);
c896fe29
FB		 600}
601
a7812ae4
PB		 602static inline void tcg_gen_st16_i64(TCGv_i64 arg1, TCGv_ptr arg2,
603 tcg_target_long offset)
c896fe29 604{
951c6300 605 tcg_gen_ldst_op_i64(INDEX_op_st16_i64, arg1, arg2, offset);
c896fe29
FB		 606}
607
a7812ae4
PB		 608static inline void tcg_gen_st32_i64(TCGv_i64 arg1, TCGv_ptr arg2,
609 tcg_target_long offset)
c896fe29 610{
951c6300 611 tcg_gen_ldst_op_i64(INDEX_op_st32_i64, arg1, arg2, offset);
c896fe29
FB		 612}
613
a7812ae4
PB		 614static inline void tcg_gen_st_i64(TCGv_i64 arg1, TCGv_ptr arg2,
615 tcg_target_long offset)
c896fe29 616{
951c6300 617 tcg_gen_ldst_op_i64(INDEX_op_st_i64, arg1, arg2, offset);
c896fe29
FB		 618}
619
a7812ae4 620static inline void tcg_gen_add_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
c896fe29 621{
951c6300 622 tcg_gen_op3_i64(INDEX_op_add_i64, ret, arg1, arg2);
c896fe29
FB		 623}
624
a7812ae4 625static inline void tcg_gen_sub_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
c896fe29 626{
951c6300 627 tcg_gen_op3_i64(INDEX_op_sub_i64, ret, arg1, arg2);
c896fe29
FB		 628}
629
a7812ae4 630static inline void tcg_gen_and_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
c896fe29 631{
951c6300 632 tcg_gen_op3_i64(INDEX_op_and_i64, ret, arg1, arg2);
c896fe29
FB		 633}
634
a7812ae4 635static inline void tcg_gen_or_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
c896fe29 636{
951c6300 637 tcg_gen_op3_i64(INDEX_op_or_i64, ret, arg1, arg2);
c896fe29
FB		 638}
639
a7812ae4 640static inline void tcg_gen_xor_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
c896fe29 641{
951c6300 642 tcg_gen_op3_i64(INDEX_op_xor_i64, ret, arg1, arg2);
c896fe29
FB		 643}
644
a7812ae4 645static inline void tcg_gen_shl_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
c896fe29 646{
951c6300 647 tcg_gen_op3_i64(INDEX_op_shl_i64, ret, arg1, arg2);
c896fe29
FB		 648}
649
a7812ae4 650static inline void tcg_gen_shr_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
c896fe29 651{
951c6300 652 tcg_gen_op3_i64(INDEX_op_shr_i64, ret, arg1, arg2);
c896fe29
FB		 653}
654
a7812ae4 655static inline void tcg_gen_sar_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
c896fe29 656{
951c6300 657 tcg_gen_op3_i64(INDEX_op_sar_i64, ret, arg1, arg2);
5105c556
AJ		 658}
659
a7812ae4 660static inline void tcg_gen_mul_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
c896fe29 661{
951c6300 662 tcg_gen_op3_i64(INDEX_op_mul_i64, ret, arg1, arg2);
c896fe29 663}
951c6300 664#else /* TCG_TARGET_REG_BITS == 32 */
d56fea79
RH		 665void tcg_gen_st8_i64(TCGv_i64 arg1, TCGv_ptr arg2, tcg_target_long offset);
666void tcg_gen_st16_i64(TCGv_i64 arg1, TCGv_ptr arg2, tcg_target_long offset);
667void tcg_gen_st32_i64(TCGv_i64 arg1, TCGv_ptr arg2, tcg_target_long offset);
c896fe29 668
d56fea79
RH		 669void tcg_gen_add_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2);
670void tcg_gen_sub_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2);
951c6300
RH		 671
672void tcg_gen_discard_i64(TCGv_i64 arg);
673void tcg_gen_mov_i64(TCGv_i64 ret, TCGv_i64 arg);
951c6300
RH		 674void tcg_gen_ld8u_i64(TCGv_i64 ret, TCGv_ptr arg2, tcg_target_long offset);
675void tcg_gen_ld8s_i64(TCGv_i64 ret, TCGv_ptr arg2, tcg_target_long offset);
676void tcg_gen_ld16u_i64(TCGv_i64 ret, TCGv_ptr arg2, tcg_target_long offset);
677void tcg_gen_ld16s_i64(TCGv_i64 ret, TCGv_ptr arg2, tcg_target_long offset);
678void tcg_gen_ld32u_i64(TCGv_i64 ret, TCGv_ptr arg2, tcg_target_long offset);
679void tcg_gen_ld32s_i64(TCGv_i64 ret, TCGv_ptr arg2, tcg_target_long offset);
680void tcg_gen_ld_i64(TCGv_i64 ret, TCGv_ptr arg2, tcg_target_long offset);
681void tcg_gen_st_i64(TCGv_i64 arg1, TCGv_ptr arg2, tcg_target_long offset);
682void tcg_gen_and_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2);
683void tcg_gen_or_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2);
684void tcg_gen_xor_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2);
685void tcg_gen_shl_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2);
686void tcg_gen_shr_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2);
687void tcg_gen_sar_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2);
688void tcg_gen_mul_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2);
689#endif /* TCG_TARGET_REG_BITS */
c896fe29 690
951c6300 691static inline void tcg_gen_neg_i64(TCGv_i64 ret, TCGv_i64 arg)
c896fe29 692{
951c6300
RH		 693 if (TCG_TARGET_HAS_neg_i64) {
694 tcg_gen_op2_i64(INDEX_op_neg_i64, ret, arg);
695 } else {
696 tcg_gen_subfi_i64(ret, 0, arg);
697 }
c896fe29
FB		 698}
699
951c6300 700/* Size changing operations. */
c896fe29 701
951c6300
RH		 702void tcg_gen_extu_i32_i64(TCGv_i64 ret, TCGv_i32 arg);
703void tcg_gen_ext_i32_i64(TCGv_i64 ret, TCGv_i32 arg);
704void tcg_gen_concat_i32_i64(TCGv_i64 dest, TCGv_i32 low, TCGv_i32 high);
609ad705
RH		 705void tcg_gen_extrl_i64_i32(TCGv_i32 ret, TCGv_i64 arg);
706void tcg_gen_extrh_i64_i32(TCGv_i32 ret, TCGv_i64 arg);
951c6300
RH		 707void tcg_gen_extr_i64_i32(TCGv_i32 lo, TCGv_i32 hi, TCGv_i64 arg);
708void tcg_gen_extr32_i64(TCGv_i64 lo, TCGv_i64 hi, TCGv_i64 arg);
c896fe29 709
4771e71c
RH		 710void tcg_gen_mov_i128(TCGv_i128 dst, TCGv_i128 src);
711void tcg_gen_extr_i128_i64(TCGv_i64 lo, TCGv_i64 hi, TCGv_i128 arg);
712void tcg_gen_concat_i64_i128(TCGv_i128 ret, TCGv_i64 lo, TCGv_i64 hi);
713
951c6300 714static inline void tcg_gen_concat32_i64(TCGv_i64 ret, TCGv_i64 lo, TCGv_i64 hi)
c896fe29 715{
951c6300 716 tcg_gen_deposit_i64(ret, lo, hi, 32, 32);
c896fe29
FB		 717}
718
951c6300 719/* QEMU specific operations. */
c896fe29 720
951c6300
RH		 721#ifndef TARGET_LONG_BITS
722#error must include QEMU headers
723#endif
c896fe29 724
9aef40ed
RH		 725#if TARGET_INSN_START_WORDS == 1
726# if TARGET_LONG_BITS <= TCG_TARGET_REG_BITS
727static inline void tcg_gen_insn_start(target_ulong pc)
c896fe29 728{
b7e8b17a 729 tcg_gen_op1(INDEX_op_insn_start, pc);
9aef40ed
RH		 730}
731# else
732static inline void tcg_gen_insn_start(target_ulong pc)
733{
b7e8b17a 734 tcg_gen_op2(INDEX_op_insn_start, (uint32_t)pc, (uint32_t)(pc >> 32));
9aef40ed
RH		 735}
736# endif
737#elif TARGET_INSN_START_WORDS == 2
738# if TARGET_LONG_BITS <= TCG_TARGET_REG_BITS
739static inline void tcg_gen_insn_start(target_ulong pc, target_ulong a1)
740{
b7e8b17a 741 tcg_gen_op2(INDEX_op_insn_start, pc, a1);
9aef40ed
RH		 742}
743# else
744static inline void tcg_gen_insn_start(target_ulong pc, target_ulong a1)
745{
b7e8b17a 746 tcg_gen_op4(INDEX_op_insn_start,
9aef40ed
RH		 747 (uint32_t)pc, (uint32_t)(pc >> 32),
748 (uint32_t)a1, (uint32_t)(a1 >> 32));
749}
750# endif
751#elif TARGET_INSN_START_WORDS == 3
752# if TARGET_LONG_BITS <= TCG_TARGET_REG_BITS
753static inline void tcg_gen_insn_start(target_ulong pc, target_ulong a1,
754 target_ulong a2)
755{
b7e8b17a 756 tcg_gen_op3(INDEX_op_insn_start, pc, a1, a2);
9aef40ed
RH		 757}
758# else
759static inline void tcg_gen_insn_start(target_ulong pc, target_ulong a1,
760 target_ulong a2)
761{
b7e8b17a 762 tcg_gen_op6(INDEX_op_insn_start,
9aef40ed
RH		 763 (uint32_t)pc, (uint32_t)(pc >> 32),
764 (uint32_t)a1, (uint32_t)(a1 >> 32),
765 (uint32_t)a2, (uint32_t)(a2 >> 32));
766}
767# endif
951c6300 768#else
9aef40ed 769# error "Unhandled number of operands to insn_start"
951c6300 770#endif
c896fe29 771
07ea28b4
RH		 772/**
773 * tcg_gen_exit_tb() - output exit_tb TCG operation
774 * @tb: The TranslationBlock from which we are exiting
775 * @idx: Direct jump slot index, or exit request
776 *
777 * See tcg/README for more info about this TCG operation.
778 * See also tcg.h and the block comment above TB_EXIT_MASK.
779 *
780 * For a normal exit from the TB, back to the main loop, @tb should
781 * be NULL and @idx should be 0. Otherwise, @tb should be valid and
782 * @idx should be one of the TB_EXIT_ values.
783 */
d9971435 784void tcg_gen_exit_tb(const TranslationBlock *tb, unsigned idx);
c896fe29 785
5b053a4a
SF		 786/**
787 * tcg_gen_goto_tb() - output goto_tb TCG operation
788 * @idx: Direct jump slot index (0 or 1)
789 *
790 * See tcg/README for more info about this TCG operation.
791 *
90aa39a1
SF		 792 * NOTE: In softmmu emulation, direct jumps with goto_tb are only safe within
793 * the pages this TB resides in because we don't take care of direct jumps when
794 * address mapping changes, e.g. in tlb_flush(). In user mode, there's only a
795 * static address translation, so the destination address is always valid, TBs
796 * are always invalidated properly, and direct jumps are reset when mapping
797 * changes.
5b053a4a 798 */
951c6300 799void tcg_gen_goto_tb(unsigned idx);
c896fe29 800
cedbcb01 801/**
7f11636d 802 * tcg_gen_lookup_and_goto_ptr() - look up the current TB, jump to it if valid
cedbcb01
EC		 803 * @addr: Guest address of the target TB
804 *
805 * If the TB is not valid, jump to the epilogue.
806 *
807 * This operation is optional. If the TCG backend does not implement goto_ptr,
808 * this op is equivalent to calling tcg_gen_exit_tb() with 0 as the argument.
809 */
7f11636d 810void tcg_gen_lookup_and_goto_ptr(void);
cedbcb01 811
38b47b19
EC		 812static inline void tcg_gen_plugin_cb_start(unsigned from, unsigned type,
813 unsigned wr)
814{
815 tcg_gen_op3(INDEX_op_plugin_cb_start, from, type, wr);
816}
817
818static inline void tcg_gen_plugin_cb_end(void)
819{
d4478943 820 tcg_emit_op(INDEX_op_plugin_cb_end, 0);
38b47b19
EC		 821}
822
a7812ae4 823#if TARGET_LONG_BITS == 32
a7812ae4 824#define tcg_temp_new() tcg_temp_new_i32()
a7812ae4 825#define tcg_global_mem_new tcg_global_mem_new_i32
a7812ae4 826#define tcg_temp_free tcg_temp_free_i32
f713d6ad
RH		 827#define tcg_gen_qemu_ld_tl tcg_gen_qemu_ld_i32
828#define tcg_gen_qemu_st_tl tcg_gen_qemu_st_i32
a7812ae4 829#else
a7812ae4 830#define tcg_temp_new() tcg_temp_new_i64()
a7812ae4 831#define tcg_global_mem_new tcg_global_mem_new_i64
a7812ae4 832#define tcg_temp_free tcg_temp_free_i64
f713d6ad
RH		 833#define tcg_gen_qemu_ld_tl tcg_gen_qemu_ld_i64
834#define tcg_gen_qemu_st_tl tcg_gen_qemu_st_i64
a7812ae4
PB		 835#endif
836
14776ab5
TN		 837void tcg_gen_qemu_ld_i32(TCGv_i32, TCGv, TCGArg, MemOp);
838void tcg_gen_qemu_st_i32(TCGv_i32, TCGv, TCGArg, MemOp);
839void tcg_gen_qemu_ld_i64(TCGv_i64, TCGv, TCGArg, MemOp);
840void tcg_gen_qemu_st_i64(TCGv_i64, TCGv, TCGArg, MemOp);
cb48f365
RH		 841void tcg_gen_qemu_ld_i128(TCGv_i128, TCGv, TCGArg, MemOp);
842void tcg_gen_qemu_st_i128(TCGv_i128, TCGv, TCGArg, MemOp);
c896fe29 843
ac56dd48 844static inline void tcg_gen_qemu_ld8u(TCGv ret, TCGv addr, int mem_index)
c896fe29 845{
f713d6ad 846 tcg_gen_qemu_ld_tl(ret, addr, mem_index, MO_UB);
c896fe29
FB		 847}
848
ac56dd48 849static inline void tcg_gen_qemu_ld8s(TCGv ret, TCGv addr, int mem_index)
c896fe29 850{
f713d6ad 851 tcg_gen_qemu_ld_tl(ret, addr, mem_index, MO_SB);
c896fe29
FB		 852}
853
ac56dd48 854static inline void tcg_gen_qemu_ld16u(TCGv ret, TCGv addr, int mem_index)
c896fe29 855{
f713d6ad 856 tcg_gen_qemu_ld_tl(ret, addr, mem_index, MO_TEUW);
c896fe29
FB		 857}
858
ac56dd48 859static inline void tcg_gen_qemu_ld16s(TCGv ret, TCGv addr, int mem_index)
c896fe29 860{
f713d6ad 861 tcg_gen_qemu_ld_tl(ret, addr, mem_index, MO_TESW);
c896fe29
FB		 862}
863
ac56dd48 864static inline void tcg_gen_qemu_ld32u(TCGv ret, TCGv addr, int mem_index)
c896fe29 865{
f713d6ad 866 tcg_gen_qemu_ld_tl(ret, addr, mem_index, MO_TEUL);
c896fe29
FB		 867}
868
ac56dd48 869static inline void tcg_gen_qemu_ld32s(TCGv ret, TCGv addr, int mem_index)
c896fe29 870{
f713d6ad 871 tcg_gen_qemu_ld_tl(ret, addr, mem_index, MO_TESL);
c896fe29
FB		 872}
873
a7812ae4 874static inline void tcg_gen_qemu_ld64(TCGv_i64 ret, TCGv addr, int mem_index)
c896fe29 875{
fc313c64 876 tcg_gen_qemu_ld_i64(ret, addr, mem_index, MO_TEUQ);
c896fe29
FB		 877}
878
ac56dd48 879static inline void tcg_gen_qemu_st8(TCGv arg, TCGv addr, int mem_index)
c896fe29 880{
f713d6ad 881 tcg_gen_qemu_st_tl(arg, addr, mem_index, MO_UB);
c896fe29
FB		 882}
883
ac56dd48 884static inline void tcg_gen_qemu_st16(TCGv arg, TCGv addr, int mem_index)
c896fe29 885{
f713d6ad 886 tcg_gen_qemu_st_tl(arg, addr, mem_index, MO_TEUW);
c896fe29
FB		 887}
888
ac56dd48 889static inline void tcg_gen_qemu_st32(TCGv arg, TCGv addr, int mem_index)
c896fe29 890{
f713d6ad 891 tcg_gen_qemu_st_tl(arg, addr, mem_index, MO_TEUL);
c896fe29
FB		 892}
893
a7812ae4 894static inline void tcg_gen_qemu_st64(TCGv_i64 arg, TCGv addr, int mem_index)
c896fe29 895{
fc313c64 896 tcg_gen_qemu_st_i64(arg, addr, mem_index, MO_TEUQ);
c896fe29
FB		 897}
898
c482cb11 899void tcg_gen_atomic_cmpxchg_i32(TCGv_i32, TCGv, TCGv_i32, TCGv_i32,
14776ab5 900 TCGArg, MemOp);
c482cb11 901void tcg_gen_atomic_cmpxchg_i64(TCGv_i64, TCGv, TCGv_i64, TCGv_i64,
14776ab5 902 TCGArg, MemOp);
123ae568
RH		 903void tcg_gen_atomic_cmpxchg_i128(TCGv_i128, TCGv, TCGv_i128, TCGv_i128,
904 TCGArg, MemOp);
905
d1beee4d
RH		 906void tcg_gen_nonatomic_cmpxchg_i32(TCGv_i32, TCGv, TCGv_i32, TCGv_i32,
907 TCGArg, MemOp);
908void tcg_gen_nonatomic_cmpxchg_i64(TCGv_i64, TCGv, TCGv_i64, TCGv_i64,
909 TCGArg, MemOp);
123ae568
RH		 910void tcg_gen_nonatomic_cmpxchg_i128(TCGv_i128, TCGv, TCGv_i128, TCGv_i128,
911 TCGArg, MemOp);
14776ab5
TN		 912
913void tcg_gen_atomic_xchg_i32(TCGv_i32, TCGv, TCGv_i32, TCGArg, MemOp);
914void tcg_gen_atomic_xchg_i64(TCGv_i64, TCGv, TCGv_i64, TCGArg, MemOp);
915
916void tcg_gen_atomic_fetch_add_i32(TCGv_i32, TCGv, TCGv_i32, TCGArg, MemOp);
917void tcg_gen_atomic_fetch_add_i64(TCGv_i64, TCGv, TCGv_i64, TCGArg, MemOp);
918void tcg_gen_atomic_fetch_and_i32(TCGv_i32, TCGv, TCGv_i32, TCGArg, MemOp);
919void tcg_gen_atomic_fetch_and_i64(TCGv_i64, TCGv, TCGv_i64, TCGArg, MemOp);
920void tcg_gen_atomic_fetch_or_i32(TCGv_i32, TCGv, TCGv_i32, TCGArg, MemOp);
921void tcg_gen_atomic_fetch_or_i64(TCGv_i64, TCGv, TCGv_i64, TCGArg, MemOp);
922void tcg_gen_atomic_fetch_xor_i32(TCGv_i32, TCGv, TCGv_i32, TCGArg, MemOp);
923void tcg_gen_atomic_fetch_xor_i64(TCGv_i64, TCGv, TCGv_i64, TCGArg, MemOp);
924void tcg_gen_atomic_fetch_smin_i32(TCGv_i32, TCGv, TCGv_i32, TCGArg, MemOp);
925void tcg_gen_atomic_fetch_smin_i64(TCGv_i64, TCGv, TCGv_i64, TCGArg, MemOp);
926void tcg_gen_atomic_fetch_umin_i32(TCGv_i32, TCGv, TCGv_i32, TCGArg, MemOp);
927void tcg_gen_atomic_fetch_umin_i64(TCGv_i64, TCGv, TCGv_i64, TCGArg, MemOp);
928void tcg_gen_atomic_fetch_smax_i32(TCGv_i32, TCGv, TCGv_i32, TCGArg, MemOp);
929void tcg_gen_atomic_fetch_smax_i64(TCGv_i64, TCGv, TCGv_i64, TCGArg, MemOp);
930void tcg_gen_atomic_fetch_umax_i32(TCGv_i32, TCGv, TCGv_i32, TCGArg, MemOp);
931void tcg_gen_atomic_fetch_umax_i64(TCGv_i64, TCGv, TCGv_i64, TCGArg, MemOp);
932
933void tcg_gen_atomic_add_fetch_i32(TCGv_i32, TCGv, TCGv_i32, TCGArg, MemOp);
934void tcg_gen_atomic_add_fetch_i64(TCGv_i64, TCGv, TCGv_i64, TCGArg, MemOp);
935void tcg_gen_atomic_and_fetch_i32(TCGv_i32, TCGv, TCGv_i32, TCGArg, MemOp);
936void tcg_gen_atomic_and_fetch_i64(TCGv_i64, TCGv, TCGv_i64, TCGArg, MemOp);
937void tcg_gen_atomic_or_fetch_i32(TCGv_i32, TCGv, TCGv_i32, TCGArg, MemOp);
938void tcg_gen_atomic_or_fetch_i64(TCGv_i64, TCGv, TCGv_i64, TCGArg, MemOp);
939void tcg_gen_atomic_xor_fetch_i32(TCGv_i32, TCGv, TCGv_i32, TCGArg, MemOp);
940void tcg_gen_atomic_xor_fetch_i64(TCGv_i64, TCGv, TCGv_i64, TCGArg, MemOp);
941void tcg_gen_atomic_smin_fetch_i32(TCGv_i32, TCGv, TCGv_i32, TCGArg, MemOp);
942void tcg_gen_atomic_smin_fetch_i64(TCGv_i64, TCGv, TCGv_i64, TCGArg, MemOp);
943void tcg_gen_atomic_umin_fetch_i32(TCGv_i32, TCGv, TCGv_i32, TCGArg, MemOp);
944void tcg_gen_atomic_umin_fetch_i64(TCGv_i64, TCGv, TCGv_i64, TCGArg, MemOp);
945void tcg_gen_atomic_smax_fetch_i32(TCGv_i32, TCGv, TCGv_i32, TCGArg, MemOp);
946void tcg_gen_atomic_smax_fetch_i64(TCGv_i64, TCGv, TCGv_i64, TCGArg, MemOp);
947void tcg_gen_atomic_umax_fetch_i32(TCGv_i32, TCGv, TCGv_i32, TCGArg, MemOp);
948void tcg_gen_atomic_umax_fetch_i64(TCGv_i64, TCGv, TCGv_i64, TCGArg, MemOp);
c482cb11 949
d2fd745f
RH		 950void tcg_gen_mov_vec(TCGv_vec, TCGv_vec);
951void tcg_gen_dup_i32_vec(unsigned vece, TCGv_vec, TCGv_i32);
952void tcg_gen_dup_i64_vec(unsigned vece, TCGv_vec, TCGv_i64);
37ee55a0 953void tcg_gen_dup_mem_vec(unsigned vece, TCGv_vec, TCGv_ptr, tcg_target_long);
db432672 954void tcg_gen_dupi_vec(unsigned vece, TCGv_vec, uint64_t);
d2fd745f
RH		 955void tcg_gen_add_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec b);
956void tcg_gen_sub_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec b);
3774030a 957void tcg_gen_mul_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec b);
d2fd745f
RH		 958void tcg_gen_and_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec b);
959void tcg_gen_or_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec b);
960void tcg_gen_xor_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec b);
961void tcg_gen_andc_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec b);
962void tcg_gen_orc_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec b);
f550805d
RH		 963void tcg_gen_nand_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec b);
964void tcg_gen_nor_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec b);
965void tcg_gen_eqv_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec b);
d2fd745f
RH		 966void tcg_gen_not_vec(unsigned vece, TCGv_vec r, TCGv_vec a);
967void tcg_gen_neg_vec(unsigned vece, TCGv_vec r, TCGv_vec a);
ff1f11f7 968void tcg_gen_abs_vec(unsigned vece, TCGv_vec r, TCGv_vec a);
8afaf050
RH		 969void tcg_gen_ssadd_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec b);
970void tcg_gen_usadd_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec b);
971void tcg_gen_sssub_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec b);
972void tcg_gen_ussub_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec b);
dd0a0fcd
RH		 973void tcg_gen_smin_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec b);
974void tcg_gen_umin_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec b);
975void tcg_gen_smax_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec b);
976void tcg_gen_umax_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec b);
d2fd745f 977
d0ec9796
RH		 978void tcg_gen_shli_vec(unsigned vece, TCGv_vec r, TCGv_vec a, int64_t i);
979void tcg_gen_shri_vec(unsigned vece, TCGv_vec r, TCGv_vec a, int64_t i);
980void tcg_gen_sari_vec(unsigned vece, TCGv_vec r, TCGv_vec a, int64_t i);
b0f7e744
RH		 981void tcg_gen_rotli_vec(unsigned vece, TCGv_vec r, TCGv_vec a, int64_t i);
982void tcg_gen_rotri_vec(unsigned vece, TCGv_vec r, TCGv_vec a, int64_t i);
d0ec9796 983
b4578cd9
RH		 984void tcg_gen_shls_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_i32 s);
985void tcg_gen_shrs_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_i32 s);
986void tcg_gen_sars_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_i32 s);
23850a74 987void tcg_gen_rotls_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_i32 s);
b4578cd9 988
5ee5c14c
RH		 989void tcg_gen_shlv_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec s);
990void tcg_gen_shrv_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec s);
991void tcg_gen_sarv_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec s);
5d0ceda9
RH		 992void tcg_gen_rotlv_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec s);
993void tcg_gen_rotrv_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec s);
5ee5c14c 994
212be173
RH		 995void tcg_gen_cmp_vec(TCGCond cond, unsigned vece, TCGv_vec r,
996 TCGv_vec a, TCGv_vec b);
997
38dc1294
RH		 998void tcg_gen_bitsel_vec(unsigned vece, TCGv_vec r, TCGv_vec a,
999 TCGv_vec b, TCGv_vec c);
f75da298
RH		 1000void tcg_gen_cmpsel_vec(TCGCond cond, unsigned vece, TCGv_vec r,
1001 TCGv_vec a, TCGv_vec b, TCGv_vec c, TCGv_vec d);
38dc1294 1002
d2fd745f
RH		 1003void tcg_gen_ld_vec(TCGv_vec r, TCGv_ptr base, TCGArg offset);
1004void tcg_gen_st_vec(TCGv_vec r, TCGv_ptr base, TCGArg offset);
1005void tcg_gen_stl_vec(TCGv_vec r, TCGv_ptr base, TCGArg offset, TCGType t);
1006
f8422f52 1007#if TARGET_LONG_BITS == 64
f8422f52
BS		 1008#define tcg_gen_movi_tl tcg_gen_movi_i64
1009#define tcg_gen_mov_tl tcg_gen_mov_i64
1010#define tcg_gen_ld8u_tl tcg_gen_ld8u_i64
1011#define tcg_gen_ld8s_tl tcg_gen_ld8s_i64
1012#define tcg_gen_ld16u_tl tcg_gen_ld16u_i64
1013#define tcg_gen_ld16s_tl tcg_gen_ld16s_i64
1014#define tcg_gen_ld32u_tl tcg_gen_ld32u_i64
1015#define tcg_gen_ld32s_tl tcg_gen_ld32s_i64
1016#define tcg_gen_ld_tl tcg_gen_ld_i64
1017#define tcg_gen_st8_tl tcg_gen_st8_i64
1018#define tcg_gen_st16_tl tcg_gen_st16_i64
1019#define tcg_gen_st32_tl tcg_gen_st32_i64
1020#define tcg_gen_st_tl tcg_gen_st_i64
1021#define tcg_gen_add_tl tcg_gen_add_i64
1022#define tcg_gen_addi_tl tcg_gen_addi_i64
1023#define tcg_gen_sub_tl tcg_gen_sub_i64
390efc54 1024#define tcg_gen_neg_tl tcg_gen_neg_i64
ff1f11f7 1025#define tcg_gen_abs_tl tcg_gen_abs_i64
10460c8a 1026#define tcg_gen_subfi_tl tcg_gen_subfi_i64
f8422f52
BS		 1027#define tcg_gen_subi_tl tcg_gen_subi_i64
1028#define tcg_gen_and_tl tcg_gen_and_i64
1029#define tcg_gen_andi_tl tcg_gen_andi_i64
1030#define tcg_gen_or_tl tcg_gen_or_i64
1031#define tcg_gen_ori_tl tcg_gen_ori_i64
1032#define tcg_gen_xor_tl tcg_gen_xor_i64
1033#define tcg_gen_xori_tl tcg_gen_xori_i64
0b6ce4cf 1034#define tcg_gen_not_tl tcg_gen_not_i64
f8422f52
BS		 1035#define tcg_gen_shl_tl tcg_gen_shl_i64
1036#define tcg_gen_shli_tl tcg_gen_shli_i64
1037#define tcg_gen_shr_tl tcg_gen_shr_i64
1038#define tcg_gen_shri_tl tcg_gen_shri_i64
1039#define tcg_gen_sar_tl tcg_gen_sar_i64
1040#define tcg_gen_sari_tl tcg_gen_sari_i64
0cf767d6 1041#define tcg_gen_brcond_tl tcg_gen_brcond_i64
cb63669a 1042#define tcg_gen_brcondi_tl tcg_gen_brcondi_i64
be210acb 1043#define tcg_gen_setcond_tl tcg_gen_setcond_i64
add1e7ea 1044#define tcg_gen_setcondi_tl tcg_gen_setcondi_i64
f730fd27
TS		 1045#define tcg_gen_mul_tl tcg_gen_mul_i64
1046#define tcg_gen_muli_tl tcg_gen_muli_i64
ab36421e
AJ		 1047#define tcg_gen_div_tl tcg_gen_div_i64
1048#define tcg_gen_rem_tl tcg_gen_rem_i64
864951af
AJ		 1049#define tcg_gen_divu_tl tcg_gen_divu_i64
1050#define tcg_gen_remu_tl tcg_gen_remu_i64
a768e4b2 1051#define tcg_gen_discard_tl tcg_gen_discard_i64
ecc7b3aa 1052#define tcg_gen_trunc_tl_i32 tcg_gen_extrl_i64_i32
e429073d
BS		 1053#define tcg_gen_trunc_i64_tl tcg_gen_mov_i64
1054#define tcg_gen_extu_i32_tl tcg_gen_extu_i32_i64
1055#define tcg_gen_ext_i32_tl tcg_gen_ext_i32_i64
1056#define tcg_gen_extu_tl_i64 tcg_gen_mov_i64
1057#define tcg_gen_ext_tl_i64 tcg_gen_mov_i64
0b6ce4cf
FB		 1058#define tcg_gen_ext8u_tl tcg_gen_ext8u_i64
1059#define tcg_gen_ext8s_tl tcg_gen_ext8s_i64
1060#define tcg_gen_ext16u_tl tcg_gen_ext16u_i64
1061#define tcg_gen_ext16s_tl tcg_gen_ext16s_i64
1062#define tcg_gen_ext32u_tl tcg_gen_ext32u_i64
1063#define tcg_gen_ext32s_tl tcg_gen_ext32s_i64
911d79ba
AJ		 1064#define tcg_gen_bswap16_tl tcg_gen_bswap16_i64
1065#define tcg_gen_bswap32_tl tcg_gen_bswap32_i64
1066#define tcg_gen_bswap64_tl tcg_gen_bswap64_i64
a66424ba 1067#define tcg_gen_bswap_tl tcg_gen_bswap64_i64
46be8425
RH		 1068#define tcg_gen_hswap_tl tcg_gen_hswap_i64
1069#define tcg_gen_wswap_tl tcg_gen_wswap_i64
945ca823 1070#define tcg_gen_concat_tl_i64 tcg_gen_concat32_i64
3c51a985 1071#define tcg_gen_extr_i64_tl tcg_gen_extr32_i64
f24cb33e
AJ		 1072#define tcg_gen_andc_tl tcg_gen_andc_i64
1073#define tcg_gen_eqv_tl tcg_gen_eqv_i64
1074#define tcg_gen_nand_tl tcg_gen_nand_i64
1075#define tcg_gen_nor_tl tcg_gen_nor_i64
1076#define tcg_gen_orc_tl tcg_gen_orc_i64
0e28d006
RH		 1077#define tcg_gen_clz_tl tcg_gen_clz_i64
1078#define tcg_gen_ctz_tl tcg_gen_ctz_i64
1079#define tcg_gen_clzi_tl tcg_gen_clzi_i64
1080#define tcg_gen_ctzi_tl tcg_gen_ctzi_i64
086920c2 1081#define tcg_gen_clrsb_tl tcg_gen_clrsb_i64
a768e4e9 1082#define tcg_gen_ctpop_tl tcg_gen_ctpop_i64
15824571
AJ		 1083#define tcg_gen_rotl_tl tcg_gen_rotl_i64
1084#define tcg_gen_rotli_tl tcg_gen_rotli_i64
1085#define tcg_gen_rotr_tl tcg_gen_rotr_i64
1086#define tcg_gen_rotri_tl tcg_gen_rotri_i64
b7767f0f 1087#define tcg_gen_deposit_tl tcg_gen_deposit_i64
07cc68d5 1088#define tcg_gen_deposit_z_tl tcg_gen_deposit_z_i64
7ec8bab3
RH		 1089#define tcg_gen_extract_tl tcg_gen_extract_i64
1090#define tcg_gen_sextract_tl tcg_gen_sextract_i64
2089fcc9 1091#define tcg_gen_extract2_tl tcg_gen_extract2_i64
4d87fcdd 1092#define tcg_constant_tl tcg_constant_i64
ffc5ea09 1093#define tcg_gen_movcond_tl tcg_gen_movcond_i64
f6953a73
RH		 1094#define tcg_gen_add2_tl tcg_gen_add2_i64
1095#define tcg_gen_sub2_tl tcg_gen_sub2_i64
696a8be6
RH		 1096#define tcg_gen_mulu2_tl tcg_gen_mulu2_i64
1097#define tcg_gen_muls2_tl tcg_gen_muls2_i64
5087abfb 1098#define tcg_gen_mulsu2_tl tcg_gen_mulsu2_i64
b87fb8cd
RH		 1099#define tcg_gen_smin_tl tcg_gen_smin_i64
1100#define tcg_gen_umin_tl tcg_gen_umin_i64
1101#define tcg_gen_smax_tl tcg_gen_smax_i64
1102#define tcg_gen_umax_tl tcg_gen_umax_i64
c482cb11
RH		 1103#define tcg_gen_atomic_cmpxchg_tl tcg_gen_atomic_cmpxchg_i64
1104#define tcg_gen_atomic_xchg_tl tcg_gen_atomic_xchg_i64
1105#define tcg_gen_atomic_fetch_add_tl tcg_gen_atomic_fetch_add_i64
1106#define tcg_gen_atomic_fetch_and_tl tcg_gen_atomic_fetch_and_i64
1107#define tcg_gen_atomic_fetch_or_tl tcg_gen_atomic_fetch_or_i64
1108#define tcg_gen_atomic_fetch_xor_tl tcg_gen_atomic_fetch_xor_i64
5507c2bf
RH		 1109#define tcg_gen_atomic_fetch_smin_tl tcg_gen_atomic_fetch_smin_i64
1110#define tcg_gen_atomic_fetch_umin_tl tcg_gen_atomic_fetch_umin_i64
1111#define tcg_gen_atomic_fetch_smax_tl tcg_gen_atomic_fetch_smax_i64
1112#define tcg_gen_atomic_fetch_umax_tl tcg_gen_atomic_fetch_umax_i64
c482cb11
RH		 1113#define tcg_gen_atomic_add_fetch_tl tcg_gen_atomic_add_fetch_i64
1114#define tcg_gen_atomic_and_fetch_tl tcg_gen_atomic_and_fetch_i64
1115#define tcg_gen_atomic_or_fetch_tl tcg_gen_atomic_or_fetch_i64
1116#define tcg_gen_atomic_xor_fetch_tl tcg_gen_atomic_xor_fetch_i64
5507c2bf
RH		 1117#define tcg_gen_atomic_smin_fetch_tl tcg_gen_atomic_smin_fetch_i64
1118#define tcg_gen_atomic_umin_fetch_tl tcg_gen_atomic_umin_fetch_i64
1119#define tcg_gen_atomic_smax_fetch_tl tcg_gen_atomic_smax_fetch_i64
1120#define tcg_gen_atomic_umax_fetch_tl tcg_gen_atomic_umax_fetch_i64
d2fd745f 1121#define tcg_gen_dup_tl_vec tcg_gen_dup_i64_vec
614dd4f3 1122#define tcg_gen_dup_tl tcg_gen_dup_i64
f8422f52 1123#else
f8422f52
BS		 1124#define tcg_gen_movi_tl tcg_gen_movi_i32
1125#define tcg_gen_mov_tl tcg_gen_mov_i32
1126#define tcg_gen_ld8u_tl tcg_gen_ld8u_i32
1127#define tcg_gen_ld8s_tl tcg_gen_ld8s_i32
1128#define tcg_gen_ld16u_tl tcg_gen_ld16u_i32
1129#define tcg_gen_ld16s_tl tcg_gen_ld16s_i32
1130#define tcg_gen_ld32u_tl tcg_gen_ld_i32
1131#define tcg_gen_ld32s_tl tcg_gen_ld_i32
1132#define tcg_gen_ld_tl tcg_gen_ld_i32
1133#define tcg_gen_st8_tl tcg_gen_st8_i32
1134#define tcg_gen_st16_tl tcg_gen_st16_i32
1135#define tcg_gen_st32_tl tcg_gen_st_i32
1136#define tcg_gen_st_tl tcg_gen_st_i32
1137#define tcg_gen_add_tl tcg_gen_add_i32
1138#define tcg_gen_addi_tl tcg_gen_addi_i32
1139#define tcg_gen_sub_tl tcg_gen_sub_i32
390efc54 1140#define tcg_gen_neg_tl tcg_gen_neg_i32
ff1f11f7 1141#define tcg_gen_abs_tl tcg_gen_abs_i32
0045734a 1142#define tcg_gen_subfi_tl tcg_gen_subfi_i32
f8422f52
BS		 1143#define tcg_gen_subi_tl tcg_gen_subi_i32
1144#define tcg_gen_and_tl tcg_gen_and_i32
1145#define tcg_gen_andi_tl tcg_gen_andi_i32
1146#define tcg_gen_or_tl tcg_gen_or_i32
1147#define tcg_gen_ori_tl tcg_gen_ori_i32
1148#define tcg_gen_xor_tl tcg_gen_xor_i32
1149#define tcg_gen_xori_tl tcg_gen_xori_i32
0b6ce4cf 1150#define tcg_gen_not_tl tcg_gen_not_i32
f8422f52
BS		 1151#define tcg_gen_shl_tl tcg_gen_shl_i32
1152#define tcg_gen_shli_tl tcg_gen_shli_i32
1153#define tcg_gen_shr_tl tcg_gen_shr_i32
1154#define tcg_gen_shri_tl tcg_gen_shri_i32
1155#define tcg_gen_sar_tl tcg_gen_sar_i32
1156#define tcg_gen_sari_tl tcg_gen_sari_i32
0cf767d6 1157#define tcg_gen_brcond_tl tcg_gen_brcond_i32
cb63669a 1158#define tcg_gen_brcondi_tl tcg_gen_brcondi_i32
be210acb 1159#define tcg_gen_setcond_tl tcg_gen_setcond_i32
add1e7ea 1160#define tcg_gen_setcondi_tl tcg_gen_setcondi_i32
f730fd27
TS		 1161#define tcg_gen_mul_tl tcg_gen_mul_i32
1162#define tcg_gen_muli_tl tcg_gen_muli_i32
ab36421e
AJ		 1163#define tcg_gen_div_tl tcg_gen_div_i32
1164#define tcg_gen_rem_tl tcg_gen_rem_i32
864951af
AJ		 1165#define tcg_gen_divu_tl tcg_gen_divu_i32
1166#define tcg_gen_remu_tl tcg_gen_remu_i32
a768e4b2 1167#define tcg_gen_discard_tl tcg_gen_discard_i32
e429073d 1168#define tcg_gen_trunc_tl_i32 tcg_gen_mov_i32
ecc7b3aa 1169#define tcg_gen_trunc_i64_tl tcg_gen_extrl_i64_i32
e429073d
BS		 1170#define tcg_gen_extu_i32_tl tcg_gen_mov_i32
1171#define tcg_gen_ext_i32_tl tcg_gen_mov_i32
1172#define tcg_gen_extu_tl_i64 tcg_gen_extu_i32_i64
1173#define tcg_gen_ext_tl_i64 tcg_gen_ext_i32_i64
0b6ce4cf
FB		 1174#define tcg_gen_ext8u_tl tcg_gen_ext8u_i32
1175#define tcg_gen_ext8s_tl tcg_gen_ext8s_i32
1176#define tcg_gen_ext16u_tl tcg_gen_ext16u_i32
1177#define tcg_gen_ext16s_tl tcg_gen_ext16s_i32
1178#define tcg_gen_ext32u_tl tcg_gen_mov_i32
1179#define tcg_gen_ext32s_tl tcg_gen_mov_i32
911d79ba 1180#define tcg_gen_bswap16_tl tcg_gen_bswap16_i32
2b836c2a 1181#define tcg_gen_bswap32_tl(D, S, F) tcg_gen_bswap32_i32(D, S)
a66424ba 1182#define tcg_gen_bswap_tl tcg_gen_bswap32_i32
46be8425 1183#define tcg_gen_hswap_tl tcg_gen_hswap_i32
945ca823 1184#define tcg_gen_concat_tl_i64 tcg_gen_concat_i32_i64
e3eb9806 1185#define tcg_gen_extr_i64_tl tcg_gen_extr_i64_i32
f24cb33e
AJ		 1186#define tcg_gen_andc_tl tcg_gen_andc_i32
1187#define tcg_gen_eqv_tl tcg_gen_eqv_i32
1188#define tcg_gen_nand_tl tcg_gen_nand_i32
1189#define tcg_gen_nor_tl tcg_gen_nor_i32
1190#define tcg_gen_orc_tl tcg_gen_orc_i32
0e28d006
RH		 1191#define tcg_gen_clz_tl tcg_gen_clz_i32
1192#define tcg_gen_ctz_tl tcg_gen_ctz_i32
1193#define tcg_gen_clzi_tl tcg_gen_clzi_i32
1194#define tcg_gen_ctzi_tl tcg_gen_ctzi_i32
086920c2 1195#define tcg_gen_clrsb_tl tcg_gen_clrsb_i32
a768e4e9 1196#define tcg_gen_ctpop_tl tcg_gen_ctpop_i32
15824571
AJ		 1197#define tcg_gen_rotl_tl tcg_gen_rotl_i32
1198#define tcg_gen_rotli_tl tcg_gen_rotli_i32
1199#define tcg_gen_rotr_tl tcg_gen_rotr_i32
1200#define tcg_gen_rotri_tl tcg_gen_rotri_i32
b7767f0f 1201#define tcg_gen_deposit_tl tcg_gen_deposit_i32
07cc68d5 1202#define tcg_gen_deposit_z_tl tcg_gen_deposit_z_i32
7ec8bab3
RH		 1203#define tcg_gen_extract_tl tcg_gen_extract_i32
1204#define tcg_gen_sextract_tl tcg_gen_sextract_i32
2089fcc9 1205#define tcg_gen_extract2_tl tcg_gen_extract2_i32
4d87fcdd 1206#define tcg_constant_tl tcg_constant_i32
ffc5ea09 1207#define tcg_gen_movcond_tl tcg_gen_movcond_i32
f6953a73
RH		 1208#define tcg_gen_add2_tl tcg_gen_add2_i32
1209#define tcg_gen_sub2_tl tcg_gen_sub2_i32
696a8be6
RH		 1210#define tcg_gen_mulu2_tl tcg_gen_mulu2_i32
1211#define tcg_gen_muls2_tl tcg_gen_muls2_i32
5087abfb 1212#define tcg_gen_mulsu2_tl tcg_gen_mulsu2_i32
b87fb8cd
RH		 1213#define tcg_gen_smin_tl tcg_gen_smin_i32
1214#define tcg_gen_umin_tl tcg_gen_umin_i32
1215#define tcg_gen_smax_tl tcg_gen_smax_i32
1216#define tcg_gen_umax_tl tcg_gen_umax_i32
c482cb11
RH		 1217#define tcg_gen_atomic_cmpxchg_tl tcg_gen_atomic_cmpxchg_i32
1218#define tcg_gen_atomic_xchg_tl tcg_gen_atomic_xchg_i32
1219#define tcg_gen_atomic_fetch_add_tl tcg_gen_atomic_fetch_add_i32
1220#define tcg_gen_atomic_fetch_and_tl tcg_gen_atomic_fetch_and_i32
1221#define tcg_gen_atomic_fetch_or_tl tcg_gen_atomic_fetch_or_i32
1222#define tcg_gen_atomic_fetch_xor_tl tcg_gen_atomic_fetch_xor_i32
5507c2bf
RH		 1223#define tcg_gen_atomic_fetch_smin_tl tcg_gen_atomic_fetch_smin_i32
1224#define tcg_gen_atomic_fetch_umin_tl tcg_gen_atomic_fetch_umin_i32
1225#define tcg_gen_atomic_fetch_smax_tl tcg_gen_atomic_fetch_smax_i32
1226#define tcg_gen_atomic_fetch_umax_tl tcg_gen_atomic_fetch_umax_i32
c482cb11
RH		 1227#define tcg_gen_atomic_add_fetch_tl tcg_gen_atomic_add_fetch_i32
1228#define tcg_gen_atomic_and_fetch_tl tcg_gen_atomic_and_fetch_i32
1229#define tcg_gen_atomic_or_fetch_tl tcg_gen_atomic_or_fetch_i32
1230#define tcg_gen_atomic_xor_fetch_tl tcg_gen_atomic_xor_fetch_i32
5507c2bf
RH		 1231#define tcg_gen_atomic_smin_fetch_tl tcg_gen_atomic_smin_fetch_i32
1232#define tcg_gen_atomic_umin_fetch_tl tcg_gen_atomic_umin_fetch_i32
1233#define tcg_gen_atomic_smax_fetch_tl tcg_gen_atomic_smax_fetch_i32
1234#define tcg_gen_atomic_umax_fetch_tl tcg_gen_atomic_umax_fetch_i32
d2fd745f 1235#define tcg_gen_dup_tl_vec tcg_gen_dup_i32_vec
614dd4f3 1236#define tcg_gen_dup_tl tcg_gen_dup_i32
f8422f52 1237#endif
6ddbc6e4 1238
71b92699 1239#if UINTPTR_MAX == UINT32_MAX
5bfa8034
RH		 1240# define PTR i32
1241# define NAT TCGv_i32
f713d6ad 1242#else
5bfa8034
RH		 1243# define PTR i64
1244# define NAT TCGv_i64
1245#endif
1246
1247static inline void tcg_gen_ld_ptr(TCGv_ptr r, TCGv_ptr a, intptr_t o)
1248{
1249 glue(tcg_gen_ld_,PTR)((NAT)r, a, o);
1250}
1251
c87fb14f
EC		 1252static inline void tcg_gen_st_ptr(TCGv_ptr r, TCGv_ptr a, intptr_t o)
1253{
1254 glue(tcg_gen_st_, PTR)((NAT)r, a, o);
1255}
1256
5bfa8034
RH		 1257static inline void tcg_gen_discard_ptr(TCGv_ptr a)
1258{
1259 glue(tcg_gen_discard_,PTR)((NAT)a);
1260}
1261
1262static inline void tcg_gen_add_ptr(TCGv_ptr r, TCGv_ptr a, TCGv_ptr b)
1263{
1264 glue(tcg_gen_add_,PTR)((NAT)r, (NAT)a, (NAT)b);
1265}
1266
1267static inline void tcg_gen_addi_ptr(TCGv_ptr r, TCGv_ptr a, intptr_t b)
1268{
1269 glue(tcg_gen_addi_,PTR)((NAT)r, (NAT)a, b);
1270}
1271
dc24c991
RH		 1272static inline void tcg_gen_mov_ptr(TCGv_ptr d, TCGv_ptr s)
1273{
1274 glue(tcg_gen_mov_,PTR)((NAT)d, (NAT)s);
1275}
1276
94586f73
RH		 1277static inline void tcg_gen_movi_ptr(TCGv_ptr d, intptr_t s)
1278{
1279 glue(tcg_gen_movi_,PTR)((NAT)d, s);
1280}
1281
5bfa8034
RH		 1282static inline void tcg_gen_brcondi_ptr(TCGCond cond, TCGv_ptr a,
1283 intptr_t b, TCGLabel *label)
1284{
1285 glue(tcg_gen_brcondi_,PTR)(cond, (NAT)a, b, label);
1286}
1287
1288static inline void tcg_gen_ext_i32_ptr(TCGv_ptr r, TCGv_i32 a)
1289{
1290#if UINTPTR_MAX == UINT32_MAX
1291 tcg_gen_mov_i32((NAT)r, a);
1292#else
1293 tcg_gen_ext_i32_i64((NAT)r, a);
1294#endif
1295}
1296
1297static inline void tcg_gen_trunc_i64_ptr(TCGv_ptr r, TCGv_i64 a)
1298{
1299#if UINTPTR_MAX == UINT32_MAX
1300 tcg_gen_extrl_i64_i32((NAT)r, a);
1301#else
1302 tcg_gen_mov_i64((NAT)r, a);
1303#endif
1304}
1305
1306static inline void tcg_gen_extu_ptr_i64(TCGv_i64 r, TCGv_ptr a)
1307{
1308#if UINTPTR_MAX == UINT32_MAX
1309 tcg_gen_extu_i32_i64(r, (NAT)a);
1310#else
1311 tcg_gen_mov_i64(r, (NAT)a);
1312#endif
1313}
1314
1315static inline void tcg_gen_trunc_ptr_i32(TCGv_i32 r, TCGv_ptr a)
1316{
1317#if UINTPTR_MAX == UINT32_MAX
1318 tcg_gen_mov_i32(r, (NAT)a);
1319#else
1320 tcg_gen_extrl_i64_i32(r, (NAT)a);
1321#endif
1322}
1323
1324#undef PTR
1325#undef NAT
a7ce790a
PM		 1326
1327#endif /* TCG_TCG_OP_H */
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