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c896fe29 FB |
1 | /* |
2 | * Tiny Code Generator for QEMU | |
3 | * | |
4 | * Copyright (c) 2008 Fabrice Bellard | |
5 | * | |
6 | * Permission is hereby granted, free of charge, to any person obtaining a copy | |
7 | * of this software and associated documentation files (the "Software"), to deal | |
8 | * in the Software without restriction, including without limitation the rights | |
9 | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell | |
10 | * copies of the Software, and to permit persons to whom the Software is | |
11 | * furnished to do so, subject to the following conditions: | |
12 | * | |
13 | * The above copyright notice and this permission notice shall be included in | |
14 | * all copies or substantial portions of the Software. | |
15 | * | |
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
19 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
20 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, | |
21 | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN | |
22 | * THE SOFTWARE. | |
23 | */ | |
c61aaf7a AJ |
24 | |
25 | /* | |
26 | * DEF(name, oargs, iargs, cargs, flags) | |
27 | */ | |
c896fe29 FB |
28 | |
29 | /* predefined ops */ | |
c1a61f6c RH |
30 | DEF(discard, 1, 0, 0, TCG_OPF_NOT_PRESENT) |
31 | DEF(set_label, 0, 0, 1, TCG_OPF_BB_END | TCG_OPF_NOT_PRESENT) | |
32 | ||
33 | /* variable number of parameters */ | |
96d0ee7f | 34 | DEF(call, 0, 0, 3, TCG_OPF_CALL_CLOBBER | TCG_OPF_NOT_PRESENT) |
5ff9d6a4 | 35 | |
344028ba | 36 | DEF(br, 0, 0, 1, TCG_OPF_BB_END) |
c896fe29 | 37 | |
25c012b4 | 38 | #define IMPL(X) (__builtin_constant_p(X) && (X) <= 0 ? TCG_OPF_NOT_PRESENT : 0) |
25c4d9cc RH |
39 | #if TCG_TARGET_REG_BITS == 32 |
40 | # define IMPL64 TCG_OPF_64BIT | TCG_OPF_NOT_PRESENT | |
41 | #else | |
42 | # define IMPL64 TCG_OPF_64BIT | |
43 | #endif | |
44 | ||
f65e19bc PK |
45 | DEF(mb, 0, 0, 1, 0) |
46 | ||
96d0ee7f | 47 | DEF(mov_i32, 1, 1, 0, TCG_OPF_NOT_PRESENT) |
c61aaf7a | 48 | DEF(setcond_i32, 1, 2, 1, 0) |
ffc5ea09 | 49 | DEF(movcond_i32, 1, 4, 1, IMPL(TCG_TARGET_HAS_movcond_i32)) |
c896fe29 | 50 | /* load/store */ |
c61aaf7a AJ |
51 | DEF(ld8u_i32, 1, 1, 1, 0) |
52 | DEF(ld8s_i32, 1, 1, 1, 0) | |
53 | DEF(ld16u_i32, 1, 1, 1, 0) | |
54 | DEF(ld16s_i32, 1, 1, 1, 0) | |
55 | DEF(ld_i32, 1, 1, 1, 0) | |
b202d41e AJ |
56 | DEF(st8_i32, 0, 2, 1, 0) |
57 | DEF(st16_i32, 0, 2, 1, 0) | |
58 | DEF(st_i32, 0, 2, 1, 0) | |
c896fe29 | 59 | /* arith */ |
c61aaf7a AJ |
60 | DEF(add_i32, 1, 2, 0, 0) |
61 | DEF(sub_i32, 1, 2, 0, 0) | |
62 | DEF(mul_i32, 1, 2, 0, 0) | |
25c4d9cc RH |
63 | DEF(div_i32, 1, 2, 0, IMPL(TCG_TARGET_HAS_div_i32)) |
64 | DEF(divu_i32, 1, 2, 0, IMPL(TCG_TARGET_HAS_div_i32)) | |
ca675f46 RH |
65 | DEF(rem_i32, 1, 2, 0, IMPL(TCG_TARGET_HAS_rem_i32)) |
66 | DEF(remu_i32, 1, 2, 0, IMPL(TCG_TARGET_HAS_rem_i32)) | |
25c4d9cc RH |
67 | DEF(div2_i32, 2, 3, 0, IMPL(TCG_TARGET_HAS_div2_i32)) |
68 | DEF(divu2_i32, 2, 3, 0, IMPL(TCG_TARGET_HAS_div2_i32)) | |
c61aaf7a AJ |
69 | DEF(and_i32, 1, 2, 0, 0) |
70 | DEF(or_i32, 1, 2, 0, 0) | |
71 | DEF(xor_i32, 1, 2, 0, 0) | |
d42f183c | 72 | /* shifts/rotates */ |
c61aaf7a AJ |
73 | DEF(shl_i32, 1, 2, 0, 0) |
74 | DEF(shr_i32, 1, 2, 0, 0) | |
75 | DEF(sar_i32, 1, 2, 0, 0) | |
25c4d9cc RH |
76 | DEF(rotl_i32, 1, 2, 0, IMPL(TCG_TARGET_HAS_rot_i32)) |
77 | DEF(rotr_i32, 1, 2, 0, IMPL(TCG_TARGET_HAS_rot_i32)) | |
78 | DEF(deposit_i32, 1, 2, 2, IMPL(TCG_TARGET_HAS_deposit_i32)) | |
7ec8bab3 RH |
79 | DEF(extract_i32, 1, 1, 2, IMPL(TCG_TARGET_HAS_extract_i32)) |
80 | DEF(sextract_i32, 1, 1, 2, IMPL(TCG_TARGET_HAS_sextract_i32)) | |
fce1296f | 81 | DEF(extract2_i32, 1, 2, 1, IMPL(TCG_TARGET_HAS_extract2_i32)) |
c896fe29 | 82 | |
b4cb76e6 | 83 | DEF(brcond_i32, 0, 2, 2, TCG_OPF_BB_END | TCG_OPF_COND_BRANCH) |
c896fe29 | 84 | |
e6a72734 RH |
85 | DEF(add2_i32, 2, 4, 0, IMPL(TCG_TARGET_HAS_add2_i32)) |
86 | DEF(sub2_i32, 2, 4, 0, IMPL(TCG_TARGET_HAS_sub2_i32)) | |
87 | DEF(mulu2_i32, 2, 2, 0, IMPL(TCG_TARGET_HAS_mulu2_i32)) | |
4d3203fd | 88 | DEF(muls2_i32, 2, 2, 0, IMPL(TCG_TARGET_HAS_muls2_i32)) |
03271524 RH |
89 | DEF(muluh_i32, 1, 2, 0, IMPL(TCG_TARGET_HAS_muluh_i32)) |
90 | DEF(mulsh_i32, 1, 2, 0, IMPL(TCG_TARGET_HAS_mulsh_i32)) | |
b4cb76e6 RH |
91 | DEF(brcond2_i32, 0, 4, 2, |
92 | TCG_OPF_BB_END | TCG_OPF_COND_BRANCH | IMPL(TCG_TARGET_REG_BITS == 32)) | |
25c4d9cc RH |
93 | DEF(setcond2_i32, 1, 4, 1, IMPL(TCG_TARGET_REG_BITS == 32)) |
94 | ||
95 | DEF(ext8s_i32, 1, 1, 0, IMPL(TCG_TARGET_HAS_ext8s_i32)) | |
96 | DEF(ext16s_i32, 1, 1, 0, IMPL(TCG_TARGET_HAS_ext16s_i32)) | |
97 | DEF(ext8u_i32, 1, 1, 0, IMPL(TCG_TARGET_HAS_ext8u_i32)) | |
98 | DEF(ext16u_i32, 1, 1, 0, IMPL(TCG_TARGET_HAS_ext16u_i32)) | |
587195bd RH |
99 | DEF(bswap16_i32, 1, 1, 1, IMPL(TCG_TARGET_HAS_bswap16_i32)) |
100 | DEF(bswap32_i32, 1, 1, 1, IMPL(TCG_TARGET_HAS_bswap32_i32)) | |
25c4d9cc RH |
101 | DEF(not_i32, 1, 1, 0, IMPL(TCG_TARGET_HAS_not_i32)) |
102 | DEF(neg_i32, 1, 1, 0, IMPL(TCG_TARGET_HAS_neg_i32)) | |
103 | DEF(andc_i32, 1, 2, 0, IMPL(TCG_TARGET_HAS_andc_i32)) | |
104 | DEF(orc_i32, 1, 2, 0, IMPL(TCG_TARGET_HAS_orc_i32)) | |
105 | DEF(eqv_i32, 1, 2, 0, IMPL(TCG_TARGET_HAS_eqv_i32)) | |
106 | DEF(nand_i32, 1, 2, 0, IMPL(TCG_TARGET_HAS_nand_i32)) | |
107 | DEF(nor_i32, 1, 2, 0, IMPL(TCG_TARGET_HAS_nor_i32)) | |
0e28d006 RH |
108 | DEF(clz_i32, 1, 2, 0, IMPL(TCG_TARGET_HAS_clz_i32)) |
109 | DEF(ctz_i32, 1, 2, 0, IMPL(TCG_TARGET_HAS_ctz_i32)) | |
a768e4e9 | 110 | DEF(ctpop_i32, 1, 1, 0, IMPL(TCG_TARGET_HAS_ctpop_i32)) |
25c4d9cc | 111 | |
96d0ee7f | 112 | DEF(mov_i64, 1, 1, 0, TCG_OPF_64BIT | TCG_OPF_NOT_PRESENT) |
25c4d9cc | 113 | DEF(setcond_i64, 1, 2, 1, IMPL64) |
ffc5ea09 | 114 | DEF(movcond_i64, 1, 4, 1, IMPL64 | IMPL(TCG_TARGET_HAS_movcond_i64)) |
c896fe29 | 115 | /* load/store */ |
25c4d9cc RH |
116 | DEF(ld8u_i64, 1, 1, 1, IMPL64) |
117 | DEF(ld8s_i64, 1, 1, 1, IMPL64) | |
118 | DEF(ld16u_i64, 1, 1, 1, IMPL64) | |
119 | DEF(ld16s_i64, 1, 1, 1, IMPL64) | |
120 | DEF(ld32u_i64, 1, 1, 1, IMPL64) | |
121 | DEF(ld32s_i64, 1, 1, 1, IMPL64) | |
122 | DEF(ld_i64, 1, 1, 1, IMPL64) | |
b202d41e AJ |
123 | DEF(st8_i64, 0, 2, 1, IMPL64) |
124 | DEF(st16_i64, 0, 2, 1, IMPL64) | |
125 | DEF(st32_i64, 0, 2, 1, IMPL64) | |
126 | DEF(st_i64, 0, 2, 1, IMPL64) | |
c896fe29 | 127 | /* arith */ |
25c4d9cc RH |
128 | DEF(add_i64, 1, 2, 0, IMPL64) |
129 | DEF(sub_i64, 1, 2, 0, IMPL64) | |
130 | DEF(mul_i64, 1, 2, 0, IMPL64) | |
131 | DEF(div_i64, 1, 2, 0, IMPL64 | IMPL(TCG_TARGET_HAS_div_i64)) | |
132 | DEF(divu_i64, 1, 2, 0, IMPL64 | IMPL(TCG_TARGET_HAS_div_i64)) | |
ca675f46 RH |
133 | DEF(rem_i64, 1, 2, 0, IMPL64 | IMPL(TCG_TARGET_HAS_rem_i64)) |
134 | DEF(remu_i64, 1, 2, 0, IMPL64 | IMPL(TCG_TARGET_HAS_rem_i64)) | |
25c4d9cc RH |
135 | DEF(div2_i64, 2, 3, 0, IMPL64 | IMPL(TCG_TARGET_HAS_div2_i64)) |
136 | DEF(divu2_i64, 2, 3, 0, IMPL64 | IMPL(TCG_TARGET_HAS_div2_i64)) | |
137 | DEF(and_i64, 1, 2, 0, IMPL64) | |
138 | DEF(or_i64, 1, 2, 0, IMPL64) | |
139 | DEF(xor_i64, 1, 2, 0, IMPL64) | |
d42f183c | 140 | /* shifts/rotates */ |
25c4d9cc RH |
141 | DEF(shl_i64, 1, 2, 0, IMPL64) |
142 | DEF(shr_i64, 1, 2, 0, IMPL64) | |
143 | DEF(sar_i64, 1, 2, 0, IMPL64) | |
144 | DEF(rotl_i64, 1, 2, 0, IMPL64 | IMPL(TCG_TARGET_HAS_rot_i64)) | |
145 | DEF(rotr_i64, 1, 2, 0, IMPL64 | IMPL(TCG_TARGET_HAS_rot_i64)) | |
146 | DEF(deposit_i64, 1, 2, 2, IMPL64 | IMPL(TCG_TARGET_HAS_deposit_i64)) | |
7ec8bab3 RH |
147 | DEF(extract_i64, 1, 1, 2, IMPL64 | IMPL(TCG_TARGET_HAS_extract_i64)) |
148 | DEF(sextract_i64, 1, 1, 2, IMPL64 | IMPL(TCG_TARGET_HAS_sextract_i64)) | |
fce1296f | 149 | DEF(extract2_i64, 1, 2, 1, IMPL64 | IMPL(TCG_TARGET_HAS_extract2_i64)) |
c896fe29 | 150 | |
4f2331e5 AJ |
151 | /* size changing ops */ |
152 | DEF(ext_i32_i64, 1, 1, 0, IMPL64) | |
153 | DEF(extu_i32_i64, 1, 1, 0, IMPL64) | |
609ad705 RH |
154 | DEF(extrl_i64_i32, 1, 1, 0, |
155 | IMPL(TCG_TARGET_HAS_extrl_i64_i32) | |
156 | | (TCG_TARGET_REG_BITS == 32 ? TCG_OPF_NOT_PRESENT : 0)) | |
157 | DEF(extrh_i64_i32, 1, 1, 0, | |
158 | IMPL(TCG_TARGET_HAS_extrh_i64_i32) | |
4bb7a41e RH |
159 | | (TCG_TARGET_REG_BITS == 32 ? TCG_OPF_NOT_PRESENT : 0)) |
160 | ||
b4cb76e6 | 161 | DEF(brcond_i64, 0, 2, 2, TCG_OPF_BB_END | TCG_OPF_COND_BRANCH | IMPL64) |
25c4d9cc RH |
162 | DEF(ext8s_i64, 1, 1, 0, IMPL64 | IMPL(TCG_TARGET_HAS_ext8s_i64)) |
163 | DEF(ext16s_i64, 1, 1, 0, IMPL64 | IMPL(TCG_TARGET_HAS_ext16s_i64)) | |
164 | DEF(ext32s_i64, 1, 1, 0, IMPL64 | IMPL(TCG_TARGET_HAS_ext32s_i64)) | |
165 | DEF(ext8u_i64, 1, 1, 0, IMPL64 | IMPL(TCG_TARGET_HAS_ext8u_i64)) | |
166 | DEF(ext16u_i64, 1, 1, 0, IMPL64 | IMPL(TCG_TARGET_HAS_ext16u_i64)) | |
167 | DEF(ext32u_i64, 1, 1, 0, IMPL64 | IMPL(TCG_TARGET_HAS_ext32u_i64)) | |
587195bd RH |
168 | DEF(bswap16_i64, 1, 1, 1, IMPL64 | IMPL(TCG_TARGET_HAS_bswap16_i64)) |
169 | DEF(bswap32_i64, 1, 1, 1, IMPL64 | IMPL(TCG_TARGET_HAS_bswap32_i64)) | |
170 | DEF(bswap64_i64, 1, 1, 1, IMPL64 | IMPL(TCG_TARGET_HAS_bswap64_i64)) | |
25c4d9cc RH |
171 | DEF(not_i64, 1, 1, 0, IMPL64 | IMPL(TCG_TARGET_HAS_not_i64)) |
172 | DEF(neg_i64, 1, 1, 0, IMPL64 | IMPL(TCG_TARGET_HAS_neg_i64)) | |
173 | DEF(andc_i64, 1, 2, 0, IMPL64 | IMPL(TCG_TARGET_HAS_andc_i64)) | |
174 | DEF(orc_i64, 1, 2, 0, IMPL64 | IMPL(TCG_TARGET_HAS_orc_i64)) | |
175 | DEF(eqv_i64, 1, 2, 0, IMPL64 | IMPL(TCG_TARGET_HAS_eqv_i64)) | |
176 | DEF(nand_i64, 1, 2, 0, IMPL64 | IMPL(TCG_TARGET_HAS_nand_i64)) | |
177 | DEF(nor_i64, 1, 2, 0, IMPL64 | IMPL(TCG_TARGET_HAS_nor_i64)) | |
0e28d006 RH |
178 | DEF(clz_i64, 1, 2, 0, IMPL64 | IMPL(TCG_TARGET_HAS_clz_i64)) |
179 | DEF(ctz_i64, 1, 2, 0, IMPL64 | IMPL(TCG_TARGET_HAS_ctz_i64)) | |
a768e4e9 | 180 | DEF(ctpop_i64, 1, 1, 0, IMPL64 | IMPL(TCG_TARGET_HAS_ctpop_i64)) |
c896fe29 | 181 | |
d7156f7c RH |
182 | DEF(add2_i64, 2, 4, 0, IMPL64 | IMPL(TCG_TARGET_HAS_add2_i64)) |
183 | DEF(sub2_i64, 2, 4, 0, IMPL64 | IMPL(TCG_TARGET_HAS_sub2_i64)) | |
184 | DEF(mulu2_i64, 2, 2, 0, IMPL64 | IMPL(TCG_TARGET_HAS_mulu2_i64)) | |
4d3203fd | 185 | DEF(muls2_i64, 2, 2, 0, IMPL64 | IMPL(TCG_TARGET_HAS_muls2_i64)) |
f2f1dde7 RH |
186 | DEF(muluh_i64, 1, 2, 0, IMPL64 | IMPL(TCG_TARGET_HAS_muluh_i64)) |
187 | DEF(mulsh_i64, 1, 2, 0, IMPL64 | IMPL(TCG_TARGET_HAS_mulsh_i64)) | |
d7156f7c | 188 | |
c0e40dbd JH |
189 | #define TLADDR_ARGS (TARGET_LONG_BITS <= TCG_TARGET_REG_BITS ? 1 : 2) |
190 | #define DATA64_ARGS (TCG_TARGET_REG_BITS == 64 ? 1 : 2) | |
191 | ||
c896fe29 | 192 | /* QEMU specific */ |
c0e40dbd JH |
193 | DEF(insn_start, 0, 0, TLADDR_ARGS * TARGET_INSN_START_WORDS, |
194 | TCG_OPF_NOT_PRESENT) | |
ae36a246 RH |
195 | DEF(exit_tb, 0, 0, 1, TCG_OPF_BB_EXIT | TCG_OPF_BB_END) |
196 | DEF(goto_tb, 0, 0, 1, TCG_OPF_BB_EXIT | TCG_OPF_BB_END) | |
f4e01e30 | 197 | DEF(goto_ptr, 0, 1, 0, TCG_OPF_BB_EXIT | TCG_OPF_BB_END) |
f713d6ad | 198 | |
38b47b19 EC |
199 | DEF(plugin_cb_start, 0, 0, 3, TCG_OPF_NOT_PRESENT) |
200 | DEF(plugin_cb_end, 0, 0, 0, TCG_OPF_NOT_PRESENT) | |
201 | ||
59227d5d | 202 | DEF(qemu_ld_i32, 1, TLADDR_ARGS, 1, |
3d1b2ff6 | 203 | TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS) |
59227d5d | 204 | DEF(qemu_st_i32, 0, TLADDR_ARGS + 1, 1, |
3d1b2ff6 | 205 | TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS) |
59227d5d | 206 | DEF(qemu_ld_i64, DATA64_ARGS, TLADDR_ARGS, 1, |
3d1b2ff6 | 207 | TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS | TCG_OPF_64BIT) |
59227d5d | 208 | DEF(qemu_st_i64, 0, TLADDR_ARGS + DATA64_ARGS, 1, |
3d1b2ff6 RH |
209 | TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS | TCG_OPF_64BIT) |
210 | ||
07ce0b05 RH |
211 | /* Only used by i386 to cope with stupid register constraints. */ |
212 | DEF(qemu_st8_i32, 0, TLADDR_ARGS + 1, 1, | |
213 | TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS | | |
214 | IMPL(TCG_TARGET_HAS_qemu_st8_i32)) | |
215 | ||
d2fd745f RH |
216 | /* Host vector support. */ |
217 | ||
218 | #define IMPLVEC TCG_OPF_VECTOR | IMPL(TCG_TARGET_MAYBE_vec) | |
219 | ||
220 | DEF(mov_vec, 1, 1, 0, TCG_OPF_VECTOR | TCG_OPF_NOT_PRESENT) | |
d2fd745f RH |
221 | |
222 | DEF(dup_vec, 1, 1, 0, IMPLVEC) | |
223 | DEF(dup2_vec, 1, 2, 0, IMPLVEC | IMPL(TCG_TARGET_REG_BITS == 32)) | |
224 | ||
225 | DEF(ld_vec, 1, 1, 1, IMPLVEC) | |
226 | DEF(st_vec, 0, 2, 1, IMPLVEC) | |
37ee55a0 | 227 | DEF(dupm_vec, 1, 1, 1, IMPLVEC) |
d2fd745f RH |
228 | |
229 | DEF(add_vec, 1, 2, 0, IMPLVEC) | |
230 | DEF(sub_vec, 1, 2, 0, IMPLVEC) | |
3774030a | 231 | DEF(mul_vec, 1, 2, 0, IMPLVEC | IMPL(TCG_TARGET_HAS_mul_vec)) |
d2fd745f | 232 | DEF(neg_vec, 1, 1, 0, IMPLVEC | IMPL(TCG_TARGET_HAS_neg_vec)) |
bcefc902 | 233 | DEF(abs_vec, 1, 1, 0, IMPLVEC | IMPL(TCG_TARGET_HAS_abs_vec)) |
8afaf050 RH |
234 | DEF(ssadd_vec, 1, 2, 0, IMPLVEC | IMPL(TCG_TARGET_HAS_sat_vec)) |
235 | DEF(usadd_vec, 1, 2, 0, IMPLVEC | IMPL(TCG_TARGET_HAS_sat_vec)) | |
236 | DEF(sssub_vec, 1, 2, 0, IMPLVEC | IMPL(TCG_TARGET_HAS_sat_vec)) | |
237 | DEF(ussub_vec, 1, 2, 0, IMPLVEC | IMPL(TCG_TARGET_HAS_sat_vec)) | |
dd0a0fcd RH |
238 | DEF(smin_vec, 1, 2, 0, IMPLVEC | IMPL(TCG_TARGET_HAS_minmax_vec)) |
239 | DEF(umin_vec, 1, 2, 0, IMPLVEC | IMPL(TCG_TARGET_HAS_minmax_vec)) | |
240 | DEF(smax_vec, 1, 2, 0, IMPLVEC | IMPL(TCG_TARGET_HAS_minmax_vec)) | |
241 | DEF(umax_vec, 1, 2, 0, IMPLVEC | IMPL(TCG_TARGET_HAS_minmax_vec)) | |
d2fd745f RH |
242 | |
243 | DEF(and_vec, 1, 2, 0, IMPLVEC) | |
244 | DEF(or_vec, 1, 2, 0, IMPLVEC) | |
245 | DEF(xor_vec, 1, 2, 0, IMPLVEC) | |
246 | DEF(andc_vec, 1, 2, 0, IMPLVEC | IMPL(TCG_TARGET_HAS_andc_vec)) | |
247 | DEF(orc_vec, 1, 2, 0, IMPLVEC | IMPL(TCG_TARGET_HAS_orc_vec)) | |
ed523473 RH |
248 | DEF(nand_vec, 1, 2, 0, IMPLVEC | IMPL(TCG_TARGET_HAS_nand_vec)) |
249 | DEF(nor_vec, 1, 2, 0, IMPLVEC | IMPL(TCG_TARGET_HAS_nor_vec)) | |
250 | DEF(eqv_vec, 1, 2, 0, IMPLVEC | IMPL(TCG_TARGET_HAS_eqv_vec)) | |
d2fd745f RH |
251 | DEF(not_vec, 1, 1, 0, IMPLVEC | IMPL(TCG_TARGET_HAS_not_vec)) |
252 | ||
d0ec9796 RH |
253 | DEF(shli_vec, 1, 1, 1, IMPLVEC | IMPL(TCG_TARGET_HAS_shi_vec)) |
254 | DEF(shri_vec, 1, 1, 1, IMPLVEC | IMPL(TCG_TARGET_HAS_shi_vec)) | |
255 | DEF(sari_vec, 1, 1, 1, IMPLVEC | IMPL(TCG_TARGET_HAS_shi_vec)) | |
b0f7e744 | 256 | DEF(rotli_vec, 1, 1, 1, IMPLVEC | IMPL(TCG_TARGET_HAS_roti_vec)) |
d0ec9796 RH |
257 | |
258 | DEF(shls_vec, 1, 2, 0, IMPLVEC | IMPL(TCG_TARGET_HAS_shs_vec)) | |
259 | DEF(shrs_vec, 1, 2, 0, IMPLVEC | IMPL(TCG_TARGET_HAS_shs_vec)) | |
260 | DEF(sars_vec, 1, 2, 0, IMPLVEC | IMPL(TCG_TARGET_HAS_shs_vec)) | |
23850a74 | 261 | DEF(rotls_vec, 1, 2, 0, IMPLVEC | IMPL(TCG_TARGET_HAS_rots_vec)) |
d0ec9796 RH |
262 | |
263 | DEF(shlv_vec, 1, 2, 0, IMPLVEC | IMPL(TCG_TARGET_HAS_shv_vec)) | |
264 | DEF(shrv_vec, 1, 2, 0, IMPLVEC | IMPL(TCG_TARGET_HAS_shv_vec)) | |
265 | DEF(sarv_vec, 1, 2, 0, IMPLVEC | IMPL(TCG_TARGET_HAS_shv_vec)) | |
5d0ceda9 RH |
266 | DEF(rotlv_vec, 1, 2, 0, IMPLVEC | IMPL(TCG_TARGET_HAS_rotv_vec)) |
267 | DEF(rotrv_vec, 1, 2, 0, IMPLVEC | IMPL(TCG_TARGET_HAS_rotv_vec)) | |
d0ec9796 | 268 | |
212be173 RH |
269 | DEF(cmp_vec, 1, 2, 1, IMPLVEC) |
270 | ||
38dc1294 | 271 | DEF(bitsel_vec, 1, 3, 0, IMPLVEC | IMPL(TCG_TARGET_HAS_bitsel_vec)) |
f75da298 | 272 | DEF(cmpsel_vec, 1, 4, 1, IMPLVEC | IMPL(TCG_TARGET_HAS_cmpsel_vec)) |
38dc1294 | 273 | |
db432672 RH |
274 | DEF(last_generic, 0, 0, 0, TCG_OPF_NOT_PRESENT) |
275 | ||
276 | #if TCG_TARGET_MAYBE_vec | |
277 | #include "tcg-target.opc.h" | |
278 | #endif | |
279 | ||
1bd1af98 RH |
280 | #ifdef TCG_TARGET_INTERPRETER |
281 | /* These opcodes are only for use between the tci generator and interpreter. */ | |
65089889 RH |
282 | DEF(tci_movi, 1, 0, 1, TCG_OPF_NOT_PRESENT) |
283 | DEF(tci_movl, 1, 0, 1, TCG_OPF_NOT_PRESENT) | |
1bd1af98 | 284 | #endif |
1bd1af98 | 285 | |
3d1b2ff6 RH |
286 | #undef TLADDR_ARGS |
287 | #undef DATA64_ARGS | |
25c4d9cc RH |
288 | #undef IMPL |
289 | #undef IMPL64 | |
d2fd745f | 290 | #undef IMPLVEC |
c61aaf7a | 291 | #undef DEF |