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c896fe29 FB |
1 | /* |
2 | * Tiny Code Generator for QEMU | |
3 | * | |
4 | * Copyright (c) 2008 Fabrice Bellard | |
5 | * | |
6 | * Permission is hereby granted, free of charge, to any person obtaining a copy | |
7 | * of this software and associated documentation files (the "Software"), to deal | |
8 | * in the Software without restriction, including without limitation the rights | |
9 | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell | |
10 | * copies of the Software, and to permit persons to whom the Software is | |
11 | * furnished to do so, subject to the following conditions: | |
12 | * | |
13 | * The above copyright notice and this permission notice shall be included in | |
14 | * all copies or substantial portions of the Software. | |
15 | * | |
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
19 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
20 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, | |
21 | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN | |
22 | * THE SOFTWARE. | |
23 | */ | |
e58eb534 RH |
24 | |
25 | #ifndef TCG_H | |
26 | #define TCG_H | |
27 | ||
33c11879 | 28 | #include "cpu.h" |
14776ab5 | 29 | #include "exec/memop.h" |
abe2e23e | 30 | #include "exec/memopidx.h" |
0ec9eabc | 31 | #include "qemu/bitops.h" |
e6d86bed | 32 | #include "qemu/plugin.h" |
15fa08f8 | 33 | #include "qemu/queue.h" |
dcb32f1d | 34 | #include "tcg/tcg-mo.h" |
78cd7b83 | 35 | #include "tcg-target.h" |
e6cd4bb5 | 36 | #include "qemu/int128.h" |
9ca03622 | 37 | #include "tcg/tcg-cond.h" |
78cd7b83 | 38 | |
00f6da6a PB |
39 | /* XXX: make safe guess about sizes */ |
40 | #define MAX_OP_PER_INSTR 266 | |
41 | ||
42 | #if HOST_LONG_BITS == 32 | |
43 | #define MAX_OPC_PARAM_PER_ARG 2 | |
44 | #else | |
45 | #define MAX_OPC_PARAM_PER_ARG 1 | |
46 | #endif | |
1df3caa9 | 47 | #define MAX_OPC_PARAM_IARGS 6 |
00f6da6a PB |
48 | #define MAX_OPC_PARAM_OARGS 1 |
49 | #define MAX_OPC_PARAM_ARGS (MAX_OPC_PARAM_IARGS + MAX_OPC_PARAM_OARGS) | |
50 | ||
51 | /* A Call op needs up to 4 + 2N parameters on 32-bit archs, | |
52 | * and up to 4 + N parameters on 64-bit archs | |
53 | * (N = number of input arguments + output arguments). */ | |
54 | #define MAX_OPC_PARAM (4 + (MAX_OPC_PARAM_PER_ARG * MAX_OPC_PARAM_ARGS)) | |
00f6da6a | 55 | |
6e0b0730 | 56 | #define CPU_TEMP_BUF_NLONGS 128 |
7b7d8b2d | 57 | #define TCG_STATIC_FRAME_SIZE (CPU_TEMP_BUF_NLONGS * sizeof(long)) |
6e0b0730 | 58 | |
78cd7b83 RH |
59 | /* Default target word size to pointer size. */ |
60 | #ifndef TCG_TARGET_REG_BITS | |
61 | # if UINTPTR_MAX == UINT32_MAX | |
62 | # define TCG_TARGET_REG_BITS 32 | |
63 | # elif UINTPTR_MAX == UINT64_MAX | |
64 | # define TCG_TARGET_REG_BITS 64 | |
65 | # else | |
66 | # error Unknown pointer size for tcg target | |
67 | # endif | |
817b838e SW |
68 | #endif |
69 | ||
c896fe29 FB |
70 | #if TCG_TARGET_REG_BITS == 32 |
71 | typedef int32_t tcg_target_long; | |
72 | typedef uint32_t tcg_target_ulong; | |
73 | #define TCG_PRIlx PRIx32 | |
74 | #define TCG_PRIld PRId32 | |
75 | #elif TCG_TARGET_REG_BITS == 64 | |
76 | typedef int64_t tcg_target_long; | |
77 | typedef uint64_t tcg_target_ulong; | |
78 | #define TCG_PRIlx PRIx64 | |
79 | #define TCG_PRIld PRId64 | |
80 | #else | |
81 | #error unsupported | |
82 | #endif | |
83 | ||
8d4e9146 FK |
84 | /* Oversized TCG guests make things like MTTCG hard |
85 | * as we can't use atomics for cputlb updates. | |
86 | */ | |
87 | #if TARGET_LONG_BITS > TCG_TARGET_REG_BITS | |
88 | #define TCG_OVERSIZED_GUEST 1 | |
89 | #else | |
90 | #define TCG_OVERSIZED_GUEST 0 | |
91 | #endif | |
92 | ||
c896fe29 FB |
93 | #if TCG_TARGET_NB_REGS <= 32 |
94 | typedef uint32_t TCGRegSet; | |
95 | #elif TCG_TARGET_NB_REGS <= 64 | |
96 | typedef uint64_t TCGRegSet; | |
97 | #else | |
98 | #error unsupported | |
99 | #endif | |
100 | ||
25c4d9cc | 101 | #if TCG_TARGET_REG_BITS == 32 |
e6a72734 | 102 | /* Turn some undef macros into false macros. */ |
609ad705 RH |
103 | #define TCG_TARGET_HAS_extrl_i64_i32 0 |
104 | #define TCG_TARGET_HAS_extrh_i64_i32 0 | |
25c4d9cc | 105 | #define TCG_TARGET_HAS_div_i64 0 |
ca675f46 | 106 | #define TCG_TARGET_HAS_rem_i64 0 |
25c4d9cc RH |
107 | #define TCG_TARGET_HAS_div2_i64 0 |
108 | #define TCG_TARGET_HAS_rot_i64 0 | |
109 | #define TCG_TARGET_HAS_ext8s_i64 0 | |
110 | #define TCG_TARGET_HAS_ext16s_i64 0 | |
111 | #define TCG_TARGET_HAS_ext32s_i64 0 | |
112 | #define TCG_TARGET_HAS_ext8u_i64 0 | |
113 | #define TCG_TARGET_HAS_ext16u_i64 0 | |
114 | #define TCG_TARGET_HAS_ext32u_i64 0 | |
115 | #define TCG_TARGET_HAS_bswap16_i64 0 | |
116 | #define TCG_TARGET_HAS_bswap32_i64 0 | |
117 | #define TCG_TARGET_HAS_bswap64_i64 0 | |
118 | #define TCG_TARGET_HAS_neg_i64 0 | |
119 | #define TCG_TARGET_HAS_not_i64 0 | |
120 | #define TCG_TARGET_HAS_andc_i64 0 | |
121 | #define TCG_TARGET_HAS_orc_i64 0 | |
122 | #define TCG_TARGET_HAS_eqv_i64 0 | |
123 | #define TCG_TARGET_HAS_nand_i64 0 | |
124 | #define TCG_TARGET_HAS_nor_i64 0 | |
0e28d006 RH |
125 | #define TCG_TARGET_HAS_clz_i64 0 |
126 | #define TCG_TARGET_HAS_ctz_i64 0 | |
a768e4e9 | 127 | #define TCG_TARGET_HAS_ctpop_i64 0 |
25c4d9cc | 128 | #define TCG_TARGET_HAS_deposit_i64 0 |
7ec8bab3 RH |
129 | #define TCG_TARGET_HAS_extract_i64 0 |
130 | #define TCG_TARGET_HAS_sextract_i64 0 | |
fce1296f | 131 | #define TCG_TARGET_HAS_extract2_i64 0 |
ffc5ea09 | 132 | #define TCG_TARGET_HAS_movcond_i64 0 |
d7156f7c RH |
133 | #define TCG_TARGET_HAS_add2_i64 0 |
134 | #define TCG_TARGET_HAS_sub2_i64 0 | |
135 | #define TCG_TARGET_HAS_mulu2_i64 0 | |
4d3203fd | 136 | #define TCG_TARGET_HAS_muls2_i64 0 |
03271524 RH |
137 | #define TCG_TARGET_HAS_muluh_i64 0 |
138 | #define TCG_TARGET_HAS_mulsh_i64 0 | |
e6a72734 RH |
139 | /* Turn some undef macros into true macros. */ |
140 | #define TCG_TARGET_HAS_add2_i32 1 | |
141 | #define TCG_TARGET_HAS_sub2_i32 1 | |
25c4d9cc RH |
142 | #endif |
143 | ||
a4773324 JK |
144 | #ifndef TCG_TARGET_deposit_i32_valid |
145 | #define TCG_TARGET_deposit_i32_valid(ofs, len) 1 | |
146 | #endif | |
147 | #ifndef TCG_TARGET_deposit_i64_valid | |
148 | #define TCG_TARGET_deposit_i64_valid(ofs, len) 1 | |
149 | #endif | |
7ec8bab3 RH |
150 | #ifndef TCG_TARGET_extract_i32_valid |
151 | #define TCG_TARGET_extract_i32_valid(ofs, len) 1 | |
152 | #endif | |
153 | #ifndef TCG_TARGET_extract_i64_valid | |
154 | #define TCG_TARGET_extract_i64_valid(ofs, len) 1 | |
155 | #endif | |
a4773324 | 156 | |
25c4d9cc RH |
157 | /* Only one of DIV or DIV2 should be defined. */ |
158 | #if defined(TCG_TARGET_HAS_div_i32) | |
159 | #define TCG_TARGET_HAS_div2_i32 0 | |
160 | #elif defined(TCG_TARGET_HAS_div2_i32) | |
161 | #define TCG_TARGET_HAS_div_i32 0 | |
ca675f46 | 162 | #define TCG_TARGET_HAS_rem_i32 0 |
25c4d9cc RH |
163 | #endif |
164 | #if defined(TCG_TARGET_HAS_div_i64) | |
165 | #define TCG_TARGET_HAS_div2_i64 0 | |
166 | #elif defined(TCG_TARGET_HAS_div2_i64) | |
167 | #define TCG_TARGET_HAS_div_i64 0 | |
ca675f46 | 168 | #define TCG_TARGET_HAS_rem_i64 0 |
25c4d9cc RH |
169 | #endif |
170 | ||
df9ebea5 RH |
171 | /* For 32-bit targets, some sort of unsigned widening multiply is required. */ |
172 | #if TCG_TARGET_REG_BITS == 32 \ | |
173 | && !(defined(TCG_TARGET_HAS_mulu2_i32) \ | |
174 | || defined(TCG_TARGET_HAS_muluh_i32)) | |
175 | # error "Missing unsigned widening multiply" | |
176 | #endif | |
177 | ||
d2fd745f RH |
178 | #if !defined(TCG_TARGET_HAS_v64) \ |
179 | && !defined(TCG_TARGET_HAS_v128) \ | |
180 | && !defined(TCG_TARGET_HAS_v256) | |
181 | #define TCG_TARGET_MAYBE_vec 0 | |
bcefc902 | 182 | #define TCG_TARGET_HAS_abs_vec 0 |
d2fd745f RH |
183 | #define TCG_TARGET_HAS_neg_vec 0 |
184 | #define TCG_TARGET_HAS_not_vec 0 | |
185 | #define TCG_TARGET_HAS_andc_vec 0 | |
186 | #define TCG_TARGET_HAS_orc_vec 0 | |
b0f7e744 | 187 | #define TCG_TARGET_HAS_roti_vec 0 |
23850a74 | 188 | #define TCG_TARGET_HAS_rots_vec 0 |
5d0ceda9 | 189 | #define TCG_TARGET_HAS_rotv_vec 0 |
d0ec9796 RH |
190 | #define TCG_TARGET_HAS_shi_vec 0 |
191 | #define TCG_TARGET_HAS_shs_vec 0 | |
192 | #define TCG_TARGET_HAS_shv_vec 0 | |
3774030a | 193 | #define TCG_TARGET_HAS_mul_vec 0 |
8afaf050 | 194 | #define TCG_TARGET_HAS_sat_vec 0 |
dd0a0fcd | 195 | #define TCG_TARGET_HAS_minmax_vec 0 |
38dc1294 | 196 | #define TCG_TARGET_HAS_bitsel_vec 0 |
f75da298 | 197 | #define TCG_TARGET_HAS_cmpsel_vec 0 |
d2fd745f RH |
198 | #else |
199 | #define TCG_TARGET_MAYBE_vec 1 | |
200 | #endif | |
201 | #ifndef TCG_TARGET_HAS_v64 | |
202 | #define TCG_TARGET_HAS_v64 0 | |
203 | #endif | |
204 | #ifndef TCG_TARGET_HAS_v128 | |
205 | #define TCG_TARGET_HAS_v128 0 | |
206 | #endif | |
207 | #ifndef TCG_TARGET_HAS_v256 | |
208 | #define TCG_TARGET_HAS_v256 0 | |
209 | #endif | |
210 | ||
9aef40ed RH |
211 | #ifndef TARGET_INSN_START_EXTRA_WORDS |
212 | # define TARGET_INSN_START_WORDS 1 | |
213 | #else | |
214 | # define TARGET_INSN_START_WORDS (1 + TARGET_INSN_START_EXTRA_WORDS) | |
215 | #endif | |
216 | ||
a9751609 | 217 | typedef enum TCGOpcode { |
c61aaf7a | 218 | #define DEF(name, oargs, iargs, cargs, flags) INDEX_op_ ## name, |
dcb32f1d | 219 | #include "tcg/tcg-opc.h" |
c896fe29 FB |
220 | #undef DEF |
221 | NB_OPS, | |
a9751609 | 222 | } TCGOpcode; |
c896fe29 | 223 | |
80a8b9a9 RH |
224 | #define tcg_regset_set_reg(d, r) ((d) |= (TCGRegSet)1 << (r)) |
225 | #define tcg_regset_reset_reg(d, r) ((d) &= ~((TCGRegSet)1 << (r))) | |
226 | #define tcg_regset_test_reg(d, r) (((d) >> (r)) & 1) | |
c896fe29 | 227 | |
1813e175 | 228 | #ifndef TCG_TARGET_INSN_UNIT_SIZE |
5053361b RH |
229 | # error "Missing TCG_TARGET_INSN_UNIT_SIZE" |
230 | #elif TCG_TARGET_INSN_UNIT_SIZE == 1 | |
1813e175 RH |
231 | typedef uint8_t tcg_insn_unit; |
232 | #elif TCG_TARGET_INSN_UNIT_SIZE == 2 | |
233 | typedef uint16_t tcg_insn_unit; | |
234 | #elif TCG_TARGET_INSN_UNIT_SIZE == 4 | |
235 | typedef uint32_t tcg_insn_unit; | |
236 | #elif TCG_TARGET_INSN_UNIT_SIZE == 8 | |
237 | typedef uint64_t tcg_insn_unit; | |
238 | #else | |
239 | /* The port better have done this. */ | |
240 | #endif | |
241 | ||
242 | ||
8bff06a0 | 243 | #if defined CONFIG_DEBUG_TCG || defined QEMU_STATIC_ANALYSIS |
1f00b27f | 244 | # define tcg_debug_assert(X) do { assert(X); } while (0) |
6fa2cef2 | 245 | #else |
1f00b27f SS |
246 | # define tcg_debug_assert(X) \ |
247 | do { if (!(X)) { __builtin_unreachable(); } } while (0) | |
1f00b27f SS |
248 | #endif |
249 | ||
7ecd02a0 RH |
250 | typedef struct TCGRelocation TCGRelocation; |
251 | struct TCGRelocation { | |
252 | QSIMPLEQ_ENTRY(TCGRelocation) next; | |
1813e175 | 253 | tcg_insn_unit *ptr; |
2ba7fae2 | 254 | intptr_t addend; |
7ecd02a0 RH |
255 | int type; |
256 | }; | |
c896fe29 | 257 | |
bef16ab4 RH |
258 | typedef struct TCGLabel TCGLabel; |
259 | struct TCGLabel { | |
260 | unsigned present : 1; | |
51e3972c | 261 | unsigned has_value : 1; |
bef16ab4 | 262 | unsigned id : 14; |
d88a117e | 263 | unsigned refs : 16; |
c896fe29 | 264 | union { |
2ba7fae2 | 265 | uintptr_t value; |
ffd0e507 | 266 | const tcg_insn_unit *value_ptr; |
c896fe29 | 267 | } u; |
7ecd02a0 | 268 | QSIMPLEQ_HEAD(, TCGRelocation) relocs; |
bef16ab4 | 269 | QSIMPLEQ_ENTRY(TCGLabel) next; |
bef16ab4 | 270 | }; |
c896fe29 FB |
271 | |
272 | typedef struct TCGPool { | |
273 | struct TCGPool *next; | |
c44f945a | 274 | int size; |
f7795e40 | 275 | uint8_t data[] __attribute__ ((aligned)); |
c896fe29 FB |
276 | } TCGPool; |
277 | ||
278 | #define TCG_POOL_CHUNK_SIZE 32768 | |
279 | ||
c4071c90 | 280 | #define TCG_MAX_TEMPS 512 |
190ce7fb | 281 | #define TCG_MAX_INSNS 512 |
c896fe29 | 282 | |
b03cce8e FB |
283 | /* when the size of the arguments of a called function is smaller than |
284 | this value, they are statically allocated in the TB stack frame */ | |
285 | #define TCG_STATIC_CALL_ARGS_SIZE 128 | |
286 | ||
c02244a5 RH |
287 | typedef enum TCGType { |
288 | TCG_TYPE_I32, | |
289 | TCG_TYPE_I64, | |
d2fd745f RH |
290 | |
291 | TCG_TYPE_V64, | |
292 | TCG_TYPE_V128, | |
293 | TCG_TYPE_V256, | |
294 | ||
c02244a5 | 295 | TCG_TYPE_COUNT, /* number of different types */ |
c896fe29 | 296 | |
3b6dac34 | 297 | /* An alias for the size of the host register. */ |
c896fe29 | 298 | #if TCG_TARGET_REG_BITS == 32 |
3b6dac34 | 299 | TCG_TYPE_REG = TCG_TYPE_I32, |
c02244a5 | 300 | #else |
3b6dac34 | 301 | TCG_TYPE_REG = TCG_TYPE_I64, |
c02244a5 | 302 | #endif |
3b6dac34 | 303 | |
d289837e RH |
304 | /* An alias for the size of the native pointer. */ |
305 | #if UINTPTR_MAX == UINT32_MAX | |
306 | TCG_TYPE_PTR = TCG_TYPE_I32, | |
307 | #else | |
308 | TCG_TYPE_PTR = TCG_TYPE_I64, | |
309 | #endif | |
3b6dac34 RH |
310 | |
311 | /* An alias for the size of the target "long", aka register. */ | |
c02244a5 RH |
312 | #if TARGET_LONG_BITS == 64 |
313 | TCG_TYPE_TL = TCG_TYPE_I64, | |
c896fe29 | 314 | #else |
c02244a5 | 315 | TCG_TYPE_TL = TCG_TYPE_I32, |
c896fe29 | 316 | #endif |
c02244a5 | 317 | } TCGType; |
c896fe29 | 318 | |
1f00b27f SS |
319 | /** |
320 | * get_alignment_bits | |
14776ab5 | 321 | * @memop: MemOp value |
1f00b27f SS |
322 | * |
323 | * Extract the alignment size from the memop. | |
1f00b27f | 324 | */ |
14776ab5 | 325 | static inline unsigned get_alignment_bits(MemOp memop) |
1f00b27f | 326 | { |
85aa8081 | 327 | unsigned a = memop & MO_AMASK; |
1f00b27f SS |
328 | |
329 | if (a == MO_UNALN) { | |
85aa8081 RH |
330 | /* No alignment required. */ |
331 | a = 0; | |
1f00b27f | 332 | } else if (a == MO_ALIGN) { |
85aa8081 RH |
333 | /* A natural alignment requirement. */ |
334 | a = memop & MO_SIZE; | |
1f00b27f | 335 | } else { |
85aa8081 RH |
336 | /* A specific alignment requirement. */ |
337 | a = a >> MO_ASHIFT; | |
1f00b27f SS |
338 | } |
339 | #if defined(CONFIG_SOFTMMU) | |
340 | /* The requested alignment cannot overlap the TLB flags. */ | |
85aa8081 | 341 | tcg_debug_assert((TLB_FLAGS_MASK & ((1 << a) - 1)) == 0); |
1f00b27f | 342 | #endif |
85aa8081 | 343 | return a; |
1f00b27f SS |
344 | } |
345 | ||
c896fe29 FB |
346 | typedef tcg_target_ulong TCGArg; |
347 | ||
a40d4701 PM |
348 | /* Define type and accessor macros for TCG variables. |
349 | ||
350 | TCG variables are the inputs and outputs of TCG ops, as described | |
351 | in tcg/README. Target CPU front-end code uses these types to deal | |
352 | with TCG variables as it emits TCG code via the tcg_gen_* functions. | |
353 | They come in several flavours: | |
354 | * TCGv_i32 : 32 bit integer type | |
355 | * TCGv_i64 : 64 bit integer type | |
356 | * TCGv_ptr : a host pointer type | |
d2fd745f RH |
357 | * TCGv_vec : a host vector type; the exact size is not exposed |
358 | to the CPU front-end code. | |
a40d4701 PM |
359 | * TCGv : an integer type the same size as target_ulong |
360 | (an alias for either TCGv_i32 or TCGv_i64) | |
361 | The compiler's type checking will complain if you mix them | |
362 | up and pass the wrong sized TCGv to a function. | |
363 | ||
364 | Users of tcg_gen_* don't need to know about any of the internal | |
365 | details of these, and should treat them as opaque types. | |
366 | You won't be able to look inside them in a debugger either. | |
367 | ||
368 | Internal implementation details follow: | |
369 | ||
370 | Note that there is no definition of the structs TCGv_i32_d etc anywhere. | |
371 | This is deliberate, because the values we store in variables of type | |
372 | TCGv_i32 are not really pointers-to-structures. They're just small | |
373 | integers, but keeping them in pointer types like this means that the | |
374 | compiler will complain if you accidentally pass a TCGv_i32 to a | |
375 | function which takes a TCGv_i64, and so on. Only the internals of | |
dc41aa7d | 376 | TCG need to care about the actual contents of the types. */ |
ac56dd48 | 377 | |
b6c73a6d RH |
378 | typedef struct TCGv_i32_d *TCGv_i32; |
379 | typedef struct TCGv_i64_d *TCGv_i64; | |
380 | typedef struct TCGv_ptr_d *TCGv_ptr; | |
d2fd745f | 381 | typedef struct TCGv_vec_d *TCGv_vec; |
1bcea73e | 382 | typedef TCGv_ptr TCGv_env; |
5d4e1a10 LV |
383 | #if TARGET_LONG_BITS == 32 |
384 | #define TCGv TCGv_i32 | |
385 | #elif TARGET_LONG_BITS == 64 | |
386 | #define TCGv TCGv_i64 | |
387 | #else | |
388 | #error Unhandled TARGET_LONG_BITS value | |
389 | #endif | |
ac56dd48 | 390 | |
c896fe29 | 391 | /* call flags */ |
78505279 AJ |
392 | /* Helper does not read globals (either directly or through an exception). It |
393 | implies TCG_CALL_NO_WRITE_GLOBALS. */ | |
3b50352b | 394 | #define TCG_CALL_NO_READ_GLOBALS 0x0001 |
78505279 | 395 | /* Helper does not write globals */ |
3b50352b | 396 | #define TCG_CALL_NO_WRITE_GLOBALS 0x0002 |
78505279 | 397 | /* Helper can be safely suppressed if the return value is not used. */ |
3b50352b | 398 | #define TCG_CALL_NO_SIDE_EFFECTS 0x0004 |
15d74092 RH |
399 | /* Helper is QEMU_NORETURN. */ |
400 | #define TCG_CALL_NO_RETURN 0x0008 | |
78505279 AJ |
401 | |
402 | /* convenience version of most used call flags */ | |
403 | #define TCG_CALL_NO_RWG TCG_CALL_NO_READ_GLOBALS | |
404 | #define TCG_CALL_NO_WG TCG_CALL_NO_WRITE_GLOBALS | |
405 | #define TCG_CALL_NO_SE TCG_CALL_NO_SIDE_EFFECTS | |
406 | #define TCG_CALL_NO_RWG_SE (TCG_CALL_NO_RWG | TCG_CALL_NO_SE) | |
407 | #define TCG_CALL_NO_WG_SE (TCG_CALL_NO_WG | TCG_CALL_NO_SE) | |
408 | ||
e89b28a6 RH |
409 | /* Used to align parameters. See the comment before tcgv_i32_temp. */ |
410 | #define TCG_CALL_DUMMY_ARG ((TCGArg)0) | |
39cf05d3 | 411 | |
587195bd RH |
412 | /* |
413 | * Flags for the bswap opcodes. | |
414 | * If IZ, the input is zero-extended, otherwise unknown. | |
415 | * If OZ or OS, the output is zero- or sign-extended respectively, | |
416 | * otherwise the high bits are undefined. | |
417 | */ | |
418 | enum { | |
419 | TCG_BSWAP_IZ = 1, | |
420 | TCG_BSWAP_OZ = 2, | |
421 | TCG_BSWAP_OS = 4, | |
422 | }; | |
423 | ||
00c8fa9f EC |
424 | typedef enum TCGTempVal { |
425 | TEMP_VAL_DEAD, | |
426 | TEMP_VAL_REG, | |
427 | TEMP_VAL_MEM, | |
428 | TEMP_VAL_CONST, | |
429 | } TCGTempVal; | |
c896fe29 | 430 | |
ee17db83 RH |
431 | typedef enum TCGTempKind { |
432 | /* Temp is dead at the end of all basic blocks. */ | |
433 | TEMP_NORMAL, | |
434 | /* Temp is saved across basic blocks but dead at the end of TBs. */ | |
435 | TEMP_LOCAL, | |
436 | /* Temp is saved across both basic blocks and translation blocks. */ | |
437 | TEMP_GLOBAL, | |
438 | /* Temp is in a fixed register. */ | |
439 | TEMP_FIXED, | |
c0522136 RH |
440 | /* Temp is a fixed constant. */ |
441 | TEMP_CONST, | |
ee17db83 RH |
442 | } TCGTempKind; |
443 | ||
c896fe29 | 444 | typedef struct TCGTemp { |
b6638662 | 445 | TCGReg reg:8; |
00c8fa9f EC |
446 | TCGTempVal val_type:8; |
447 | TCGType base_type:8; | |
448 | TCGType type:8; | |
ee17db83 | 449 | TCGTempKind kind:3; |
b3915dbb RH |
450 | unsigned int indirect_reg:1; |
451 | unsigned int indirect_base:1; | |
c896fe29 FB |
452 | unsigned int mem_coherent:1; |
453 | unsigned int mem_allocated:1; | |
fa477d25 | 454 | unsigned int temp_allocated:1; |
00c8fa9f | 455 | |
bdb38b95 | 456 | int64_t val; |
b3a62939 | 457 | struct TCGTemp *mem_base; |
00c8fa9f | 458 | intptr_t mem_offset; |
c896fe29 | 459 | const char *name; |
b83eabea RH |
460 | |
461 | /* Pass-specific information that can be stored for a temporary. | |
462 | One word worth of integer data, and one pointer to data | |
463 | allocated separately. */ | |
464 | uintptr_t state; | |
465 | void *state_ptr; | |
c896fe29 FB |
466 | } TCGTemp; |
467 | ||
c896fe29 FB |
468 | typedef struct TCGContext TCGContext; |
469 | ||
0ec9eabc RH |
470 | typedef struct TCGTempSet { |
471 | unsigned long l[BITS_TO_LONGS(TCG_MAX_TEMPS)]; | |
472 | } TCGTempSet; | |
473 | ||
a1b3c48d RH |
474 | /* While we limit helpers to 6 arguments, for 32-bit hosts, with padding, |
475 | this imples a max of 6*2 (64-bit in) + 2 (64-bit out) = 14 operands. | |
476 | There are never more than 2 outputs, which means that we can store all | |
477 | dead + sync data within 16 bits. */ | |
478 | #define DEAD_ARG 4 | |
479 | #define SYNC_ARG 1 | |
480 | typedef uint16_t TCGLifeData; | |
481 | ||
75e8b9b7 RH |
482 | /* The layout here is designed to avoid a bitfield crossing of |
483 | a 32-bit boundary, which would cause GCC to add extra padding. */ | |
c45cb8bb | 484 | typedef struct TCGOp { |
bee158cb RH |
485 | TCGOpcode opc : 8; /* 8 */ |
486 | ||
cd9090aa RH |
487 | /* Parameters for this opcode. See below. */ |
488 | unsigned param1 : 4; /* 12 */ | |
489 | unsigned param2 : 4; /* 16 */ | |
c45cb8bb | 490 | |
bee158cb | 491 | /* Lifetime data of the operands. */ |
15fa08f8 RH |
492 | unsigned life : 16; /* 32 */ |
493 | ||
494 | /* Next and previous opcodes. */ | |
495 | QTAILQ_ENTRY(TCGOp) link; | |
38b47b19 EC |
496 | #ifdef CONFIG_PLUGIN |
497 | QSIMPLEQ_ENTRY(TCGOp) plugin_link; | |
498 | #endif | |
75e8b9b7 RH |
499 | |
500 | /* Arguments for the opcode. */ | |
501 | TCGArg args[MAX_OPC_PARAM]; | |
69e3706d RH |
502 | |
503 | /* Register preferences for the output(s). */ | |
504 | TCGRegSet output_pref[2]; | |
c45cb8bb RH |
505 | } TCGOp; |
506 | ||
cd9090aa RH |
507 | #define TCGOP_CALLI(X) (X)->param1 |
508 | #define TCGOP_CALLO(X) (X)->param2 | |
509 | ||
d2fd745f RH |
510 | #define TCGOP_VECL(X) (X)->param1 |
511 | #define TCGOP_VECE(X) (X)->param2 | |
512 | ||
dcb8e758 RH |
513 | /* Make sure operands fit in the bitfields above. */ |
514 | QEMU_BUILD_BUG_ON(NB_OPS > (1 << 8)); | |
c45cb8bb | 515 | |
c3fac113 | 516 | typedef struct TCGProfile { |
72fd2efb | 517 | int64_t cpu_exec_time; |
c3fac113 EC |
518 | int64_t tb_count1; |
519 | int64_t tb_count; | |
520 | int64_t op_count; /* total insn count */ | |
521 | int op_count_max; /* max insn per TB */ | |
c3fac113 | 522 | int temp_count_max; |
dd1d7da2 | 523 | int64_t temp_count; |
c3fac113 EC |
524 | int64_t del_op_count; |
525 | int64_t code_in_len; | |
526 | int64_t code_out_len; | |
527 | int64_t search_out_len; | |
528 | int64_t interm_time; | |
529 | int64_t code_time; | |
530 | int64_t la_time; | |
531 | int64_t opt_time; | |
532 | int64_t restore_count; | |
533 | int64_t restore_time; | |
534 | int64_t table_op_count[NB_OPS]; | |
535 | } TCGProfile; | |
536 | ||
c896fe29 FB |
537 | struct TCGContext { |
538 | uint8_t *pool_cur, *pool_end; | |
4055299e | 539 | TCGPool *pool_first, *pool_current, *pool_first_large; |
c896fe29 | 540 | int nb_labels; |
c896fe29 FB |
541 | int nb_globals; |
542 | int nb_temps; | |
5a18407f | 543 | int nb_indirects; |
abebf925 | 544 | int nb_ops; |
c896fe29 FB |
545 | |
546 | /* goto_tb support */ | |
1813e175 | 547 | tcg_insn_unit *code_buf; |
f309101c | 548 | uint16_t *tb_jmp_reset_offset; /* tb->jmp_reset_offset */ |
a8583393 RH |
549 | uintptr_t *tb_jmp_insn_offset; /* tb->jmp_target_arg if direct_jump */ |
550 | uintptr_t *tb_jmp_target_addr; /* tb->jmp_target_arg if !direct_jump */ | |
c896fe29 | 551 | |
c896fe29 | 552 | TCGRegSet reserved_regs; |
e82d5a24 | 553 | uint32_t tb_cflags; /* cflags of the current TB */ |
e2c6d1b4 RH |
554 | intptr_t current_frame_offset; |
555 | intptr_t frame_start; | |
556 | intptr_t frame_end; | |
b3a62939 | 557 | TCGTemp *frame_temp; |
c896fe29 | 558 | |
1813e175 | 559 | tcg_insn_unit *code_ptr; |
c896fe29 | 560 | |
a23a9ec6 | 561 | #ifdef CONFIG_PROFILER |
c3fac113 | 562 | TCGProfile prof; |
a23a9ec6 | 563 | #endif |
27bfd83c PM |
564 | |
565 | #ifdef CONFIG_DEBUG_TCG | |
566 | int temps_in_use; | |
0a209d4b | 567 | int goto_tb_issue_mask; |
53229a77 | 568 | const TCGOpcode *vecop_list; |
27bfd83c | 569 | #endif |
b76f0d8c | 570 | |
1813e175 RH |
571 | /* Code generation. Note that we specifically do not use tcg_insn_unit |
572 | here, because there's too much arithmetic throughout that relies | |
573 | on addition and subtraction working on bytes. Rely on the GCC | |
574 | extension that allows arithmetic on void*. */ | |
1813e175 | 575 | void *code_gen_buffer; |
0b0d3320 | 576 | size_t code_gen_buffer_size; |
1813e175 | 577 | void *code_gen_ptr; |
57a26946 | 578 | void *data_gen_ptr; |
0b0d3320 | 579 | |
b125f9dc RH |
580 | /* Threshold to flush the translated code buffer. */ |
581 | void *code_gen_highwater; | |
582 | ||
7c255043 LV |
583 | /* Track which vCPU triggers events */ |
584 | CPUState *cpu; /* *_trans */ | |
7c255043 | 585 | |
139c1837 | 586 | /* These structures are private to tcg-target.c.inc. */ |
659ef5cb | 587 | #ifdef TCG_TARGET_NEED_LDST_LABELS |
b58deb34 | 588 | QSIMPLEQ_HEAD(, TCGLabelQemuLdst) ldst_labels; |
659ef5cb | 589 | #endif |
57a26946 RH |
590 | #ifdef TCG_TARGET_NEED_POOL_LABELS |
591 | struct TCGLabelPoolData *pool_labels; | |
592 | #endif | |
c45cb8bb | 593 | |
26689780 EC |
594 | TCGLabel *exitreq_label; |
595 | ||
38b47b19 EC |
596 | #ifdef CONFIG_PLUGIN |
597 | /* | |
598 | * We keep one plugin_tb struct per TCGContext. Note that on every TB | |
599 | * translation we clear but do not free its contents; this way we | |
600 | * avoid a lot of malloc/free churn, since after a few TB's it's | |
601 | * unlikely that we'll need to allocate either more instructions or more | |
602 | * space for instructions (for variable-instruction-length ISAs). | |
603 | */ | |
604 | struct qemu_plugin_tb *plugin_tb; | |
605 | ||
606 | /* descriptor of the instruction being translated */ | |
607 | struct qemu_plugin_insn *plugin_insn; | |
608 | ||
609 | /* list to quickly access the injected ops */ | |
610 | QSIMPLEQ_HEAD(, TCGOp) plugin_ops; | |
611 | #endif | |
612 | ||
c0522136 | 613 | GHashTable *const_table[TCG_TYPE_COUNT]; |
c45cb8bb RH |
614 | TCGTempSet free_temps[TCG_TYPE_COUNT * 2]; |
615 | TCGTemp temps[TCG_MAX_TEMPS]; /* globals first, temps after */ | |
616 | ||
eae3eb3e | 617 | QTAILQ_HEAD(, TCGOp) ops, free_ops; |
7ecd02a0 | 618 | QSIMPLEQ_HEAD(, TCGLabel) labels; |
15fa08f8 | 619 | |
f8b2f202 RH |
620 | /* Tells which temporary holds a given register. |
621 | It does not take into account fixed registers */ | |
622 | TCGTemp *reg_to_temp[TCG_TARGET_NB_REGS]; | |
c45cb8bb | 623 | |
fca8a500 RH |
624 | uint16_t gen_insn_end_off[TCG_MAX_INSNS]; |
625 | target_ulong gen_insn_data[TCG_MAX_INSNS][TARGET_INSN_START_WORDS]; | |
ae30e866 RH |
626 | |
627 | /* Exit to translator on overflow. */ | |
628 | sigjmp_buf jmp_trans; | |
c896fe29 FB |
629 | }; |
630 | ||
e01fa97d RH |
631 | static inline bool temp_readonly(TCGTemp *ts) |
632 | { | |
c0522136 | 633 | return ts->kind >= TEMP_FIXED; |
e01fa97d RH |
634 | } |
635 | ||
3468b59e | 636 | extern __thread TCGContext *tcg_ctx; |
c8bc1168 | 637 | extern const void *tcg_code_gen_epilogue; |
db0c51a3 | 638 | extern uintptr_t tcg_splitwx_diff; |
1c2adb95 | 639 | extern TCGv_env cpu_env; |
c896fe29 | 640 | |
47d590df | 641 | bool in_code_gen_buffer(const void *p); |
4846cd37 | 642 | |
db0c51a3 RH |
643 | #ifdef CONFIG_DEBUG_TCG |
644 | const void *tcg_splitwx_to_rx(void *rw); | |
645 | void *tcg_splitwx_to_rw(const void *rx); | |
646 | #else | |
647 | static inline const void *tcg_splitwx_to_rx(void *rw) | |
648 | { | |
649 | return rw ? rw + tcg_splitwx_diff : NULL; | |
650 | } | |
651 | ||
652 | static inline void *tcg_splitwx_to_rw(const void *rx) | |
653 | { | |
654 | return rx ? (void *)rx - tcg_splitwx_diff : NULL; | |
655 | } | |
656 | #endif | |
657 | ||
1807f4c4 RH |
658 | static inline size_t temp_idx(TCGTemp *ts) |
659 | { | |
b1311c4a EC |
660 | ptrdiff_t n = ts - tcg_ctx->temps; |
661 | tcg_debug_assert(n >= 0 && n < tcg_ctx->nb_temps); | |
1807f4c4 RH |
662 | return n; |
663 | } | |
664 | ||
665 | static inline TCGArg temp_arg(TCGTemp *ts) | |
666 | { | |
e89b28a6 | 667 | return (uintptr_t)ts; |
1807f4c4 RH |
668 | } |
669 | ||
43439139 RH |
670 | static inline TCGTemp *arg_temp(TCGArg a) |
671 | { | |
e89b28a6 | 672 | return (TCGTemp *)(uintptr_t)a; |
43439139 RH |
673 | } |
674 | ||
e89b28a6 RH |
675 | /* Using the offset of a temporary, relative to TCGContext, rather than |
676 | its index means that we don't use 0. That leaves offset 0 free for | |
677 | a NULL representation without having to leave index 0 unused. */ | |
678 | static inline TCGTemp *tcgv_i32_temp(TCGv_i32 v) | |
6349039d | 679 | { |
e89b28a6 | 680 | uintptr_t o = (uintptr_t)v; |
b1311c4a | 681 | TCGTemp *t = (void *)tcg_ctx + o; |
e89b28a6 RH |
682 | tcg_debug_assert(offsetof(TCGContext, temps[temp_idx(t)]) == o); |
683 | return t; | |
ae8b75dc RH |
684 | } |
685 | ||
e89b28a6 | 686 | static inline TCGTemp *tcgv_i64_temp(TCGv_i64 v) |
ae8b75dc | 687 | { |
e89b28a6 | 688 | return tcgv_i32_temp((TCGv_i32)v); |
ae8b75dc RH |
689 | } |
690 | ||
e89b28a6 | 691 | static inline TCGTemp *tcgv_ptr_temp(TCGv_ptr v) |
ae8b75dc | 692 | { |
e89b28a6 | 693 | return tcgv_i32_temp((TCGv_i32)v); |
ae8b75dc RH |
694 | } |
695 | ||
d2fd745f RH |
696 | static inline TCGTemp *tcgv_vec_temp(TCGv_vec v) |
697 | { | |
698 | return tcgv_i32_temp((TCGv_i32)v); | |
699 | } | |
700 | ||
e89b28a6 | 701 | static inline TCGArg tcgv_i32_arg(TCGv_i32 v) |
ae8b75dc | 702 | { |
e89b28a6 | 703 | return temp_arg(tcgv_i32_temp(v)); |
ae8b75dc RH |
704 | } |
705 | ||
e89b28a6 | 706 | static inline TCGArg tcgv_i64_arg(TCGv_i64 v) |
ae8b75dc | 707 | { |
e89b28a6 | 708 | return temp_arg(tcgv_i64_temp(v)); |
ae8b75dc RH |
709 | } |
710 | ||
e89b28a6 | 711 | static inline TCGArg tcgv_ptr_arg(TCGv_ptr v) |
ae8b75dc | 712 | { |
e89b28a6 | 713 | return temp_arg(tcgv_ptr_temp(v)); |
ae8b75dc RH |
714 | } |
715 | ||
d2fd745f RH |
716 | static inline TCGArg tcgv_vec_arg(TCGv_vec v) |
717 | { | |
718 | return temp_arg(tcgv_vec_temp(v)); | |
719 | } | |
720 | ||
085272b3 RH |
721 | static inline TCGv_i32 temp_tcgv_i32(TCGTemp *t) |
722 | { | |
e89b28a6 | 723 | (void)temp_idx(t); /* trigger embedded assert */ |
b1311c4a | 724 | return (TCGv_i32)((void *)t - (void *)tcg_ctx); |
085272b3 RH |
725 | } |
726 | ||
727 | static inline TCGv_i64 temp_tcgv_i64(TCGTemp *t) | |
728 | { | |
e89b28a6 | 729 | return (TCGv_i64)temp_tcgv_i32(t); |
085272b3 RH |
730 | } |
731 | ||
732 | static inline TCGv_ptr temp_tcgv_ptr(TCGTemp *t) | |
733 | { | |
e89b28a6 | 734 | return (TCGv_ptr)temp_tcgv_i32(t); |
085272b3 RH |
735 | } |
736 | ||
d2fd745f RH |
737 | static inline TCGv_vec temp_tcgv_vec(TCGTemp *t) |
738 | { | |
739 | return (TCGv_vec)temp_tcgv_i32(t); | |
740 | } | |
741 | ||
dc41aa7d RH |
742 | #if TCG_TARGET_REG_BITS == 32 |
743 | static inline TCGv_i32 TCGV_LOW(TCGv_i64 t) | |
744 | { | |
745 | return temp_tcgv_i32(tcgv_i64_temp(t)); | |
746 | } | |
747 | ||
748 | static inline TCGv_i32 TCGV_HIGH(TCGv_i64 t) | |
749 | { | |
750 | return temp_tcgv_i32(tcgv_i64_temp(t) + 1); | |
751 | } | |
752 | #endif | |
753 | ||
2271a6ac RH |
754 | static inline TCGArg tcg_get_insn_param(TCGOp *op, int arg) |
755 | { | |
756 | return op->args[arg]; | |
757 | } | |
758 | ||
15fa08f8 | 759 | static inline void tcg_set_insn_param(TCGOp *op, int arg, TCGArg v) |
1d41478f | 760 | { |
15fa08f8 | 761 | op->args[arg] = v; |
1d41478f EI |
762 | } |
763 | ||
2271a6ac RH |
764 | static inline target_ulong tcg_get_insn_start_param(TCGOp *op, int arg) |
765 | { | |
766 | #if TARGET_LONG_BITS <= TCG_TARGET_REG_BITS | |
767 | return tcg_get_insn_param(op, arg); | |
768 | #else | |
769 | return tcg_get_insn_param(op, arg * 2) | | |
770 | ((uint64_t)tcg_get_insn_param(op, arg * 2 + 1) << 32); | |
771 | #endif | |
772 | } | |
773 | ||
9743cd57 RH |
774 | static inline void tcg_set_insn_start_param(TCGOp *op, int arg, target_ulong v) |
775 | { | |
776 | #if TARGET_LONG_BITS <= TCG_TARGET_REG_BITS | |
777 | tcg_set_insn_param(op, arg, v); | |
778 | #else | |
779 | tcg_set_insn_param(op, arg * 2, v); | |
780 | tcg_set_insn_param(op, arg * 2 + 1, v >> 32); | |
781 | #endif | |
782 | } | |
783 | ||
15fa08f8 RH |
784 | /* The last op that was emitted. */ |
785 | static inline TCGOp *tcg_last_op(void) | |
fe700adb | 786 | { |
eae3eb3e | 787 | return QTAILQ_LAST(&tcg_ctx->ops); |
fe700adb RH |
788 | } |
789 | ||
790 | /* Test for whether to terminate the TB for using too many opcodes. */ | |
791 | static inline bool tcg_op_buf_full(void) | |
792 | { | |
abebf925 RH |
793 | /* This is not a hard limit, it merely stops translation when |
794 | * we have produced "enough" opcodes. We want to limit TB size | |
795 | * such that a RISC host can reasonably use a 16-bit signed | |
9f754620 RH |
796 | * branch within the TB. We also need to be mindful of the |
797 | * 16-bit unsigned offsets, TranslationBlock.jmp_reset_offset[] | |
798 | * and TCGContext.gen_insn_end_off[]. | |
abebf925 | 799 | */ |
9f754620 | 800 | return tcg_ctx->nb_ops >= 4000; |
fe700adb RH |
801 | } |
802 | ||
c896fe29 FB |
803 | /* pool based memory allocation */ |
804 | ||
0ac20318 | 805 | /* user-mode: mmap_lock must be held for tcg_malloc_internal. */ |
c896fe29 FB |
806 | void *tcg_malloc_internal(TCGContext *s, int size); |
807 | void tcg_pool_reset(TCGContext *s); | |
6e3b2bfd | 808 | TranslationBlock *tcg_tb_alloc(TCGContext *s); |
c896fe29 | 809 | |
e8feb96f EC |
810 | void tcg_region_reset_all(void); |
811 | ||
812 | size_t tcg_code_size(void); | |
813 | size_t tcg_code_capacity(void); | |
814 | ||
be2cdc5e EC |
815 | void tcg_tb_insert(TranslationBlock *tb); |
816 | void tcg_tb_remove(TranslationBlock *tb); | |
817 | TranslationBlock *tcg_tb_lookup(uintptr_t tc_ptr); | |
818 | void tcg_tb_foreach(GTraverseFunc func, gpointer user_data); | |
819 | size_t tcg_nb_tbs(void); | |
820 | ||
0ac20318 | 821 | /* user-mode: Called with mmap_lock held. */ |
c896fe29 FB |
822 | static inline void *tcg_malloc(int size) |
823 | { | |
b1311c4a | 824 | TCGContext *s = tcg_ctx; |
c896fe29 | 825 | uint8_t *ptr, *ptr_end; |
13aaef67 RH |
826 | |
827 | /* ??? This is a weak placeholder for minimum malloc alignment. */ | |
828 | size = QEMU_ALIGN_UP(size, 8); | |
829 | ||
c896fe29 FB |
830 | ptr = s->pool_cur; |
831 | ptr_end = ptr + size; | |
832 | if (unlikely(ptr_end > s->pool_end)) { | |
b1311c4a | 833 | return tcg_malloc_internal(tcg_ctx, size); |
c896fe29 FB |
834 | } else { |
835 | s->pool_cur = ptr_end; | |
836 | return ptr; | |
837 | } | |
838 | } | |
839 | ||
43b972b7 | 840 | void tcg_init(size_t tb_size, int splitwx, unsigned max_cpus); |
3468b59e | 841 | void tcg_register_thread(void); |
9002ec79 | 842 | void tcg_prologue_init(TCGContext *s); |
c896fe29 FB |
843 | void tcg_func_start(TCGContext *s); |
844 | ||
5bd2ec3d | 845 | int tcg_gen_code(TCGContext *s, TranslationBlock *tb); |
c896fe29 | 846 | |
b6638662 | 847 | void tcg_set_frame(TCGContext *s, TCGReg reg, intptr_t start, intptr_t size); |
a7812ae4 | 848 | |
085272b3 RH |
849 | TCGTemp *tcg_global_mem_new_internal(TCGType, TCGv_ptr, |
850 | intptr_t, const char *); | |
5bfa8034 RH |
851 | TCGTemp *tcg_temp_new_internal(TCGType, bool); |
852 | void tcg_temp_free_internal(TCGTemp *); | |
d2fd745f RH |
853 | TCGv_vec tcg_temp_new_vec(TCGType type); |
854 | TCGv_vec tcg_temp_new_vec_matching(TCGv_vec match); | |
e1ccc054 | 855 | |
5bfa8034 RH |
856 | static inline void tcg_temp_free_i32(TCGv_i32 arg) |
857 | { | |
858 | tcg_temp_free_internal(tcgv_i32_temp(arg)); | |
859 | } | |
860 | ||
861 | static inline void tcg_temp_free_i64(TCGv_i64 arg) | |
862 | { | |
863 | tcg_temp_free_internal(tcgv_i64_temp(arg)); | |
864 | } | |
865 | ||
866 | static inline void tcg_temp_free_ptr(TCGv_ptr arg) | |
867 | { | |
868 | tcg_temp_free_internal(tcgv_ptr_temp(arg)); | |
869 | } | |
870 | ||
871 | static inline void tcg_temp_free_vec(TCGv_vec arg) | |
872 | { | |
873 | tcg_temp_free_internal(tcgv_vec_temp(arg)); | |
874 | } | |
e1ccc054 | 875 | |
e1ccc054 RH |
876 | static inline TCGv_i32 tcg_global_mem_new_i32(TCGv_ptr reg, intptr_t offset, |
877 | const char *name) | |
878 | { | |
085272b3 RH |
879 | TCGTemp *t = tcg_global_mem_new_internal(TCG_TYPE_I32, reg, offset, name); |
880 | return temp_tcgv_i32(t); | |
e1ccc054 RH |
881 | } |
882 | ||
a7812ae4 PB |
883 | static inline TCGv_i32 tcg_temp_new_i32(void) |
884 | { | |
5bfa8034 RH |
885 | TCGTemp *t = tcg_temp_new_internal(TCG_TYPE_I32, false); |
886 | return temp_tcgv_i32(t); | |
a7812ae4 | 887 | } |
e1ccc054 | 888 | |
a7812ae4 PB |
889 | static inline TCGv_i32 tcg_temp_local_new_i32(void) |
890 | { | |
5bfa8034 RH |
891 | TCGTemp *t = tcg_temp_new_internal(TCG_TYPE_I32, true); |
892 | return temp_tcgv_i32(t); | |
a7812ae4 | 893 | } |
a7812ae4 | 894 | |
e1ccc054 RH |
895 | static inline TCGv_i64 tcg_global_mem_new_i64(TCGv_ptr reg, intptr_t offset, |
896 | const char *name) | |
897 | { | |
085272b3 RH |
898 | TCGTemp *t = tcg_global_mem_new_internal(TCG_TYPE_I64, reg, offset, name); |
899 | return temp_tcgv_i64(t); | |
e1ccc054 RH |
900 | } |
901 | ||
a7812ae4 | 902 | static inline TCGv_i64 tcg_temp_new_i64(void) |
641d5fbe | 903 | { |
5bfa8034 RH |
904 | TCGTemp *t = tcg_temp_new_internal(TCG_TYPE_I64, false); |
905 | return temp_tcgv_i64(t); | |
641d5fbe | 906 | } |
e1ccc054 | 907 | |
a7812ae4 | 908 | static inline TCGv_i64 tcg_temp_local_new_i64(void) |
641d5fbe | 909 | { |
5bfa8034 RH |
910 | TCGTemp *t = tcg_temp_new_internal(TCG_TYPE_I64, true); |
911 | return temp_tcgv_i64(t); | |
912 | } | |
913 | ||
914 | static inline TCGv_ptr tcg_global_mem_new_ptr(TCGv_ptr reg, intptr_t offset, | |
915 | const char *name) | |
916 | { | |
917 | TCGTemp *t = tcg_global_mem_new_internal(TCG_TYPE_PTR, reg, offset, name); | |
918 | return temp_tcgv_ptr(t); | |
919 | } | |
920 | ||
921 | static inline TCGv_ptr tcg_temp_new_ptr(void) | |
922 | { | |
923 | TCGTemp *t = tcg_temp_new_internal(TCG_TYPE_PTR, false); | |
924 | return temp_tcgv_ptr(t); | |
925 | } | |
926 | ||
927 | static inline TCGv_ptr tcg_temp_local_new_ptr(void) | |
928 | { | |
929 | TCGTemp *t = tcg_temp_new_internal(TCG_TYPE_PTR, true); | |
930 | return temp_tcgv_ptr(t); | |
641d5fbe | 931 | } |
a7812ae4 | 932 | |
27bfd83c PM |
933 | #if defined(CONFIG_DEBUG_TCG) |
934 | /* If you call tcg_clear_temp_count() at the start of a section of | |
935 | * code which is not supposed to leak any TCG temporaries, then | |
936 | * calling tcg_check_temp_count() at the end of the section will | |
937 | * return 1 if the section did in fact leak a temporary. | |
938 | */ | |
939 | void tcg_clear_temp_count(void); | |
940 | int tcg_check_temp_count(void); | |
941 | #else | |
942 | #define tcg_clear_temp_count() do { } while (0) | |
943 | #define tcg_check_temp_count() 0 | |
944 | #endif | |
945 | ||
72fd2efb | 946 | int64_t tcg_cpu_exec_time(void); |
3de2faa9 | 947 | void tcg_dump_info(void); |
d4c51a0a | 948 | void tcg_dump_op_count(void); |
c896fe29 | 949 | |
bc2b17e6 | 950 | #define TCG_CT_CONST 1 /* any constant of register size */ |
c896fe29 FB |
951 | |
952 | typedef struct TCGArgConstraint { | |
bc2b17e6 RH |
953 | unsigned ct : 16; |
954 | unsigned alias_index : 4; | |
955 | unsigned sort_index : 4; | |
956 | bool oalias : 1; | |
957 | bool ialias : 1; | |
958 | bool newreg : 1; | |
9be0d080 | 959 | TCGRegSet regs; |
c896fe29 FB |
960 | } TCGArgConstraint; |
961 | ||
962 | #define TCG_MAX_OP_ARGS 16 | |
963 | ||
b4cb76e6 | 964 | /* Bits for TCGOpDef->flags, 8 bits available, all used. */ |
8399ad59 | 965 | enum { |
ae36a246 RH |
966 | /* Instruction exits the translation block. */ |
967 | TCG_OPF_BB_EXIT = 0x01, | |
8399ad59 | 968 | /* Instruction defines the end of a basic block. */ |
ae36a246 | 969 | TCG_OPF_BB_END = 0x02, |
8399ad59 | 970 | /* Instruction clobbers call registers and potentially update globals. */ |
ae36a246 | 971 | TCG_OPF_CALL_CLOBBER = 0x04, |
3d5c5f87 AJ |
972 | /* Instruction has side effects: it cannot be removed if its outputs |
973 | are not used, and might trigger exceptions. */ | |
ae36a246 | 974 | TCG_OPF_SIDE_EFFECTS = 0x08, |
8399ad59 | 975 | /* Instruction operands are 64-bits (otherwise 32-bits). */ |
ae36a246 | 976 | TCG_OPF_64BIT = 0x10, |
c1a61f6c RH |
977 | /* Instruction is optional and not implemented by the host, or insn |
978 | is generic and should not be implemened by the host. */ | |
ae36a246 | 979 | TCG_OPF_NOT_PRESENT = 0x20, |
d2fd745f | 980 | /* Instruction operands are vectors. */ |
ae36a246 | 981 | TCG_OPF_VECTOR = 0x40, |
b4cb76e6 RH |
982 | /* Instruction is a conditional branch. */ |
983 | TCG_OPF_COND_BRANCH = 0x80 | |
8399ad59 | 984 | }; |
c896fe29 FB |
985 | |
986 | typedef struct TCGOpDef { | |
987 | const char *name; | |
988 | uint8_t nb_oargs, nb_iargs, nb_cargs, nb_args; | |
989 | uint8_t flags; | |
c896fe29 | 990 | TCGArgConstraint *args_ct; |
c896fe29 | 991 | } TCGOpDef; |
8399ad59 RH |
992 | |
993 | extern TCGOpDef tcg_op_defs[]; | |
2a24374a SW |
994 | extern const size_t tcg_op_defs_max; |
995 | ||
c896fe29 | 996 | typedef struct TCGTargetOpDef { |
a9751609 | 997 | TCGOpcode op; |
c896fe29 FB |
998 | const char *args_ct_str[TCG_MAX_OP_ARGS]; |
999 | } TCGTargetOpDef; | |
1000 | ||
c896fe29 FB |
1001 | #define tcg_abort() \ |
1002 | do {\ | |
1003 | fprintf(stderr, "%s:%d: tcg fatal error\n", __FILE__, __LINE__);\ | |
1004 | abort();\ | |
1005 | } while (0) | |
1006 | ||
be0f34b5 RH |
1007 | bool tcg_op_supported(TCGOpcode op); |
1008 | ||
ae8b75dc | 1009 | void tcg_gen_callN(void *func, TCGTemp *ret, int nargs, TCGTemp **args); |
a7812ae4 | 1010 | |
15fa08f8 | 1011 | TCGOp *tcg_emit_op(TCGOpcode opc); |
0c627cdc | 1012 | void tcg_op_remove(TCGContext *s, TCGOp *op); |
ac1043f6 EC |
1013 | TCGOp *tcg_op_insert_before(TCGContext *s, TCGOp *op, TCGOpcode opc); |
1014 | TCGOp *tcg_op_insert_after(TCGContext *s, TCGOp *op, TCGOpcode opc); | |
5a18407f | 1015 | |
a80cdd31 RH |
1016 | /** |
1017 | * tcg_remove_ops_after: | |
1018 | * @op: target operation | |
1019 | * | |
1020 | * Discard any opcodes emitted since @op. Expected usage is to save | |
1021 | * a starting point with tcg_last_op(), speculatively emit opcodes, | |
1022 | * then decide whether or not to keep those opcodes after the fact. | |
1023 | */ | |
1024 | void tcg_remove_ops_after(TCGOp *op); | |
1025 | ||
c45cb8bb | 1026 | void tcg_optimize(TCGContext *s); |
a7812ae4 | 1027 | |
c0522136 | 1028 | /* Allocate a new temporary and initialize it with a constant. */ |
a7812ae4 PB |
1029 | TCGv_i32 tcg_const_i32(int32_t val); |
1030 | TCGv_i64 tcg_const_i64(int64_t val); | |
1031 | TCGv_i32 tcg_const_local_i32(int32_t val); | |
1032 | TCGv_i64 tcg_const_local_i64(int64_t val); | |
d2fd745f RH |
1033 | TCGv_vec tcg_const_zeros_vec(TCGType); |
1034 | TCGv_vec tcg_const_ones_vec(TCGType); | |
1035 | TCGv_vec tcg_const_zeros_vec_matching(TCGv_vec); | |
1036 | TCGv_vec tcg_const_ones_vec_matching(TCGv_vec); | |
a7812ae4 | 1037 | |
c0522136 RH |
1038 | /* |
1039 | * Locate or create a read-only temporary that is a constant. | |
a14b3ad1 RH |
1040 | * This kind of temporary need not be freed, but for convenience |
1041 | * will be silently ignored by tcg_temp_free_*. | |
c0522136 RH |
1042 | */ |
1043 | TCGTemp *tcg_constant_internal(TCGType type, int64_t val); | |
1044 | ||
1045 | static inline TCGv_i32 tcg_constant_i32(int32_t val) | |
1046 | { | |
1047 | return temp_tcgv_i32(tcg_constant_internal(TCG_TYPE_I32, val)); | |
1048 | } | |
1049 | ||
1050 | static inline TCGv_i64 tcg_constant_i64(int64_t val) | |
1051 | { | |
1052 | return temp_tcgv_i64(tcg_constant_internal(TCG_TYPE_I64, val)); | |
1053 | } | |
1054 | ||
1055 | TCGv_vec tcg_constant_vec(TCGType type, unsigned vece, int64_t val); | |
88d4005b | 1056 | TCGv_vec tcg_constant_vec_matching(TCGv_vec match, unsigned vece, int64_t val); |
c0522136 | 1057 | |
5bfa8034 RH |
1058 | #if UINTPTR_MAX == UINT32_MAX |
1059 | # define tcg_const_ptr(x) ((TCGv_ptr)tcg_const_i32((intptr_t)(x))) | |
1060 | # define tcg_const_local_ptr(x) ((TCGv_ptr)tcg_const_local_i32((intptr_t)(x))) | |
1061 | #else | |
1062 | # define tcg_const_ptr(x) ((TCGv_ptr)tcg_const_i64((intptr_t)(x))) | |
1063 | # define tcg_const_local_ptr(x) ((TCGv_ptr)tcg_const_local_i64((intptr_t)(x))) | |
1064 | #endif | |
1065 | ||
42a268c2 RH |
1066 | TCGLabel *gen_new_label(void); |
1067 | ||
1068 | /** | |
1069 | * label_arg | |
1070 | * @l: label | |
1071 | * | |
1072 | * Encode a label for storage in the TCG opcode stream. | |
1073 | */ | |
1074 | ||
1075 | static inline TCGArg label_arg(TCGLabel *l) | |
1076 | { | |
51e3972c | 1077 | return (uintptr_t)l; |
42a268c2 RH |
1078 | } |
1079 | ||
1080 | /** | |
1081 | * arg_label | |
1082 | * @i: value | |
1083 | * | |
1084 | * The opposite of label_arg. Retrieve a label from the | |
1085 | * encoding of the TCG opcode stream. | |
1086 | */ | |
1087 | ||
51e3972c | 1088 | static inline TCGLabel *arg_label(TCGArg i) |
42a268c2 | 1089 | { |
51e3972c | 1090 | return (TCGLabel *)(uintptr_t)i; |
42a268c2 RH |
1091 | } |
1092 | ||
52a1f64e RH |
1093 | /** |
1094 | * tcg_ptr_byte_diff | |
1095 | * @a, @b: addresses to be differenced | |
1096 | * | |
1097 | * There are many places within the TCG backends where we need a byte | |
1098 | * difference between two pointers. While this can be accomplished | |
1099 | * with local casting, it's easy to get wrong -- especially if one is | |
1100 | * concerned with the signedness of the result. | |
1101 | * | |
1102 | * This version relies on GCC's void pointer arithmetic to get the | |
1103 | * correct result. | |
1104 | */ | |
1105 | ||
db0c51a3 | 1106 | static inline ptrdiff_t tcg_ptr_byte_diff(const void *a, const void *b) |
52a1f64e RH |
1107 | { |
1108 | return a - b; | |
1109 | } | |
1110 | ||
1111 | /** | |
1112 | * tcg_pcrel_diff | |
1113 | * @s: the tcg context | |
1114 | * @target: address of the target | |
1115 | * | |
1116 | * Produce a pc-relative difference, from the current code_ptr | |
1117 | * to the destination address. | |
1118 | */ | |
1119 | ||
db0c51a3 | 1120 | static inline ptrdiff_t tcg_pcrel_diff(TCGContext *s, const void *target) |
52a1f64e | 1121 | { |
db0c51a3 | 1122 | return tcg_ptr_byte_diff(target, tcg_splitwx_to_rx(s->code_ptr)); |
52a1f64e RH |
1123 | } |
1124 | ||
44c7197f RH |
1125 | /** |
1126 | * tcg_tbrel_diff | |
1127 | * @s: the tcg context | |
1128 | * @target: address of the target | |
1129 | * | |
1130 | * Produce a difference, from the beginning of the current TB code | |
1131 | * to the destination address. | |
1132 | */ | |
1133 | static inline ptrdiff_t tcg_tbrel_diff(TCGContext *s, const void *target) | |
1134 | { | |
1135 | return tcg_ptr_byte_diff(target, tcg_splitwx_to_rx(s->code_buf)); | |
1136 | } | |
1137 | ||
52a1f64e RH |
1138 | /** |
1139 | * tcg_current_code_size | |
1140 | * @s: the tcg context | |
1141 | * | |
1142 | * Compute the current code size within the translation block. | |
1143 | * This is used to fill in qemu's data structures for goto_tb. | |
1144 | */ | |
1145 | ||
1146 | static inline size_t tcg_current_code_size(TCGContext *s) | |
1147 | { | |
1148 | return tcg_ptr_byte_diff(s->code_ptr, s->code_buf); | |
1149 | } | |
1150 | ||
0980011b PM |
1151 | /** |
1152 | * tcg_qemu_tb_exec: | |
819af24b | 1153 | * @env: pointer to CPUArchState for the CPU |
0980011b PM |
1154 | * @tb_ptr: address of generated code for the TB to execute |
1155 | * | |
1156 | * Start executing code from a given translation block. | |
1157 | * Where translation blocks have been linked, execution | |
1158 | * may proceed from the given TB into successive ones. | |
1159 | * Control eventually returns only when some action is needed | |
1160 | * from the top-level loop: either control must pass to a TB | |
1161 | * which has not yet been directly linked, or an asynchronous | |
1162 | * event such as an interrupt needs handling. | |
1163 | * | |
819af24b SF |
1164 | * Return: The return value is the value passed to the corresponding |
1165 | * tcg_gen_exit_tb() at translation time of the last TB attempted to execute. | |
1166 | * The value is either zero or a 4-byte aligned pointer to that TB combined | |
1167 | * with additional information in its two least significant bits. The | |
1168 | * additional information is encoded as follows: | |
0980011b PM |
1169 | * 0, 1: the link between this TB and the next is via the specified |
1170 | * TB index (0 or 1). That is, we left the TB via (the equivalent | |
1171 | * of) "goto_tb <index>". The main loop uses this to determine | |
1172 | * how to link the TB just executed to the next. | |
1173 | * 2: we are using instruction counting code generation, and we | |
1174 | * did not start executing this TB because the instruction counter | |
819af24b | 1175 | * would hit zero midway through it. In this case the pointer |
0980011b PM |
1176 | * returned is the TB we were about to execute, and the caller must |
1177 | * arrange to execute the remaining count of instructions. | |
378df4b2 PM |
1178 | * 3: we stopped because the CPU's exit_request flag was set |
1179 | * (usually meaning that there is an interrupt that needs to be | |
819af24b SF |
1180 | * handled). The pointer returned is the TB we were about to execute |
1181 | * when we noticed the pending exit request. | |
0980011b PM |
1182 | * |
1183 | * If the bottom two bits indicate an exit-via-index then the CPU | |
1184 | * state is correctly synchronised and ready for execution of the next | |
1185 | * TB (and in particular the guest PC is the address to execute next). | |
1186 | * Otherwise, we gave up on execution of this TB before it started, and | |
fee068e4 | 1187 | * the caller must fix up the CPU state by calling the CPU's |
819af24b | 1188 | * synchronize_from_tb() method with the TB pointer we return (falling |
fee068e4 PC |
1189 | * back to calling the CPU's set_pc method with tb->pb if no |
1190 | * synchronize_from_tb() method exists). | |
0980011b PM |
1191 | * |
1192 | * Note that TCG targets may use a different definition of tcg_qemu_tb_exec | |
1193 | * to this default (which just calls the prologue.code emitted by | |
1194 | * tcg_target_qemu_prologue()). | |
1195 | */ | |
07ea28b4 RH |
1196 | #define TB_EXIT_MASK 3 |
1197 | #define TB_EXIT_IDX0 0 | |
1198 | #define TB_EXIT_IDX1 1 | |
1199 | #define TB_EXIT_IDXMAX 1 | |
378df4b2 | 1200 | #define TB_EXIT_REQUESTED 3 |
0980011b | 1201 | |
b91ccb31 | 1202 | #ifdef CONFIG_TCG_INTERPRETER |
db0c51a3 | 1203 | uintptr_t tcg_qemu_tb_exec(CPUArchState *env, const void *tb_ptr); |
5a58e884 | 1204 | #else |
db0c51a3 | 1205 | typedef uintptr_t tcg_prologue_fn(CPUArchState *env, const void *tb_ptr); |
b91ccb31 | 1206 | extern tcg_prologue_fn *tcg_qemu_tb_exec; |
932a6909 | 1207 | #endif |
813da627 | 1208 | |
755bf9e5 | 1209 | void tcg_register_jit(const void *buf, size_t buf_size); |
b76f0d8c | 1210 | |
db432672 RH |
1211 | #if TCG_TARGET_MAYBE_vec |
1212 | /* Return zero if the tuple (opc, type, vece) is unsupportable; | |
1213 | return > 0 if it is directly supportable; | |
1214 | return < 0 if we must call tcg_expand_vec_op. */ | |
1215 | int tcg_can_emit_vec_op(TCGOpcode, TCGType, unsigned); | |
1216 | #else | |
1217 | static inline int tcg_can_emit_vec_op(TCGOpcode o, TCGType t, unsigned ve) | |
1218 | { | |
1219 | return 0; | |
1220 | } | |
1221 | #endif | |
1222 | ||
1223 | /* Expand the tuple (opc, type, vece) on the given arguments. */ | |
1224 | void tcg_expand_vec_op(TCGOpcode, TCGType, unsigned, TCGArg, ...); | |
1225 | ||
1226 | /* Replicate a constant C accoring to the log2 of the element size. */ | |
1227 | uint64_t dup_const(unsigned vece, uint64_t c); | |
1228 | ||
1229 | #define dup_const(VECE, C) \ | |
1230 | (__builtin_constant_p(VECE) \ | |
1231 | ? ( (VECE) == MO_8 ? 0x0101010101010101ull * (uint8_t)(C) \ | |
1232 | : (VECE) == MO_16 ? 0x0001000100010001ull * (uint16_t)(C) \ | |
1233 | : (VECE) == MO_32 ? 0x0000000100000001ull * (uint32_t)(C) \ | |
666cc794 RH |
1234 | : (VECE) == MO_64 ? (uint64_t)(C) \ |
1235 | : (qemu_build_not_reached_always(), 0)) \ | |
db432672 RH |
1236 | : dup_const(VECE, C)) |
1237 | ||
db637f27 PT |
1238 | #if TARGET_LONG_BITS == 64 |
1239 | # define dup_const_tl dup_const | |
1240 | #else | |
1241 | # define dup_const_tl(VECE, C) \ | |
1242 | (__builtin_constant_p(VECE) \ | |
1243 | ? ( (VECE) == MO_8 ? 0x01010101ul * (uint8_t)(C) \ | |
1244 | : (VECE) == MO_16 ? 0x00010001ul * (uint16_t)(C) \ | |
1245 | : (VECE) == MO_32 ? 0x00000001ul * (uint32_t)(C) \ | |
1246 | : (qemu_build_not_reached_always(), 0)) \ | |
1247 | : (target_long)dup_const(VECE, C)) | |
1248 | #endif | |
1249 | ||
e58eb534 RH |
1250 | /* |
1251 | * Memory helpers that will be used by TCG generated code. | |
1252 | */ | |
1253 | #ifdef CONFIG_SOFTMMU | |
c8f94df5 RH |
1254 | /* Value zero-extended to tcg register size. */ |
1255 | tcg_target_ulong helper_ret_ldub_mmu(CPUArchState *env, target_ulong addr, | |
9002ffcb | 1256 | MemOpIdx oi, uintptr_t retaddr); |
867b3201 | 1257 | tcg_target_ulong helper_le_lduw_mmu(CPUArchState *env, target_ulong addr, |
9002ffcb | 1258 | MemOpIdx oi, uintptr_t retaddr); |
867b3201 | 1259 | tcg_target_ulong helper_le_ldul_mmu(CPUArchState *env, target_ulong addr, |
9002ffcb | 1260 | MemOpIdx oi, uintptr_t retaddr); |
867b3201 | 1261 | uint64_t helper_le_ldq_mmu(CPUArchState *env, target_ulong addr, |
9002ffcb | 1262 | MemOpIdx oi, uintptr_t retaddr); |
867b3201 | 1263 | tcg_target_ulong helper_be_lduw_mmu(CPUArchState *env, target_ulong addr, |
9002ffcb | 1264 | MemOpIdx oi, uintptr_t retaddr); |
867b3201 | 1265 | tcg_target_ulong helper_be_ldul_mmu(CPUArchState *env, target_ulong addr, |
9002ffcb | 1266 | MemOpIdx oi, uintptr_t retaddr); |
867b3201 | 1267 | uint64_t helper_be_ldq_mmu(CPUArchState *env, target_ulong addr, |
9002ffcb | 1268 | MemOpIdx oi, uintptr_t retaddr); |
e58eb534 | 1269 | |
c8f94df5 RH |
1270 | /* Value sign-extended to tcg register size. */ |
1271 | tcg_target_ulong helper_ret_ldsb_mmu(CPUArchState *env, target_ulong addr, | |
9002ffcb | 1272 | MemOpIdx oi, uintptr_t retaddr); |
867b3201 | 1273 | tcg_target_ulong helper_le_ldsw_mmu(CPUArchState *env, target_ulong addr, |
9002ffcb | 1274 | MemOpIdx oi, uintptr_t retaddr); |
867b3201 | 1275 | tcg_target_ulong helper_le_ldsl_mmu(CPUArchState *env, target_ulong addr, |
9002ffcb | 1276 | MemOpIdx oi, uintptr_t retaddr); |
867b3201 | 1277 | tcg_target_ulong helper_be_ldsw_mmu(CPUArchState *env, target_ulong addr, |
9002ffcb | 1278 | MemOpIdx oi, uintptr_t retaddr); |
867b3201 | 1279 | tcg_target_ulong helper_be_ldsl_mmu(CPUArchState *env, target_ulong addr, |
9002ffcb | 1280 | MemOpIdx oi, uintptr_t retaddr); |
c8f94df5 | 1281 | |
e58eb534 | 1282 | void helper_ret_stb_mmu(CPUArchState *env, target_ulong addr, uint8_t val, |
9002ffcb | 1283 | MemOpIdx oi, uintptr_t retaddr); |
867b3201 | 1284 | void helper_le_stw_mmu(CPUArchState *env, target_ulong addr, uint16_t val, |
9002ffcb | 1285 | MemOpIdx oi, uintptr_t retaddr); |
867b3201 | 1286 | void helper_le_stl_mmu(CPUArchState *env, target_ulong addr, uint32_t val, |
9002ffcb | 1287 | MemOpIdx oi, uintptr_t retaddr); |
867b3201 | 1288 | void helper_le_stq_mmu(CPUArchState *env, target_ulong addr, uint64_t val, |
9002ffcb | 1289 | MemOpIdx oi, uintptr_t retaddr); |
867b3201 | 1290 | void helper_be_stw_mmu(CPUArchState *env, target_ulong addr, uint16_t val, |
9002ffcb | 1291 | MemOpIdx oi, uintptr_t retaddr); |
867b3201 | 1292 | void helper_be_stl_mmu(CPUArchState *env, target_ulong addr, uint32_t val, |
9002ffcb | 1293 | MemOpIdx oi, uintptr_t retaddr); |
867b3201 | 1294 | void helper_be_stq_mmu(CPUArchState *env, target_ulong addr, uint64_t val, |
9002ffcb | 1295 | MemOpIdx oi, uintptr_t retaddr); |
867b3201 RH |
1296 | |
1297 | /* Temporary aliases until backends are converted. */ | |
1298 | #ifdef TARGET_WORDS_BIGENDIAN | |
1299 | # define helper_ret_ldsw_mmu helper_be_ldsw_mmu | |
1300 | # define helper_ret_lduw_mmu helper_be_lduw_mmu | |
1301 | # define helper_ret_ldsl_mmu helper_be_ldsl_mmu | |
1302 | # define helper_ret_ldul_mmu helper_be_ldul_mmu | |
282dffc8 | 1303 | # define helper_ret_ldl_mmu helper_be_ldul_mmu |
867b3201 RH |
1304 | # define helper_ret_ldq_mmu helper_be_ldq_mmu |
1305 | # define helper_ret_stw_mmu helper_be_stw_mmu | |
1306 | # define helper_ret_stl_mmu helper_be_stl_mmu | |
1307 | # define helper_ret_stq_mmu helper_be_stq_mmu | |
1308 | #else | |
1309 | # define helper_ret_ldsw_mmu helper_le_ldsw_mmu | |
1310 | # define helper_ret_lduw_mmu helper_le_lduw_mmu | |
1311 | # define helper_ret_ldsl_mmu helper_le_ldsl_mmu | |
1312 | # define helper_ret_ldul_mmu helper_le_ldul_mmu | |
282dffc8 | 1313 | # define helper_ret_ldl_mmu helper_le_ldul_mmu |
867b3201 RH |
1314 | # define helper_ret_ldq_mmu helper_le_ldq_mmu |
1315 | # define helper_ret_stw_mmu helper_le_stw_mmu | |
1316 | # define helper_ret_stl_mmu helper_le_stl_mmu | |
1317 | # define helper_ret_stq_mmu helper_le_stq_mmu | |
1318 | #endif | |
be9568b4 | 1319 | #endif /* CONFIG_SOFTMMU */ |
e58eb534 | 1320 | |
be9568b4 RH |
1321 | uint32_t cpu_atomic_cmpxchgb_mmu(CPUArchState *env, target_ulong addr, |
1322 | uint32_t cmpv, uint32_t newv, | |
9002ffcb | 1323 | MemOpIdx oi, uintptr_t retaddr); |
be9568b4 RH |
1324 | uint32_t cpu_atomic_cmpxchgw_le_mmu(CPUArchState *env, target_ulong addr, |
1325 | uint32_t cmpv, uint32_t newv, | |
9002ffcb | 1326 | MemOpIdx oi, uintptr_t retaddr); |
be9568b4 | 1327 | uint32_t cpu_atomic_cmpxchgl_le_mmu(CPUArchState *env, target_ulong addr, |
c482cb11 | 1328 | uint32_t cmpv, uint32_t newv, |
9002ffcb | 1329 | MemOpIdx oi, uintptr_t retaddr); |
be9568b4 RH |
1330 | uint64_t cpu_atomic_cmpxchgq_le_mmu(CPUArchState *env, target_ulong addr, |
1331 | uint64_t cmpv, uint64_t newv, | |
9002ffcb | 1332 | MemOpIdx oi, uintptr_t retaddr); |
be9568b4 RH |
1333 | uint32_t cpu_atomic_cmpxchgw_be_mmu(CPUArchState *env, target_ulong addr, |
1334 | uint32_t cmpv, uint32_t newv, | |
9002ffcb | 1335 | MemOpIdx oi, uintptr_t retaddr); |
be9568b4 RH |
1336 | uint32_t cpu_atomic_cmpxchgl_be_mmu(CPUArchState *env, target_ulong addr, |
1337 | uint32_t cmpv, uint32_t newv, | |
9002ffcb | 1338 | MemOpIdx oi, uintptr_t retaddr); |
be9568b4 RH |
1339 | uint64_t cpu_atomic_cmpxchgq_be_mmu(CPUArchState *env, target_ulong addr, |
1340 | uint64_t cmpv, uint64_t newv, | |
9002ffcb | 1341 | MemOpIdx oi, uintptr_t retaddr); |
c482cb11 RH |
1342 | |
1343 | #define GEN_ATOMIC_HELPER(NAME, TYPE, SUFFIX) \ | |
be9568b4 | 1344 | TYPE cpu_atomic_ ## NAME ## SUFFIX ## _mmu \ |
c482cb11 | 1345 | (CPUArchState *env, target_ulong addr, TYPE val, \ |
9002ffcb | 1346 | MemOpIdx oi, uintptr_t retaddr); |
c482cb11 | 1347 | |
df79b996 | 1348 | #ifdef CONFIG_ATOMIC64 |
c482cb11 | 1349 | #define GEN_ATOMIC_HELPER_ALL(NAME) \ |
df79b996 | 1350 | GEN_ATOMIC_HELPER(NAME, uint32_t, b) \ |
c482cb11 | 1351 | GEN_ATOMIC_HELPER(NAME, uint32_t, w_le) \ |
c482cb11 | 1352 | GEN_ATOMIC_HELPER(NAME, uint32_t, w_be) \ |
df79b996 | 1353 | GEN_ATOMIC_HELPER(NAME, uint32_t, l_le) \ |
c482cb11 | 1354 | GEN_ATOMIC_HELPER(NAME, uint32_t, l_be) \ |
df79b996 | 1355 | GEN_ATOMIC_HELPER(NAME, uint64_t, q_le) \ |
c482cb11 | 1356 | GEN_ATOMIC_HELPER(NAME, uint64_t, q_be) |
df79b996 RH |
1357 | #else |
1358 | #define GEN_ATOMIC_HELPER_ALL(NAME) \ | |
1359 | GEN_ATOMIC_HELPER(NAME, uint32_t, b) \ | |
1360 | GEN_ATOMIC_HELPER(NAME, uint32_t, w_le) \ | |
1361 | GEN_ATOMIC_HELPER(NAME, uint32_t, w_be) \ | |
1362 | GEN_ATOMIC_HELPER(NAME, uint32_t, l_le) \ | |
1363 | GEN_ATOMIC_HELPER(NAME, uint32_t, l_be) | |
1364 | #endif | |
c482cb11 RH |
1365 | |
1366 | GEN_ATOMIC_HELPER_ALL(fetch_add) | |
1367 | GEN_ATOMIC_HELPER_ALL(fetch_sub) | |
1368 | GEN_ATOMIC_HELPER_ALL(fetch_and) | |
1369 | GEN_ATOMIC_HELPER_ALL(fetch_or) | |
1370 | GEN_ATOMIC_HELPER_ALL(fetch_xor) | |
5507c2bf RH |
1371 | GEN_ATOMIC_HELPER_ALL(fetch_smin) |
1372 | GEN_ATOMIC_HELPER_ALL(fetch_umin) | |
1373 | GEN_ATOMIC_HELPER_ALL(fetch_smax) | |
1374 | GEN_ATOMIC_HELPER_ALL(fetch_umax) | |
c482cb11 RH |
1375 | |
1376 | GEN_ATOMIC_HELPER_ALL(add_fetch) | |
1377 | GEN_ATOMIC_HELPER_ALL(sub_fetch) | |
1378 | GEN_ATOMIC_HELPER_ALL(and_fetch) | |
1379 | GEN_ATOMIC_HELPER_ALL(or_fetch) | |
1380 | GEN_ATOMIC_HELPER_ALL(xor_fetch) | |
5507c2bf RH |
1381 | GEN_ATOMIC_HELPER_ALL(smin_fetch) |
1382 | GEN_ATOMIC_HELPER_ALL(umin_fetch) | |
1383 | GEN_ATOMIC_HELPER_ALL(smax_fetch) | |
1384 | GEN_ATOMIC_HELPER_ALL(umax_fetch) | |
c482cb11 RH |
1385 | |
1386 | GEN_ATOMIC_HELPER_ALL(xchg) | |
1387 | ||
1388 | #undef GEN_ATOMIC_HELPER_ALL | |
1389 | #undef GEN_ATOMIC_HELPER | |
e58eb534 | 1390 | |
be9568b4 RH |
1391 | Int128 cpu_atomic_cmpxchgo_le_mmu(CPUArchState *env, target_ulong addr, |
1392 | Int128 cmpv, Int128 newv, | |
9002ffcb | 1393 | MemOpIdx oi, uintptr_t retaddr); |
be9568b4 RH |
1394 | Int128 cpu_atomic_cmpxchgo_be_mmu(CPUArchState *env, target_ulong addr, |
1395 | Int128 cmpv, Int128 newv, | |
9002ffcb | 1396 | MemOpIdx oi, uintptr_t retaddr); |
be9568b4 RH |
1397 | |
1398 | Int128 cpu_atomic_ldo_le_mmu(CPUArchState *env, target_ulong addr, | |
9002ffcb | 1399 | MemOpIdx oi, uintptr_t retaddr); |
be9568b4 | 1400 | Int128 cpu_atomic_ldo_be_mmu(CPUArchState *env, target_ulong addr, |
9002ffcb | 1401 | MemOpIdx oi, uintptr_t retaddr); |
be9568b4 | 1402 | void cpu_atomic_sto_le_mmu(CPUArchState *env, target_ulong addr, Int128 val, |
9002ffcb | 1403 | MemOpIdx oi, uintptr_t retaddr); |
be9568b4 | 1404 | void cpu_atomic_sto_be_mmu(CPUArchState *env, target_ulong addr, Int128 val, |
9002ffcb | 1405 | MemOpIdx oi, uintptr_t retaddr); |
7ebee43e | 1406 | |
53229a77 RH |
1407 | #ifdef CONFIG_DEBUG_TCG |
1408 | void tcg_assert_listed_vecop(TCGOpcode); | |
1409 | #else | |
1410 | static inline void tcg_assert_listed_vecop(TCGOpcode op) { } | |
1411 | #endif | |
1412 | ||
1413 | static inline const TCGOpcode *tcg_swap_vecop_list(const TCGOpcode *n) | |
1414 | { | |
1415 | #ifdef CONFIG_DEBUG_TCG | |
1416 | const TCGOpcode *o = tcg_ctx->vecop_list; | |
1417 | tcg_ctx->vecop_list = n; | |
1418 | return o; | |
1419 | #else | |
1420 | return NULL; | |
1421 | #endif | |
1422 | } | |
1423 | ||
1424 | bool tcg_can_emit_vecop_list(const TCGOpcode *, TCGType, unsigned); | |
1425 | ||
e58eb534 | 1426 | #endif /* TCG_H */ |