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Commit | Line | Data |
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c896fe29 FB |
1 | /* |
2 | * Tiny Code Generator for QEMU | |
3 | * | |
4 | * Copyright (c) 2008 Fabrice Bellard | |
5 | * | |
6 | * Permission is hereby granted, free of charge, to any person obtaining a copy | |
7 | * of this software and associated documentation files (the "Software"), to deal | |
8 | * in the Software without restriction, including without limitation the rights | |
9 | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell | |
10 | * copies of the Software, and to permit persons to whom the Software is | |
11 | * furnished to do so, subject to the following conditions: | |
12 | * | |
13 | * The above copyright notice and this permission notice shall be included in | |
14 | * all copies or substantial portions of the Software. | |
15 | * | |
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
19 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
20 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, | |
21 | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN | |
22 | * THE SOFTWARE. | |
23 | */ | |
e58eb534 RH |
24 | |
25 | #ifndef TCG_H | |
26 | #define TCG_H | |
27 | ||
14776ab5 | 28 | #include "exec/memop.h" |
abe2e23e | 29 | #include "exec/memopidx.h" |
0ec9eabc | 30 | #include "qemu/bitops.h" |
e6d86bed | 31 | #include "qemu/plugin.h" |
15fa08f8 | 32 | #include "qemu/queue.h" |
dcb32f1d | 33 | #include "tcg/tcg-mo.h" |
d46259c0 | 34 | #include "tcg-target-reg-bits.h" |
78cd7b83 | 35 | #include "tcg-target.h" |
9ca03622 | 36 | #include "tcg/tcg-cond.h" |
427fbf37 | 37 | #include "tcg/debug-assert.h" |
78cd7b83 | 38 | |
00f6da6a PB |
39 | /* XXX: make safe guess about sizes */ |
40 | #define MAX_OP_PER_INSTR 266 | |
41 | ||
39004a71 RH |
42 | #define MAX_CALL_IARGS 7 |
43 | ||
6e0b0730 | 44 | #define CPU_TEMP_BUF_NLONGS 128 |
7b7d8b2d | 45 | #define TCG_STATIC_FRAME_SIZE (CPU_TEMP_BUF_NLONGS * sizeof(long)) |
6e0b0730 | 46 | |
c896fe29 FB |
47 | #if TCG_TARGET_REG_BITS == 32 |
48 | typedef int32_t tcg_target_long; | |
49 | typedef uint32_t tcg_target_ulong; | |
50 | #define TCG_PRIlx PRIx32 | |
51 | #define TCG_PRIld PRId32 | |
52 | #elif TCG_TARGET_REG_BITS == 64 | |
53 | typedef int64_t tcg_target_long; | |
54 | typedef uint64_t tcg_target_ulong; | |
55 | #define TCG_PRIlx PRIx64 | |
56 | #define TCG_PRIld PRId64 | |
57 | #else | |
58 | #error unsupported | |
59 | #endif | |
60 | ||
61 | #if TCG_TARGET_NB_REGS <= 32 | |
62 | typedef uint32_t TCGRegSet; | |
63 | #elif TCG_TARGET_NB_REGS <= 64 | |
64 | typedef uint64_t TCGRegSet; | |
65 | #else | |
66 | #error unsupported | |
67 | #endif | |
68 | ||
25c4d9cc | 69 | #if TCG_TARGET_REG_BITS == 32 |
e6a72734 | 70 | /* Turn some undef macros into false macros. */ |
13d885b0 | 71 | #define TCG_TARGET_HAS_extr_i64_i32 0 |
25c4d9cc | 72 | #define TCG_TARGET_HAS_div_i64 0 |
ca675f46 | 73 | #define TCG_TARGET_HAS_rem_i64 0 |
25c4d9cc RH |
74 | #define TCG_TARGET_HAS_div2_i64 0 |
75 | #define TCG_TARGET_HAS_rot_i64 0 | |
76 | #define TCG_TARGET_HAS_ext8s_i64 0 | |
77 | #define TCG_TARGET_HAS_ext16s_i64 0 | |
78 | #define TCG_TARGET_HAS_ext32s_i64 0 | |
79 | #define TCG_TARGET_HAS_ext8u_i64 0 | |
80 | #define TCG_TARGET_HAS_ext16u_i64 0 | |
81 | #define TCG_TARGET_HAS_ext32u_i64 0 | |
82 | #define TCG_TARGET_HAS_bswap16_i64 0 | |
83 | #define TCG_TARGET_HAS_bswap32_i64 0 | |
84 | #define TCG_TARGET_HAS_bswap64_i64 0 | |
85 | #define TCG_TARGET_HAS_neg_i64 0 | |
86 | #define TCG_TARGET_HAS_not_i64 0 | |
87 | #define TCG_TARGET_HAS_andc_i64 0 | |
88 | #define TCG_TARGET_HAS_orc_i64 0 | |
89 | #define TCG_TARGET_HAS_eqv_i64 0 | |
90 | #define TCG_TARGET_HAS_nand_i64 0 | |
91 | #define TCG_TARGET_HAS_nor_i64 0 | |
0e28d006 RH |
92 | #define TCG_TARGET_HAS_clz_i64 0 |
93 | #define TCG_TARGET_HAS_ctz_i64 0 | |
a768e4e9 | 94 | #define TCG_TARGET_HAS_ctpop_i64 0 |
25c4d9cc | 95 | #define TCG_TARGET_HAS_deposit_i64 0 |
7ec8bab3 RH |
96 | #define TCG_TARGET_HAS_extract_i64 0 |
97 | #define TCG_TARGET_HAS_sextract_i64 0 | |
fce1296f | 98 | #define TCG_TARGET_HAS_extract2_i64 0 |
ffc5ea09 | 99 | #define TCG_TARGET_HAS_movcond_i64 0 |
3635502d | 100 | #define TCG_TARGET_HAS_negsetcond_i64 0 |
d7156f7c RH |
101 | #define TCG_TARGET_HAS_add2_i64 0 |
102 | #define TCG_TARGET_HAS_sub2_i64 0 | |
103 | #define TCG_TARGET_HAS_mulu2_i64 0 | |
4d3203fd | 104 | #define TCG_TARGET_HAS_muls2_i64 0 |
03271524 RH |
105 | #define TCG_TARGET_HAS_muluh_i64 0 |
106 | #define TCG_TARGET_HAS_mulsh_i64 0 | |
e6a72734 RH |
107 | /* Turn some undef macros into true macros. */ |
108 | #define TCG_TARGET_HAS_add2_i32 1 | |
109 | #define TCG_TARGET_HAS_sub2_i32 1 | |
25c4d9cc RH |
110 | #endif |
111 | ||
a4773324 JK |
112 | #ifndef TCG_TARGET_deposit_i32_valid |
113 | #define TCG_TARGET_deposit_i32_valid(ofs, len) 1 | |
114 | #endif | |
115 | #ifndef TCG_TARGET_deposit_i64_valid | |
116 | #define TCG_TARGET_deposit_i64_valid(ofs, len) 1 | |
117 | #endif | |
7ec8bab3 RH |
118 | #ifndef TCG_TARGET_extract_i32_valid |
119 | #define TCG_TARGET_extract_i32_valid(ofs, len) 1 | |
120 | #endif | |
121 | #ifndef TCG_TARGET_extract_i64_valid | |
122 | #define TCG_TARGET_extract_i64_valid(ofs, len) 1 | |
123 | #endif | |
a4773324 | 124 | |
25c4d9cc RH |
125 | /* Only one of DIV or DIV2 should be defined. */ |
126 | #if defined(TCG_TARGET_HAS_div_i32) | |
127 | #define TCG_TARGET_HAS_div2_i32 0 | |
128 | #elif defined(TCG_TARGET_HAS_div2_i32) | |
129 | #define TCG_TARGET_HAS_div_i32 0 | |
ca675f46 | 130 | #define TCG_TARGET_HAS_rem_i32 0 |
25c4d9cc RH |
131 | #endif |
132 | #if defined(TCG_TARGET_HAS_div_i64) | |
133 | #define TCG_TARGET_HAS_div2_i64 0 | |
134 | #elif defined(TCG_TARGET_HAS_div2_i64) | |
135 | #define TCG_TARGET_HAS_div_i64 0 | |
ca675f46 | 136 | #define TCG_TARGET_HAS_rem_i64 0 |
25c4d9cc RH |
137 | #endif |
138 | ||
d2fd745f RH |
139 | #if !defined(TCG_TARGET_HAS_v64) \ |
140 | && !defined(TCG_TARGET_HAS_v128) \ | |
141 | && !defined(TCG_TARGET_HAS_v256) | |
142 | #define TCG_TARGET_MAYBE_vec 0 | |
bcefc902 | 143 | #define TCG_TARGET_HAS_abs_vec 0 |
d2fd745f RH |
144 | #define TCG_TARGET_HAS_neg_vec 0 |
145 | #define TCG_TARGET_HAS_not_vec 0 | |
146 | #define TCG_TARGET_HAS_andc_vec 0 | |
147 | #define TCG_TARGET_HAS_orc_vec 0 | |
ed523473 RH |
148 | #define TCG_TARGET_HAS_nand_vec 0 |
149 | #define TCG_TARGET_HAS_nor_vec 0 | |
150 | #define TCG_TARGET_HAS_eqv_vec 0 | |
b0f7e744 | 151 | #define TCG_TARGET_HAS_roti_vec 0 |
23850a74 | 152 | #define TCG_TARGET_HAS_rots_vec 0 |
5d0ceda9 | 153 | #define TCG_TARGET_HAS_rotv_vec 0 |
d0ec9796 RH |
154 | #define TCG_TARGET_HAS_shi_vec 0 |
155 | #define TCG_TARGET_HAS_shs_vec 0 | |
156 | #define TCG_TARGET_HAS_shv_vec 0 | |
3774030a | 157 | #define TCG_TARGET_HAS_mul_vec 0 |
8afaf050 | 158 | #define TCG_TARGET_HAS_sat_vec 0 |
dd0a0fcd | 159 | #define TCG_TARGET_HAS_minmax_vec 0 |
38dc1294 | 160 | #define TCG_TARGET_HAS_bitsel_vec 0 |
f75da298 | 161 | #define TCG_TARGET_HAS_cmpsel_vec 0 |
d2fd745f RH |
162 | #else |
163 | #define TCG_TARGET_MAYBE_vec 1 | |
164 | #endif | |
165 | #ifndef TCG_TARGET_HAS_v64 | |
166 | #define TCG_TARGET_HAS_v64 0 | |
167 | #endif | |
168 | #ifndef TCG_TARGET_HAS_v128 | |
169 | #define TCG_TARGET_HAS_v128 0 | |
170 | #endif | |
171 | #ifndef TCG_TARGET_HAS_v256 | |
172 | #define TCG_TARGET_HAS_v256 0 | |
173 | #endif | |
174 | ||
a9751609 | 175 | typedef enum TCGOpcode { |
c61aaf7a | 176 | #define DEF(name, oargs, iargs, cargs, flags) INDEX_op_ ## name, |
dcb32f1d | 177 | #include "tcg/tcg-opc.h" |
c896fe29 FB |
178 | #undef DEF |
179 | NB_OPS, | |
a9751609 | 180 | } TCGOpcode; |
c896fe29 | 181 | |
80a8b9a9 RH |
182 | #define tcg_regset_set_reg(d, r) ((d) |= (TCGRegSet)1 << (r)) |
183 | #define tcg_regset_reset_reg(d, r) ((d) &= ~((TCGRegSet)1 << (r))) | |
184 | #define tcg_regset_test_reg(d, r) (((d) >> (r)) & 1) | |
c896fe29 | 185 | |
1813e175 | 186 | #ifndef TCG_TARGET_INSN_UNIT_SIZE |
5053361b RH |
187 | # error "Missing TCG_TARGET_INSN_UNIT_SIZE" |
188 | #elif TCG_TARGET_INSN_UNIT_SIZE == 1 | |
1813e175 RH |
189 | typedef uint8_t tcg_insn_unit; |
190 | #elif TCG_TARGET_INSN_UNIT_SIZE == 2 | |
191 | typedef uint16_t tcg_insn_unit; | |
192 | #elif TCG_TARGET_INSN_UNIT_SIZE == 4 | |
193 | typedef uint32_t tcg_insn_unit; | |
194 | #elif TCG_TARGET_INSN_UNIT_SIZE == 8 | |
195 | typedef uint64_t tcg_insn_unit; | |
196 | #else | |
197 | /* The port better have done this. */ | |
198 | #endif | |
199 | ||
7ecd02a0 RH |
200 | typedef struct TCGRelocation TCGRelocation; |
201 | struct TCGRelocation { | |
202 | QSIMPLEQ_ENTRY(TCGRelocation) next; | |
1813e175 | 203 | tcg_insn_unit *ptr; |
2ba7fae2 | 204 | intptr_t addend; |
7ecd02a0 RH |
205 | int type; |
206 | }; | |
c896fe29 | 207 | |
f85b1fc4 RH |
208 | typedef struct TCGOp TCGOp; |
209 | typedef struct TCGLabelUse TCGLabelUse; | |
210 | struct TCGLabelUse { | |
211 | QSIMPLEQ_ENTRY(TCGLabelUse) next; | |
212 | TCGOp *op; | |
213 | }; | |
214 | ||
bef16ab4 RH |
215 | typedef struct TCGLabel TCGLabel; |
216 | struct TCGLabel { | |
f85b1fc4 RH |
217 | bool present; |
218 | bool has_value; | |
219 | uint16_t id; | |
c896fe29 | 220 | union { |
2ba7fae2 | 221 | uintptr_t value; |
ffd0e507 | 222 | const tcg_insn_unit *value_ptr; |
c896fe29 | 223 | } u; |
f85b1fc4 | 224 | QSIMPLEQ_HEAD(, TCGLabelUse) branches; |
7ecd02a0 | 225 | QSIMPLEQ_HEAD(, TCGRelocation) relocs; |
bef16ab4 | 226 | QSIMPLEQ_ENTRY(TCGLabel) next; |
bef16ab4 | 227 | }; |
c896fe29 FB |
228 | |
229 | typedef struct TCGPool { | |
230 | struct TCGPool *next; | |
c44f945a | 231 | int size; |
f7795e40 | 232 | uint8_t data[] __attribute__ ((aligned)); |
c896fe29 FB |
233 | } TCGPool; |
234 | ||
235 | #define TCG_POOL_CHUNK_SIZE 32768 | |
236 | ||
c4071c90 | 237 | #define TCG_MAX_TEMPS 512 |
190ce7fb | 238 | #define TCG_MAX_INSNS 512 |
c896fe29 | 239 | |
b03cce8e FB |
240 | /* when the size of the arguments of a called function is smaller than |
241 | this value, they are statically allocated in the TB stack frame */ | |
242 | #define TCG_STATIC_CALL_ARGS_SIZE 128 | |
243 | ||
c02244a5 RH |
244 | typedef enum TCGType { |
245 | TCG_TYPE_I32, | |
246 | TCG_TYPE_I64, | |
ecbea3ec | 247 | TCG_TYPE_I128, |
d2fd745f RH |
248 | |
249 | TCG_TYPE_V64, | |
250 | TCG_TYPE_V128, | |
251 | TCG_TYPE_V256, | |
252 | ||
89496a85 RH |
253 | /* Number of different types (integer not enum) */ |
254 | #define TCG_TYPE_COUNT (TCG_TYPE_V256 + 1) | |
c896fe29 | 255 | |
3b6dac34 | 256 | /* An alias for the size of the host register. */ |
c896fe29 | 257 | #if TCG_TARGET_REG_BITS == 32 |
3b6dac34 | 258 | TCG_TYPE_REG = TCG_TYPE_I32, |
c02244a5 | 259 | #else |
3b6dac34 | 260 | TCG_TYPE_REG = TCG_TYPE_I64, |
c02244a5 | 261 | #endif |
3b6dac34 | 262 | |
d289837e RH |
263 | /* An alias for the size of the native pointer. */ |
264 | #if UINTPTR_MAX == UINT32_MAX | |
265 | TCG_TYPE_PTR = TCG_TYPE_I32, | |
266 | #else | |
267 | TCG_TYPE_PTR = TCG_TYPE_I64, | |
268 | #endif | |
c02244a5 | 269 | } TCGType; |
c896fe29 | 270 | |
31c96417 RH |
271 | /** |
272 | * tcg_type_size | |
273 | * @t: type | |
274 | * | |
275 | * Return the size of the type in bytes. | |
276 | */ | |
277 | static inline int tcg_type_size(TCGType t) | |
278 | { | |
279 | unsigned i = t; | |
280 | if (i >= TCG_TYPE_V64) { | |
281 | tcg_debug_assert(i < TCG_TYPE_COUNT); | |
282 | i -= TCG_TYPE_V64 - 1; | |
283 | } | |
284 | return 4 << i; | |
285 | } | |
286 | ||
1f00b27f SS |
287 | /** |
288 | * get_alignment_bits | |
14776ab5 | 289 | * @memop: MemOp value |
1f00b27f SS |
290 | * |
291 | * Extract the alignment size from the memop. | |
1f00b27f | 292 | */ |
14776ab5 | 293 | static inline unsigned get_alignment_bits(MemOp memop) |
1f00b27f | 294 | { |
85aa8081 | 295 | unsigned a = memop & MO_AMASK; |
1f00b27f SS |
296 | |
297 | if (a == MO_UNALN) { | |
85aa8081 RH |
298 | /* No alignment required. */ |
299 | a = 0; | |
1f00b27f | 300 | } else if (a == MO_ALIGN) { |
85aa8081 RH |
301 | /* A natural alignment requirement. */ |
302 | a = memop & MO_SIZE; | |
1f00b27f | 303 | } else { |
85aa8081 RH |
304 | /* A specific alignment requirement. */ |
305 | a = a >> MO_ASHIFT; | |
1f00b27f | 306 | } |
85aa8081 | 307 | return a; |
1f00b27f SS |
308 | } |
309 | ||
c896fe29 FB |
310 | typedef tcg_target_ulong TCGArg; |
311 | ||
a40d4701 PM |
312 | /* Define type and accessor macros for TCG variables. |
313 | ||
314 | TCG variables are the inputs and outputs of TCG ops, as described | |
315 | in tcg/README. Target CPU front-end code uses these types to deal | |
316 | with TCG variables as it emits TCG code via the tcg_gen_* functions. | |
317 | They come in several flavours: | |
ecbea3ec RH |
318 | * TCGv_i32 : 32 bit integer type |
319 | * TCGv_i64 : 64 bit integer type | |
320 | * TCGv_i128 : 128 bit integer type | |
321 | * TCGv_ptr : a host pointer type | |
322 | * TCGv_vec : a host vector type; the exact size is not exposed | |
323 | to the CPU front-end code. | |
324 | * TCGv : an integer type the same size as target_ulong | |
325 | (an alias for either TCGv_i32 or TCGv_i64) | |
a40d4701 PM |
326 | The compiler's type checking will complain if you mix them |
327 | up and pass the wrong sized TCGv to a function. | |
328 | ||
329 | Users of tcg_gen_* don't need to know about any of the internal | |
330 | details of these, and should treat them as opaque types. | |
331 | You won't be able to look inside them in a debugger either. | |
332 | ||
333 | Internal implementation details follow: | |
334 | ||
335 | Note that there is no definition of the structs TCGv_i32_d etc anywhere. | |
336 | This is deliberate, because the values we store in variables of type | |
337 | TCGv_i32 are not really pointers-to-structures. They're just small | |
338 | integers, but keeping them in pointer types like this means that the | |
339 | compiler will complain if you accidentally pass a TCGv_i32 to a | |
340 | function which takes a TCGv_i64, and so on. Only the internals of | |
dc41aa7d | 341 | TCG need to care about the actual contents of the types. */ |
ac56dd48 | 342 | |
b6c73a6d RH |
343 | typedef struct TCGv_i32_d *TCGv_i32; |
344 | typedef struct TCGv_i64_d *TCGv_i64; | |
ecbea3ec | 345 | typedef struct TCGv_i128_d *TCGv_i128; |
b6c73a6d | 346 | typedef struct TCGv_ptr_d *TCGv_ptr; |
d2fd745f | 347 | typedef struct TCGv_vec_d *TCGv_vec; |
1bcea73e | 348 | typedef TCGv_ptr TCGv_env; |
ac56dd48 | 349 | |
c896fe29 | 350 | /* call flags */ |
78505279 AJ |
351 | /* Helper does not read globals (either directly or through an exception). It |
352 | implies TCG_CALL_NO_WRITE_GLOBALS. */ | |
3b50352b | 353 | #define TCG_CALL_NO_READ_GLOBALS 0x0001 |
78505279 | 354 | /* Helper does not write globals */ |
3b50352b | 355 | #define TCG_CALL_NO_WRITE_GLOBALS 0x0002 |
78505279 | 356 | /* Helper can be safely suppressed if the return value is not used. */ |
3b50352b | 357 | #define TCG_CALL_NO_SIDE_EFFECTS 0x0004 |
8905770b | 358 | /* Helper is G_NORETURN. */ |
15d74092 | 359 | #define TCG_CALL_NO_RETURN 0x0008 |
17083f6f EC |
360 | /* Helper is part of Plugins. */ |
361 | #define TCG_CALL_PLUGIN 0x0010 | |
78505279 AJ |
362 | |
363 | /* convenience version of most used call flags */ | |
364 | #define TCG_CALL_NO_RWG TCG_CALL_NO_READ_GLOBALS | |
365 | #define TCG_CALL_NO_WG TCG_CALL_NO_WRITE_GLOBALS | |
366 | #define TCG_CALL_NO_SE TCG_CALL_NO_SIDE_EFFECTS | |
367 | #define TCG_CALL_NO_RWG_SE (TCG_CALL_NO_RWG | TCG_CALL_NO_SE) | |
368 | #define TCG_CALL_NO_WG_SE (TCG_CALL_NO_WG | TCG_CALL_NO_SE) | |
369 | ||
587195bd RH |
370 | /* |
371 | * Flags for the bswap opcodes. | |
372 | * If IZ, the input is zero-extended, otherwise unknown. | |
373 | * If OZ or OS, the output is zero- or sign-extended respectively, | |
374 | * otherwise the high bits are undefined. | |
375 | */ | |
376 | enum { | |
377 | TCG_BSWAP_IZ = 1, | |
378 | TCG_BSWAP_OZ = 2, | |
379 | TCG_BSWAP_OS = 4, | |
380 | }; | |
381 | ||
00c8fa9f EC |
382 | typedef enum TCGTempVal { |
383 | TEMP_VAL_DEAD, | |
384 | TEMP_VAL_REG, | |
385 | TEMP_VAL_MEM, | |
386 | TEMP_VAL_CONST, | |
387 | } TCGTempVal; | |
c896fe29 | 388 | |
ee17db83 | 389 | typedef enum TCGTempKind { |
f57c6915 RH |
390 | /* |
391 | * Temp is dead at the end of the extended basic block (EBB), | |
392 | * the single-entry multiple-exit region that falls through | |
393 | * conditional branches. | |
394 | */ | |
c7482438 | 395 | TEMP_EBB, |
f57c6915 RH |
396 | /* Temp is live across the entire translation block, but dead at end. */ |
397 | TEMP_TB, | |
398 | /* Temp is live across the entire translation block, and between them. */ | |
ee17db83 RH |
399 | TEMP_GLOBAL, |
400 | /* Temp is in a fixed register. */ | |
401 | TEMP_FIXED, | |
c0522136 RH |
402 | /* Temp is a fixed constant. */ |
403 | TEMP_CONST, | |
ee17db83 RH |
404 | } TCGTempKind; |
405 | ||
c896fe29 | 406 | typedef struct TCGTemp { |
b6638662 | 407 | TCGReg reg:8; |
00c8fa9f EC |
408 | TCGTempVal val_type:8; |
409 | TCGType base_type:8; | |
410 | TCGType type:8; | |
ee17db83 | 411 | TCGTempKind kind:3; |
b3915dbb RH |
412 | unsigned int indirect_reg:1; |
413 | unsigned int indirect_base:1; | |
c896fe29 FB |
414 | unsigned int mem_coherent:1; |
415 | unsigned int mem_allocated:1; | |
fa477d25 | 416 | unsigned int temp_allocated:1; |
fac87bd2 | 417 | unsigned int temp_subindex:1; |
00c8fa9f | 418 | |
bdb38b95 | 419 | int64_t val; |
b3a62939 | 420 | struct TCGTemp *mem_base; |
00c8fa9f | 421 | intptr_t mem_offset; |
c896fe29 | 422 | const char *name; |
b83eabea RH |
423 | |
424 | /* Pass-specific information that can be stored for a temporary. | |
425 | One word worth of integer data, and one pointer to data | |
426 | allocated separately. */ | |
427 | uintptr_t state; | |
428 | void *state_ptr; | |
c896fe29 FB |
429 | } TCGTemp; |
430 | ||
c896fe29 FB |
431 | typedef struct TCGContext TCGContext; |
432 | ||
0ec9eabc RH |
433 | typedef struct TCGTempSet { |
434 | unsigned long l[BITS_TO_LONGS(TCG_MAX_TEMPS)]; | |
435 | } TCGTempSet; | |
436 | ||
cb10bc63 RH |
437 | /* |
438 | * With 1 128-bit output, a 32-bit host requires 4 output parameters, | |
439 | * which leaves a maximum of 28 other slots. Which is enough for 7 | |
440 | * 128-bit operands. | |
441 | */ | |
442 | #define DEAD_ARG (1 << 4) | |
443 | #define SYNC_ARG (1 << 0) | |
444 | typedef uint32_t TCGLifeData; | |
a1b3c48d | 445 | |
f85b1fc4 | 446 | struct TCGOp { |
cb10bc63 RH |
447 | TCGOpcode opc : 8; |
448 | unsigned nargs : 8; | |
bee158cb | 449 | |
cd9090aa | 450 | /* Parameters for this opcode. See below. */ |
cb10bc63 RH |
451 | unsigned param1 : 8; |
452 | unsigned param2 : 8; | |
c45cb8bb | 453 | |
bee158cb | 454 | /* Lifetime data of the operands. */ |
cb10bc63 | 455 | TCGLifeData life; |
15fa08f8 RH |
456 | |
457 | /* Next and previous opcodes. */ | |
458 | QTAILQ_ENTRY(TCGOp) link; | |
75e8b9b7 | 459 | |
69e3706d RH |
460 | /* Register preferences for the output(s). */ |
461 | TCGRegSet output_pref[2]; | |
cb10bc63 RH |
462 | |
463 | /* Arguments for the opcode. */ | |
464 | TCGArg args[]; | |
f85b1fc4 | 465 | }; |
c45cb8bb | 466 | |
cd9090aa RH |
467 | #define TCGOP_CALLI(X) (X)->param1 |
468 | #define TCGOP_CALLO(X) (X)->param2 | |
469 | ||
d2fd745f RH |
470 | #define TCGOP_VECL(X) (X)->param1 |
471 | #define TCGOP_VECE(X) (X)->param2 | |
472 | ||
dcb8e758 RH |
473 | /* Make sure operands fit in the bitfields above. */ |
474 | QEMU_BUILD_BUG_ON(NB_OPS > (1 << 8)); | |
c45cb8bb | 475 | |
31fd884b RH |
476 | static inline TCGRegSet output_pref(const TCGOp *op, unsigned i) |
477 | { | |
478 | return i < ARRAY_SIZE(op->output_pref) ? op->output_pref[i] : 0; | |
479 | } | |
480 | ||
c896fe29 FB |
481 | struct TCGContext { |
482 | uint8_t *pool_cur, *pool_end; | |
4055299e | 483 | TCGPool *pool_first, *pool_current, *pool_first_large; |
c896fe29 | 484 | int nb_labels; |
c896fe29 FB |
485 | int nb_globals; |
486 | int nb_temps; | |
5a18407f | 487 | int nb_indirects; |
abebf925 | 488 | int nb_ops; |
4baf3978 | 489 | TCGType addr_type; /* TCG_TYPE_I32 or TCG_TYPE_I64 */ |
c896fe29 | 490 | |
aece72b7 RH |
491 | #ifdef CONFIG_SOFTMMU |
492 | int page_mask; | |
493 | uint8_t page_bits; | |
a66efde1 | 494 | uint8_t tlb_dyn_max_bits; |
aece72b7 | 495 | #endif |
747bd69d | 496 | uint8_t insn_start_words; |
28ea568a | 497 | TCGBar guest_mo; |
aece72b7 | 498 | |
c896fe29 | 499 | TCGRegSet reserved_regs; |
e2c6d1b4 RH |
500 | intptr_t current_frame_offset; |
501 | intptr_t frame_start; | |
502 | intptr_t frame_end; | |
b3a62939 | 503 | TCGTemp *frame_temp; |
c896fe29 | 504 | |
b7e4afbd RH |
505 | TranslationBlock *gen_tb; /* tb for which code is being generated */ |
506 | tcg_insn_unit *code_buf; /* pointer for start of tb */ | |
507 | tcg_insn_unit *code_ptr; /* pointer for running end of tb */ | |
c896fe29 | 508 | |
27bfd83c | 509 | #ifdef CONFIG_DEBUG_TCG |
0a209d4b | 510 | int goto_tb_issue_mask; |
53229a77 | 511 | const TCGOpcode *vecop_list; |
27bfd83c | 512 | #endif |
b76f0d8c | 513 | |
1813e175 RH |
514 | /* Code generation. Note that we specifically do not use tcg_insn_unit |
515 | here, because there's too much arithmetic throughout that relies | |
516 | on addition and subtraction working on bytes. Rely on the GCC | |
517 | extension that allows arithmetic on void*. */ | |
1813e175 | 518 | void *code_gen_buffer; |
0b0d3320 | 519 | size_t code_gen_buffer_size; |
1813e175 | 520 | void *code_gen_ptr; |
57a26946 | 521 | void *data_gen_ptr; |
0b0d3320 | 522 | |
b125f9dc RH |
523 | /* Threshold to flush the translated code buffer. */ |
524 | void *code_gen_highwater; | |
525 | ||
7c255043 LV |
526 | /* Track which vCPU triggers events */ |
527 | CPUState *cpu; /* *_trans */ | |
7c255043 | 528 | |
139c1837 | 529 | /* These structures are private to tcg-target.c.inc. */ |
659ef5cb | 530 | #ifdef TCG_TARGET_NEED_LDST_LABELS |
b58deb34 | 531 | QSIMPLEQ_HEAD(, TCGLabelQemuLdst) ldst_labels; |
659ef5cb | 532 | #endif |
57a26946 RH |
533 | #ifdef TCG_TARGET_NEED_POOL_LABELS |
534 | struct TCGLabelPoolData *pool_labels; | |
535 | #endif | |
c45cb8bb | 536 | |
26689780 EC |
537 | TCGLabel *exitreq_label; |
538 | ||
38b47b19 EC |
539 | #ifdef CONFIG_PLUGIN |
540 | /* | |
541 | * We keep one plugin_tb struct per TCGContext. Note that on every TB | |
542 | * translation we clear but do not free its contents; this way we | |
543 | * avoid a lot of malloc/free churn, since after a few TB's it's | |
544 | * unlikely that we'll need to allocate either more instructions or more | |
545 | * space for instructions (for variable-instruction-length ISAs). | |
546 | */ | |
547 | struct qemu_plugin_tb *plugin_tb; | |
548 | ||
549 | /* descriptor of the instruction being translated */ | |
550 | struct qemu_plugin_insn *plugin_insn; | |
38b47b19 EC |
551 | #endif |
552 | ||
c0522136 | 553 | GHashTable *const_table[TCG_TYPE_COUNT]; |
e1c08b00 | 554 | TCGTempSet free_temps[TCG_TYPE_COUNT]; |
c45cb8bb RH |
555 | TCGTemp temps[TCG_MAX_TEMPS]; /* globals first, temps after */ |
556 | ||
eae3eb3e | 557 | QTAILQ_HEAD(, TCGOp) ops, free_ops; |
7ecd02a0 | 558 | QSIMPLEQ_HEAD(, TCGLabel) labels; |
15fa08f8 | 559 | |
f8b2f202 RH |
560 | /* Tells which temporary holds a given register. |
561 | It does not take into account fixed registers */ | |
562 | TCGTemp *reg_to_temp[TCG_TARGET_NB_REGS]; | |
c45cb8bb | 563 | |
fca8a500 | 564 | uint16_t gen_insn_end_off[TCG_MAX_INSNS]; |
747bd69d | 565 | uint64_t *gen_insn_data; |
ae30e866 RH |
566 | |
567 | /* Exit to translator on overflow. */ | |
568 | sigjmp_buf jmp_trans; | |
c896fe29 FB |
569 | }; |
570 | ||
e01fa97d RH |
571 | static inline bool temp_readonly(TCGTemp *ts) |
572 | { | |
c0522136 | 573 | return ts->kind >= TEMP_FIXED; |
e01fa97d RH |
574 | } |
575 | ||
3468b59e | 576 | extern __thread TCGContext *tcg_ctx; |
c8bc1168 | 577 | extern const void *tcg_code_gen_epilogue; |
db0c51a3 | 578 | extern uintptr_t tcg_splitwx_diff; |
ad75a51e | 579 | extern TCGv_env tcg_env; |
c896fe29 | 580 | |
47d590df | 581 | bool in_code_gen_buffer(const void *p); |
4846cd37 | 582 | |
db0c51a3 RH |
583 | #ifdef CONFIG_DEBUG_TCG |
584 | const void *tcg_splitwx_to_rx(void *rw); | |
585 | void *tcg_splitwx_to_rw(const void *rx); | |
586 | #else | |
587 | static inline const void *tcg_splitwx_to_rx(void *rw) | |
588 | { | |
589 | return rw ? rw + tcg_splitwx_diff : NULL; | |
590 | } | |
591 | ||
592 | static inline void *tcg_splitwx_to_rw(const void *rx) | |
593 | { | |
594 | return rx ? (void *)rx - tcg_splitwx_diff : NULL; | |
595 | } | |
596 | #endif | |
597 | ||
1807f4c4 RH |
598 | static inline TCGArg temp_arg(TCGTemp *ts) |
599 | { | |
e89b28a6 | 600 | return (uintptr_t)ts; |
1807f4c4 RH |
601 | } |
602 | ||
43439139 RH |
603 | static inline TCGTemp *arg_temp(TCGArg a) |
604 | { | |
e89b28a6 | 605 | return (TCGTemp *)(uintptr_t)a; |
43439139 RH |
606 | } |
607 | ||
177f648f RH |
608 | #ifdef CONFIG_DEBUG_TCG |
609 | size_t temp_idx(TCGTemp *ts); | |
610 | TCGTemp *tcgv_i32_temp(TCGv_i32 v); | |
611 | #else | |
612 | static inline size_t temp_idx(TCGTemp *ts) | |
613 | { | |
614 | return ts - tcg_ctx->temps; | |
615 | } | |
616 | ||
617 | /* | |
618 | * Using the offset of a temporary, relative to TCGContext, rather than | |
619 | * its index means that we don't use 0. That leaves offset 0 free for | |
620 | * a NULL representation without having to leave index 0 unused. | |
621 | */ | |
e89b28a6 | 622 | static inline TCGTemp *tcgv_i32_temp(TCGv_i32 v) |
6349039d | 623 | { |
177f648f | 624 | return (void *)tcg_ctx + (uintptr_t)v; |
ae8b75dc | 625 | } |
177f648f | 626 | #endif |
ae8b75dc | 627 | |
e89b28a6 | 628 | static inline TCGTemp *tcgv_i64_temp(TCGv_i64 v) |
ae8b75dc | 629 | { |
e89b28a6 | 630 | return tcgv_i32_temp((TCGv_i32)v); |
ae8b75dc RH |
631 | } |
632 | ||
43eef72f RH |
633 | static inline TCGTemp *tcgv_i128_temp(TCGv_i128 v) |
634 | { | |
635 | return tcgv_i32_temp((TCGv_i32)v); | |
636 | } | |
637 | ||
e89b28a6 | 638 | static inline TCGTemp *tcgv_ptr_temp(TCGv_ptr v) |
ae8b75dc | 639 | { |
e89b28a6 | 640 | return tcgv_i32_temp((TCGv_i32)v); |
ae8b75dc RH |
641 | } |
642 | ||
d2fd745f RH |
643 | static inline TCGTemp *tcgv_vec_temp(TCGv_vec v) |
644 | { | |
645 | return tcgv_i32_temp((TCGv_i32)v); | |
646 | } | |
647 | ||
e89b28a6 | 648 | static inline TCGArg tcgv_i32_arg(TCGv_i32 v) |
ae8b75dc | 649 | { |
e89b28a6 | 650 | return temp_arg(tcgv_i32_temp(v)); |
ae8b75dc RH |
651 | } |
652 | ||
e89b28a6 | 653 | static inline TCGArg tcgv_i64_arg(TCGv_i64 v) |
ae8b75dc | 654 | { |
e89b28a6 | 655 | return temp_arg(tcgv_i64_temp(v)); |
ae8b75dc RH |
656 | } |
657 | ||
43eef72f RH |
658 | static inline TCGArg tcgv_i128_arg(TCGv_i128 v) |
659 | { | |
660 | return temp_arg(tcgv_i128_temp(v)); | |
661 | } | |
662 | ||
e89b28a6 | 663 | static inline TCGArg tcgv_ptr_arg(TCGv_ptr v) |
ae8b75dc | 664 | { |
e89b28a6 | 665 | return temp_arg(tcgv_ptr_temp(v)); |
ae8b75dc RH |
666 | } |
667 | ||
d2fd745f RH |
668 | static inline TCGArg tcgv_vec_arg(TCGv_vec v) |
669 | { | |
670 | return temp_arg(tcgv_vec_temp(v)); | |
671 | } | |
672 | ||
085272b3 RH |
673 | static inline TCGv_i32 temp_tcgv_i32(TCGTemp *t) |
674 | { | |
e89b28a6 | 675 | (void)temp_idx(t); /* trigger embedded assert */ |
b1311c4a | 676 | return (TCGv_i32)((void *)t - (void *)tcg_ctx); |
085272b3 RH |
677 | } |
678 | ||
679 | static inline TCGv_i64 temp_tcgv_i64(TCGTemp *t) | |
680 | { | |
e89b28a6 | 681 | return (TCGv_i64)temp_tcgv_i32(t); |
085272b3 RH |
682 | } |
683 | ||
43eef72f RH |
684 | static inline TCGv_i128 temp_tcgv_i128(TCGTemp *t) |
685 | { | |
686 | return (TCGv_i128)temp_tcgv_i32(t); | |
687 | } | |
688 | ||
085272b3 RH |
689 | static inline TCGv_ptr temp_tcgv_ptr(TCGTemp *t) |
690 | { | |
e89b28a6 | 691 | return (TCGv_ptr)temp_tcgv_i32(t); |
085272b3 RH |
692 | } |
693 | ||
d2fd745f RH |
694 | static inline TCGv_vec temp_tcgv_vec(TCGTemp *t) |
695 | { | |
696 | return (TCGv_vec)temp_tcgv_i32(t); | |
697 | } | |
698 | ||
2271a6ac RH |
699 | static inline TCGArg tcg_get_insn_param(TCGOp *op, int arg) |
700 | { | |
701 | return op->args[arg]; | |
702 | } | |
703 | ||
15fa08f8 | 704 | static inline void tcg_set_insn_param(TCGOp *op, int arg, TCGArg v) |
1d41478f | 705 | { |
15fa08f8 | 706 | op->args[arg] = v; |
1d41478f EI |
707 | } |
708 | ||
c9ad8d27 | 709 | static inline uint64_t tcg_get_insn_start_param(TCGOp *op, int arg) |
2271a6ac | 710 | { |
c9ad8d27 RH |
711 | if (TCG_TARGET_REG_BITS == 64) { |
712 | return tcg_get_insn_param(op, arg); | |
713 | } else { | |
714 | return deposit64(tcg_get_insn_param(op, arg * 2), 32, 32, | |
715 | tcg_get_insn_param(op, arg * 2 + 1)); | |
716 | } | |
2271a6ac RH |
717 | } |
718 | ||
c9ad8d27 | 719 | static inline void tcg_set_insn_start_param(TCGOp *op, int arg, uint64_t v) |
9743cd57 | 720 | { |
c9ad8d27 RH |
721 | if (TCG_TARGET_REG_BITS == 64) { |
722 | tcg_set_insn_param(op, arg, v); | |
723 | } else { | |
724 | tcg_set_insn_param(op, arg * 2, v); | |
725 | tcg_set_insn_param(op, arg * 2 + 1, v >> 32); | |
726 | } | |
9743cd57 RH |
727 | } |
728 | ||
15fa08f8 RH |
729 | /* The last op that was emitted. */ |
730 | static inline TCGOp *tcg_last_op(void) | |
fe700adb | 731 | { |
eae3eb3e | 732 | return QTAILQ_LAST(&tcg_ctx->ops); |
fe700adb RH |
733 | } |
734 | ||
735 | /* Test for whether to terminate the TB for using too many opcodes. */ | |
736 | static inline bool tcg_op_buf_full(void) | |
737 | { | |
abebf925 RH |
738 | /* This is not a hard limit, it merely stops translation when |
739 | * we have produced "enough" opcodes. We want to limit TB size | |
740 | * such that a RISC host can reasonably use a 16-bit signed | |
9f754620 RH |
741 | * branch within the TB. We also need to be mindful of the |
742 | * 16-bit unsigned offsets, TranslationBlock.jmp_reset_offset[] | |
743 | * and TCGContext.gen_insn_end_off[]. | |
abebf925 | 744 | */ |
9f754620 | 745 | return tcg_ctx->nb_ops >= 4000; |
fe700adb RH |
746 | } |
747 | ||
c896fe29 FB |
748 | /* pool based memory allocation */ |
749 | ||
0ac20318 | 750 | /* user-mode: mmap_lock must be held for tcg_malloc_internal. */ |
c896fe29 FB |
751 | void *tcg_malloc_internal(TCGContext *s, int size); |
752 | void tcg_pool_reset(TCGContext *s); | |
6e3b2bfd | 753 | TranslationBlock *tcg_tb_alloc(TCGContext *s); |
c896fe29 | 754 | |
e8feb96f EC |
755 | void tcg_region_reset_all(void); |
756 | ||
757 | size_t tcg_code_size(void); | |
758 | size_t tcg_code_capacity(void); | |
759 | ||
be2cdc5e EC |
760 | void tcg_tb_insert(TranslationBlock *tb); |
761 | void tcg_tb_remove(TranslationBlock *tb); | |
762 | TranslationBlock *tcg_tb_lookup(uintptr_t tc_ptr); | |
763 | void tcg_tb_foreach(GTraverseFunc func, gpointer user_data); | |
764 | size_t tcg_nb_tbs(void); | |
765 | ||
0ac20318 | 766 | /* user-mode: Called with mmap_lock held. */ |
c896fe29 FB |
767 | static inline void *tcg_malloc(int size) |
768 | { | |
b1311c4a | 769 | TCGContext *s = tcg_ctx; |
c896fe29 | 770 | uint8_t *ptr, *ptr_end; |
13aaef67 RH |
771 | |
772 | /* ??? This is a weak placeholder for minimum malloc alignment. */ | |
773 | size = QEMU_ALIGN_UP(size, 8); | |
774 | ||
c896fe29 FB |
775 | ptr = s->pool_cur; |
776 | ptr_end = ptr + size; | |
777 | if (unlikely(ptr_end > s->pool_end)) { | |
b1311c4a | 778 | return tcg_malloc_internal(tcg_ctx, size); |
c896fe29 FB |
779 | } else { |
780 | s->pool_cur = ptr_end; | |
781 | return ptr; | |
782 | } | |
783 | } | |
784 | ||
43b972b7 | 785 | void tcg_init(size_t tb_size, int splitwx, unsigned max_cpus); |
3468b59e | 786 | void tcg_register_thread(void); |
935f75ae | 787 | void tcg_prologue_init(void); |
c896fe29 FB |
788 | void tcg_func_start(TCGContext *s); |
789 | ||
76cef4b2 | 790 | int tcg_gen_code(TCGContext *s, TranslationBlock *tb, uint64_t pc_start); |
c896fe29 | 791 | |
0012e351 RH |
792 | void tb_target_set_jmp_target(const TranslationBlock *, int, |
793 | uintptr_t, uintptr_t); | |
794 | ||
b6638662 | 795 | void tcg_set_frame(TCGContext *s, TCGReg reg, intptr_t start, intptr_t size); |
a7812ae4 | 796 | |
085272b3 RH |
797 | TCGTemp *tcg_global_mem_new_internal(TCGType, TCGv_ptr, |
798 | intptr_t, const char *); | |
bbf989bf | 799 | TCGTemp *tcg_temp_new_internal(TCGType, TCGTempKind); |
d2fd745f RH |
800 | TCGv_vec tcg_temp_new_vec(TCGType type); |
801 | TCGv_vec tcg_temp_new_vec_matching(TCGv_vec match); | |
e1ccc054 | 802 | |
e1ccc054 RH |
803 | static inline TCGv_i32 tcg_global_mem_new_i32(TCGv_ptr reg, intptr_t offset, |
804 | const char *name) | |
805 | { | |
085272b3 RH |
806 | TCGTemp *t = tcg_global_mem_new_internal(TCG_TYPE_I32, reg, offset, name); |
807 | return temp_tcgv_i32(t); | |
e1ccc054 RH |
808 | } |
809 | ||
a7812ae4 PB |
810 | static inline TCGv_i32 tcg_temp_new_i32(void) |
811 | { | |
e2e641fa | 812 | TCGTemp *t = tcg_temp_new_internal(TCG_TYPE_I32, TEMP_TB); |
5bfa8034 | 813 | return temp_tcgv_i32(t); |
a7812ae4 | 814 | } |
e1ccc054 | 815 | |
e1ccc054 RH |
816 | static inline TCGv_i64 tcg_global_mem_new_i64(TCGv_ptr reg, intptr_t offset, |
817 | const char *name) | |
818 | { | |
085272b3 RH |
819 | TCGTemp *t = tcg_global_mem_new_internal(TCG_TYPE_I64, reg, offset, name); |
820 | return temp_tcgv_i64(t); | |
e1ccc054 RH |
821 | } |
822 | ||
a7812ae4 | 823 | static inline TCGv_i64 tcg_temp_new_i64(void) |
641d5fbe | 824 | { |
e2e641fa | 825 | TCGTemp *t = tcg_temp_new_internal(TCG_TYPE_I64, TEMP_TB); |
5bfa8034 | 826 | return temp_tcgv_i64(t); |
641d5fbe | 827 | } |
e1ccc054 | 828 | |
43eef72f RH |
829 | static inline TCGv_i128 tcg_temp_new_i128(void) |
830 | { | |
e2e641fa | 831 | TCGTemp *t = tcg_temp_new_internal(TCG_TYPE_I128, TEMP_TB); |
43eef72f RH |
832 | return temp_tcgv_i128(t); |
833 | } | |
834 | ||
5bfa8034 RH |
835 | static inline TCGv_ptr tcg_global_mem_new_ptr(TCGv_ptr reg, intptr_t offset, |
836 | const char *name) | |
837 | { | |
838 | TCGTemp *t = tcg_global_mem_new_internal(TCG_TYPE_PTR, reg, offset, name); | |
839 | return temp_tcgv_ptr(t); | |
840 | } | |
841 | ||
842 | static inline TCGv_ptr tcg_temp_new_ptr(void) | |
843 | { | |
e2e641fa | 844 | TCGTemp *t = tcg_temp_new_internal(TCG_TYPE_PTR, TEMP_TB); |
5bfa8034 RH |
845 | return temp_tcgv_ptr(t); |
846 | } | |
847 | ||
3a841ab5 | 848 | void tcg_dump_info(GString *buf); |
b6a7f3e0 | 849 | void tcg_dump_op_count(GString *buf); |
c896fe29 | 850 | |
bc2b17e6 | 851 | #define TCG_CT_CONST 1 /* any constant of register size */ |
c896fe29 FB |
852 | |
853 | typedef struct TCGArgConstraint { | |
bc2b17e6 RH |
854 | unsigned ct : 16; |
855 | unsigned alias_index : 4; | |
856 | unsigned sort_index : 4; | |
29f5e925 RH |
857 | unsigned pair_index : 4; |
858 | unsigned pair : 2; /* 0: none, 1: first, 2: second, 3: second alias */ | |
bc2b17e6 RH |
859 | bool oalias : 1; |
860 | bool ialias : 1; | |
861 | bool newreg : 1; | |
9be0d080 | 862 | TCGRegSet regs; |
c896fe29 FB |
863 | } TCGArgConstraint; |
864 | ||
865 | #define TCG_MAX_OP_ARGS 16 | |
866 | ||
b4cb76e6 | 867 | /* Bits for TCGOpDef->flags, 8 bits available, all used. */ |
8399ad59 | 868 | enum { |
ae36a246 RH |
869 | /* Instruction exits the translation block. */ |
870 | TCG_OPF_BB_EXIT = 0x01, | |
8399ad59 | 871 | /* Instruction defines the end of a basic block. */ |
ae36a246 | 872 | TCG_OPF_BB_END = 0x02, |
8399ad59 | 873 | /* Instruction clobbers call registers and potentially update globals. */ |
ae36a246 | 874 | TCG_OPF_CALL_CLOBBER = 0x04, |
3d5c5f87 AJ |
875 | /* Instruction has side effects: it cannot be removed if its outputs |
876 | are not used, and might trigger exceptions. */ | |
ae36a246 | 877 | TCG_OPF_SIDE_EFFECTS = 0x08, |
8399ad59 | 878 | /* Instruction operands are 64-bits (otherwise 32-bits). */ |
ae36a246 | 879 | TCG_OPF_64BIT = 0x10, |
c1a61f6c | 880 | /* Instruction is optional and not implemented by the host, or insn |
669dcb60 | 881 | is generic and should not be implemented by the host. */ |
ae36a246 | 882 | TCG_OPF_NOT_PRESENT = 0x20, |
d2fd745f | 883 | /* Instruction operands are vectors. */ |
ae36a246 | 884 | TCG_OPF_VECTOR = 0x40, |
b4cb76e6 RH |
885 | /* Instruction is a conditional branch. */ |
886 | TCG_OPF_COND_BRANCH = 0x80 | |
8399ad59 | 887 | }; |
c896fe29 FB |
888 | |
889 | typedef struct TCGOpDef { | |
890 | const char *name; | |
891 | uint8_t nb_oargs, nb_iargs, nb_cargs, nb_args; | |
892 | uint8_t flags; | |
c896fe29 | 893 | TCGArgConstraint *args_ct; |
c896fe29 | 894 | } TCGOpDef; |
8399ad59 RH |
895 | |
896 | extern TCGOpDef tcg_op_defs[]; | |
2a24374a SW |
897 | extern const size_t tcg_op_defs_max; |
898 | ||
c896fe29 | 899 | typedef struct TCGTargetOpDef { |
a9751609 | 900 | TCGOpcode op; |
c896fe29 FB |
901 | const char *args_ct_str[TCG_MAX_OP_ARGS]; |
902 | } TCGTargetOpDef; | |
903 | ||
be0f34b5 RH |
904 | bool tcg_op_supported(TCGOpcode op); |
905 | ||
a3a692b8 RH |
906 | void tcg_gen_call0(TCGHelperInfo *, TCGTemp *ret); |
907 | void tcg_gen_call1(TCGHelperInfo *, TCGTemp *ret, TCGTemp *); | |
908 | void tcg_gen_call2(TCGHelperInfo *, TCGTemp *ret, TCGTemp *, TCGTemp *); | |
909 | void tcg_gen_call3(TCGHelperInfo *, TCGTemp *ret, TCGTemp *, | |
910 | TCGTemp *, TCGTemp *); | |
911 | void tcg_gen_call4(TCGHelperInfo *, TCGTemp *ret, TCGTemp *, TCGTemp *, | |
912 | TCGTemp *, TCGTemp *); | |
913 | void tcg_gen_call5(TCGHelperInfo *, TCGTemp *ret, TCGTemp *, TCGTemp *, | |
914 | TCGTemp *, TCGTemp *, TCGTemp *); | |
915 | void tcg_gen_call6(TCGHelperInfo *, TCGTemp *ret, TCGTemp *, TCGTemp *, | |
916 | TCGTemp *, TCGTemp *, TCGTemp *, TCGTemp *); | |
917 | void tcg_gen_call7(TCGHelperInfo *, TCGTemp *ret, TCGTemp *, TCGTemp *, | |
918 | TCGTemp *, TCGTemp *, TCGTemp *, TCGTemp *, TCGTemp *); | |
a7812ae4 | 919 | |
d4478943 | 920 | TCGOp *tcg_emit_op(TCGOpcode opc, unsigned nargs); |
0c627cdc | 921 | void tcg_op_remove(TCGContext *s, TCGOp *op); |
d4478943 PMD |
922 | TCGOp *tcg_op_insert_before(TCGContext *s, TCGOp *op, |
923 | TCGOpcode opc, unsigned nargs); | |
924 | TCGOp *tcg_op_insert_after(TCGContext *s, TCGOp *op, | |
925 | TCGOpcode opc, unsigned nargs); | |
5a18407f | 926 | |
a80cdd31 RH |
927 | /** |
928 | * tcg_remove_ops_after: | |
929 | * @op: target operation | |
930 | * | |
931 | * Discard any opcodes emitted since @op. Expected usage is to save | |
932 | * a starting point with tcg_last_op(), speculatively emit opcodes, | |
933 | * then decide whether or not to keep those opcodes after the fact. | |
934 | */ | |
935 | void tcg_remove_ops_after(TCGOp *op); | |
936 | ||
c45cb8bb | 937 | void tcg_optimize(TCGContext *s); |
a7812ae4 | 938 | |
c0522136 RH |
939 | /* |
940 | * Locate or create a read-only temporary that is a constant. | |
a14b3ad1 RH |
941 | * This kind of temporary need not be freed, but for convenience |
942 | * will be silently ignored by tcg_temp_free_*. | |
c0522136 RH |
943 | */ |
944 | TCGTemp *tcg_constant_internal(TCGType type, int64_t val); | |
945 | ||
946 | static inline TCGv_i32 tcg_constant_i32(int32_t val) | |
947 | { | |
948 | return temp_tcgv_i32(tcg_constant_internal(TCG_TYPE_I32, val)); | |
949 | } | |
950 | ||
951 | static inline TCGv_i64 tcg_constant_i64(int64_t val) | |
952 | { | |
953 | return temp_tcgv_i64(tcg_constant_internal(TCG_TYPE_I64, val)); | |
954 | } | |
955 | ||
956 | TCGv_vec tcg_constant_vec(TCGType type, unsigned vece, int64_t val); | |
88d4005b | 957 | TCGv_vec tcg_constant_vec_matching(TCGv_vec match, unsigned vece, int64_t val); |
c0522136 | 958 | |
5bfa8034 | 959 | #if UINTPTR_MAX == UINT32_MAX |
a61532fa | 960 | # define tcg_constant_ptr(x) ((TCGv_ptr)tcg_constant_i32((intptr_t)(x))) |
5bfa8034 | 961 | #else |
a61532fa | 962 | # define tcg_constant_ptr(x) ((TCGv_ptr)tcg_constant_i64((intptr_t)(x))) |
5bfa8034 RH |
963 | #endif |
964 | ||
42a268c2 RH |
965 | TCGLabel *gen_new_label(void); |
966 | ||
967 | /** | |
968 | * label_arg | |
969 | * @l: label | |
970 | * | |
971 | * Encode a label for storage in the TCG opcode stream. | |
972 | */ | |
973 | ||
974 | static inline TCGArg label_arg(TCGLabel *l) | |
975 | { | |
51e3972c | 976 | return (uintptr_t)l; |
42a268c2 RH |
977 | } |
978 | ||
979 | /** | |
980 | * arg_label | |
981 | * @i: value | |
982 | * | |
983 | * The opposite of label_arg. Retrieve a label from the | |
984 | * encoding of the TCG opcode stream. | |
985 | */ | |
986 | ||
51e3972c | 987 | static inline TCGLabel *arg_label(TCGArg i) |
42a268c2 | 988 | { |
51e3972c | 989 | return (TCGLabel *)(uintptr_t)i; |
42a268c2 RH |
990 | } |
991 | ||
52a1f64e RH |
992 | /** |
993 | * tcg_ptr_byte_diff | |
994 | * @a, @b: addresses to be differenced | |
995 | * | |
996 | * There are many places within the TCG backends where we need a byte | |
997 | * difference between two pointers. While this can be accomplished | |
998 | * with local casting, it's easy to get wrong -- especially if one is | |
999 | * concerned with the signedness of the result. | |
1000 | * | |
1001 | * This version relies on GCC's void pointer arithmetic to get the | |
1002 | * correct result. | |
1003 | */ | |
1004 | ||
db0c51a3 | 1005 | static inline ptrdiff_t tcg_ptr_byte_diff(const void *a, const void *b) |
52a1f64e RH |
1006 | { |
1007 | return a - b; | |
1008 | } | |
1009 | ||
1010 | /** | |
1011 | * tcg_pcrel_diff | |
1012 | * @s: the tcg context | |
1013 | * @target: address of the target | |
1014 | * | |
1015 | * Produce a pc-relative difference, from the current code_ptr | |
1016 | * to the destination address. | |
1017 | */ | |
1018 | ||
db0c51a3 | 1019 | static inline ptrdiff_t tcg_pcrel_diff(TCGContext *s, const void *target) |
52a1f64e | 1020 | { |
db0c51a3 | 1021 | return tcg_ptr_byte_diff(target, tcg_splitwx_to_rx(s->code_ptr)); |
52a1f64e RH |
1022 | } |
1023 | ||
44c7197f RH |
1024 | /** |
1025 | * tcg_tbrel_diff | |
1026 | * @s: the tcg context | |
1027 | * @target: address of the target | |
1028 | * | |
1029 | * Produce a difference, from the beginning of the current TB code | |
1030 | * to the destination address. | |
1031 | */ | |
1032 | static inline ptrdiff_t tcg_tbrel_diff(TCGContext *s, const void *target) | |
1033 | { | |
1034 | return tcg_ptr_byte_diff(target, tcg_splitwx_to_rx(s->code_buf)); | |
1035 | } | |
1036 | ||
52a1f64e RH |
1037 | /** |
1038 | * tcg_current_code_size | |
1039 | * @s: the tcg context | |
1040 | * | |
1041 | * Compute the current code size within the translation block. | |
1042 | * This is used to fill in qemu's data structures for goto_tb. | |
1043 | */ | |
1044 | ||
1045 | static inline size_t tcg_current_code_size(TCGContext *s) | |
1046 | { | |
1047 | return tcg_ptr_byte_diff(s->code_ptr, s->code_buf); | |
1048 | } | |
1049 | ||
0980011b PM |
1050 | /** |
1051 | * tcg_qemu_tb_exec: | |
819af24b | 1052 | * @env: pointer to CPUArchState for the CPU |
0980011b PM |
1053 | * @tb_ptr: address of generated code for the TB to execute |
1054 | * | |
1055 | * Start executing code from a given translation block. | |
1056 | * Where translation blocks have been linked, execution | |
1057 | * may proceed from the given TB into successive ones. | |
1058 | * Control eventually returns only when some action is needed | |
1059 | * from the top-level loop: either control must pass to a TB | |
1060 | * which has not yet been directly linked, or an asynchronous | |
1061 | * event such as an interrupt needs handling. | |
1062 | * | |
819af24b SF |
1063 | * Return: The return value is the value passed to the corresponding |
1064 | * tcg_gen_exit_tb() at translation time of the last TB attempted to execute. | |
1065 | * The value is either zero or a 4-byte aligned pointer to that TB combined | |
1066 | * with additional information in its two least significant bits. The | |
1067 | * additional information is encoded as follows: | |
0980011b PM |
1068 | * 0, 1: the link between this TB and the next is via the specified |
1069 | * TB index (0 or 1). That is, we left the TB via (the equivalent | |
1070 | * of) "goto_tb <index>". The main loop uses this to determine | |
1071 | * how to link the TB just executed to the next. | |
1072 | * 2: we are using instruction counting code generation, and we | |
1073 | * did not start executing this TB because the instruction counter | |
819af24b | 1074 | * would hit zero midway through it. In this case the pointer |
0980011b PM |
1075 | * returned is the TB we were about to execute, and the caller must |
1076 | * arrange to execute the remaining count of instructions. | |
378df4b2 PM |
1077 | * 3: we stopped because the CPU's exit_request flag was set |
1078 | * (usually meaning that there is an interrupt that needs to be | |
819af24b SF |
1079 | * handled). The pointer returned is the TB we were about to execute |
1080 | * when we noticed the pending exit request. | |
0980011b PM |
1081 | * |
1082 | * If the bottom two bits indicate an exit-via-index then the CPU | |
1083 | * state is correctly synchronised and ready for execution of the next | |
1084 | * TB (and in particular the guest PC is the address to execute next). | |
1085 | * Otherwise, we gave up on execution of this TB before it started, and | |
fee068e4 | 1086 | * the caller must fix up the CPU state by calling the CPU's |
819af24b | 1087 | * synchronize_from_tb() method with the TB pointer we return (falling |
fee068e4 PC |
1088 | * back to calling the CPU's set_pc method with tb->pb if no |
1089 | * synchronize_from_tb() method exists). | |
0980011b PM |
1090 | * |
1091 | * Note that TCG targets may use a different definition of tcg_qemu_tb_exec | |
1092 | * to this default (which just calls the prologue.code emitted by | |
1093 | * tcg_target_qemu_prologue()). | |
1094 | */ | |
07ea28b4 RH |
1095 | #define TB_EXIT_MASK 3 |
1096 | #define TB_EXIT_IDX0 0 | |
1097 | #define TB_EXIT_IDX1 1 | |
1098 | #define TB_EXIT_IDXMAX 1 | |
378df4b2 | 1099 | #define TB_EXIT_REQUESTED 3 |
0980011b | 1100 | |
b91ccb31 | 1101 | #ifdef CONFIG_TCG_INTERPRETER |
db0c51a3 | 1102 | uintptr_t tcg_qemu_tb_exec(CPUArchState *env, const void *tb_ptr); |
5a58e884 | 1103 | #else |
db0c51a3 | 1104 | typedef uintptr_t tcg_prologue_fn(CPUArchState *env, const void *tb_ptr); |
b91ccb31 | 1105 | extern tcg_prologue_fn *tcg_qemu_tb_exec; |
932a6909 | 1106 | #endif |
813da627 | 1107 | |
755bf9e5 | 1108 | void tcg_register_jit(const void *buf, size_t buf_size); |
b76f0d8c | 1109 | |
db432672 RH |
1110 | #if TCG_TARGET_MAYBE_vec |
1111 | /* Return zero if the tuple (opc, type, vece) is unsupportable; | |
1112 | return > 0 if it is directly supportable; | |
1113 | return < 0 if we must call tcg_expand_vec_op. */ | |
1114 | int tcg_can_emit_vec_op(TCGOpcode, TCGType, unsigned); | |
1115 | #else | |
1116 | static inline int tcg_can_emit_vec_op(TCGOpcode o, TCGType t, unsigned ve) | |
1117 | { | |
1118 | return 0; | |
1119 | } | |
1120 | #endif | |
1121 | ||
1122 | /* Expand the tuple (opc, type, vece) on the given arguments. */ | |
1123 | void tcg_expand_vec_op(TCGOpcode, TCGType, unsigned, TCGArg, ...); | |
1124 | ||
669dcb60 | 1125 | /* Replicate a constant C according to the log2 of the element size. */ |
db432672 RH |
1126 | uint64_t dup_const(unsigned vece, uint64_t c); |
1127 | ||
1128 | #define dup_const(VECE, C) \ | |
1129 | (__builtin_constant_p(VECE) \ | |
1130 | ? ( (VECE) == MO_8 ? 0x0101010101010101ull * (uint8_t)(C) \ | |
1131 | : (VECE) == MO_16 ? 0x0001000100010001ull * (uint16_t)(C) \ | |
1132 | : (VECE) == MO_32 ? 0x0000000100000001ull * (uint32_t)(C) \ | |
666cc794 RH |
1133 | : (VECE) == MO_64 ? (uint64_t)(C) \ |
1134 | : (qemu_build_not_reached_always(), 0)) \ | |
db432672 RH |
1135 | : dup_const(VECE, C)) |
1136 | ||
53229a77 RH |
1137 | static inline const TCGOpcode *tcg_swap_vecop_list(const TCGOpcode *n) |
1138 | { | |
1139 | #ifdef CONFIG_DEBUG_TCG | |
1140 | const TCGOpcode *o = tcg_ctx->vecop_list; | |
1141 | tcg_ctx->vecop_list = n; | |
1142 | return o; | |
1143 | #else | |
1144 | return NULL; | |
1145 | #endif | |
1146 | } | |
1147 | ||
1148 | bool tcg_can_emit_vecop_list(const TCGOpcode *, TCGType, unsigned); | |
1149 | ||
e58eb534 | 1150 | #endif /* TCG_H */ |