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c896fe29 FB |
1 | /* |
2 | * Tiny Code Generator for QEMU | |
3 | * | |
4 | * Copyright (c) 2008 Fabrice Bellard | |
5 | * | |
6 | * Permission is hereby granted, free of charge, to any person obtaining a copy | |
7 | * of this software and associated documentation files (the "Software"), to deal | |
8 | * in the Software without restriction, including without limitation the rights | |
9 | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell | |
10 | * copies of the Software, and to permit persons to whom the Software is | |
11 | * furnished to do so, subject to the following conditions: | |
12 | * | |
13 | * The above copyright notice and this permission notice shall be included in | |
14 | * all copies or substantial portions of the Software. | |
15 | * | |
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
19 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
20 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, | |
21 | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN | |
22 | * THE SOFTWARE. | |
23 | */ | |
e58eb534 RH |
24 | |
25 | #ifndef TCG_H | |
26 | #define TCG_H | |
27 | ||
33c11879 | 28 | #include "cpu.h" |
14776ab5 | 29 | #include "exec/memop.h" |
00f6da6a | 30 | #include "exec/tb-context.h" |
0ec9eabc | 31 | #include "qemu/bitops.h" |
e6d86bed | 32 | #include "qemu/plugin.h" |
15fa08f8 | 33 | #include "qemu/queue.h" |
dcb32f1d | 34 | #include "tcg/tcg-mo.h" |
78cd7b83 | 35 | #include "tcg-target.h" |
e6cd4bb5 | 36 | #include "qemu/int128.h" |
78cd7b83 | 37 | |
00f6da6a PB |
38 | /* XXX: make safe guess about sizes */ |
39 | #define MAX_OP_PER_INSTR 266 | |
40 | ||
41 | #if HOST_LONG_BITS == 32 | |
42 | #define MAX_OPC_PARAM_PER_ARG 2 | |
43 | #else | |
44 | #define MAX_OPC_PARAM_PER_ARG 1 | |
45 | #endif | |
1df3caa9 | 46 | #define MAX_OPC_PARAM_IARGS 6 |
00f6da6a PB |
47 | #define MAX_OPC_PARAM_OARGS 1 |
48 | #define MAX_OPC_PARAM_ARGS (MAX_OPC_PARAM_IARGS + MAX_OPC_PARAM_OARGS) | |
49 | ||
50 | /* A Call op needs up to 4 + 2N parameters on 32-bit archs, | |
51 | * and up to 4 + N parameters on 64-bit archs | |
52 | * (N = number of input arguments + output arguments). */ | |
53 | #define MAX_OPC_PARAM (4 + (MAX_OPC_PARAM_PER_ARG * MAX_OPC_PARAM_ARGS)) | |
00f6da6a | 54 | |
6e0b0730 PC |
55 | #define CPU_TEMP_BUF_NLONGS 128 |
56 | ||
78cd7b83 RH |
57 | /* Default target word size to pointer size. */ |
58 | #ifndef TCG_TARGET_REG_BITS | |
59 | # if UINTPTR_MAX == UINT32_MAX | |
60 | # define TCG_TARGET_REG_BITS 32 | |
61 | # elif UINTPTR_MAX == UINT64_MAX | |
62 | # define TCG_TARGET_REG_BITS 64 | |
63 | # else | |
64 | # error Unknown pointer size for tcg target | |
65 | # endif | |
817b838e SW |
66 | #endif |
67 | ||
c896fe29 FB |
68 | #if TCG_TARGET_REG_BITS == 32 |
69 | typedef int32_t tcg_target_long; | |
70 | typedef uint32_t tcg_target_ulong; | |
71 | #define TCG_PRIlx PRIx32 | |
72 | #define TCG_PRIld PRId32 | |
73 | #elif TCG_TARGET_REG_BITS == 64 | |
74 | typedef int64_t tcg_target_long; | |
75 | typedef uint64_t tcg_target_ulong; | |
76 | #define TCG_PRIlx PRIx64 | |
77 | #define TCG_PRIld PRId64 | |
78 | #else | |
79 | #error unsupported | |
80 | #endif | |
81 | ||
8d4e9146 FK |
82 | /* Oversized TCG guests make things like MTTCG hard |
83 | * as we can't use atomics for cputlb updates. | |
84 | */ | |
85 | #if TARGET_LONG_BITS > TCG_TARGET_REG_BITS | |
86 | #define TCG_OVERSIZED_GUEST 1 | |
87 | #else | |
88 | #define TCG_OVERSIZED_GUEST 0 | |
89 | #endif | |
90 | ||
c896fe29 FB |
91 | #if TCG_TARGET_NB_REGS <= 32 |
92 | typedef uint32_t TCGRegSet; | |
93 | #elif TCG_TARGET_NB_REGS <= 64 | |
94 | typedef uint64_t TCGRegSet; | |
95 | #else | |
96 | #error unsupported | |
97 | #endif | |
98 | ||
25c4d9cc | 99 | #if TCG_TARGET_REG_BITS == 32 |
e6a72734 | 100 | /* Turn some undef macros into false macros. */ |
609ad705 RH |
101 | #define TCG_TARGET_HAS_extrl_i64_i32 0 |
102 | #define TCG_TARGET_HAS_extrh_i64_i32 0 | |
25c4d9cc | 103 | #define TCG_TARGET_HAS_div_i64 0 |
ca675f46 | 104 | #define TCG_TARGET_HAS_rem_i64 0 |
25c4d9cc RH |
105 | #define TCG_TARGET_HAS_div2_i64 0 |
106 | #define TCG_TARGET_HAS_rot_i64 0 | |
107 | #define TCG_TARGET_HAS_ext8s_i64 0 | |
108 | #define TCG_TARGET_HAS_ext16s_i64 0 | |
109 | #define TCG_TARGET_HAS_ext32s_i64 0 | |
110 | #define TCG_TARGET_HAS_ext8u_i64 0 | |
111 | #define TCG_TARGET_HAS_ext16u_i64 0 | |
112 | #define TCG_TARGET_HAS_ext32u_i64 0 | |
113 | #define TCG_TARGET_HAS_bswap16_i64 0 | |
114 | #define TCG_TARGET_HAS_bswap32_i64 0 | |
115 | #define TCG_TARGET_HAS_bswap64_i64 0 | |
116 | #define TCG_TARGET_HAS_neg_i64 0 | |
117 | #define TCG_TARGET_HAS_not_i64 0 | |
118 | #define TCG_TARGET_HAS_andc_i64 0 | |
119 | #define TCG_TARGET_HAS_orc_i64 0 | |
120 | #define TCG_TARGET_HAS_eqv_i64 0 | |
121 | #define TCG_TARGET_HAS_nand_i64 0 | |
122 | #define TCG_TARGET_HAS_nor_i64 0 | |
0e28d006 RH |
123 | #define TCG_TARGET_HAS_clz_i64 0 |
124 | #define TCG_TARGET_HAS_ctz_i64 0 | |
a768e4e9 | 125 | #define TCG_TARGET_HAS_ctpop_i64 0 |
25c4d9cc | 126 | #define TCG_TARGET_HAS_deposit_i64 0 |
7ec8bab3 RH |
127 | #define TCG_TARGET_HAS_extract_i64 0 |
128 | #define TCG_TARGET_HAS_sextract_i64 0 | |
fce1296f | 129 | #define TCG_TARGET_HAS_extract2_i64 0 |
ffc5ea09 | 130 | #define TCG_TARGET_HAS_movcond_i64 0 |
d7156f7c RH |
131 | #define TCG_TARGET_HAS_add2_i64 0 |
132 | #define TCG_TARGET_HAS_sub2_i64 0 | |
133 | #define TCG_TARGET_HAS_mulu2_i64 0 | |
4d3203fd | 134 | #define TCG_TARGET_HAS_muls2_i64 0 |
03271524 RH |
135 | #define TCG_TARGET_HAS_muluh_i64 0 |
136 | #define TCG_TARGET_HAS_mulsh_i64 0 | |
e6a72734 RH |
137 | /* Turn some undef macros into true macros. */ |
138 | #define TCG_TARGET_HAS_add2_i32 1 | |
139 | #define TCG_TARGET_HAS_sub2_i32 1 | |
25c4d9cc RH |
140 | #endif |
141 | ||
a4773324 JK |
142 | #ifndef TCG_TARGET_deposit_i32_valid |
143 | #define TCG_TARGET_deposit_i32_valid(ofs, len) 1 | |
144 | #endif | |
145 | #ifndef TCG_TARGET_deposit_i64_valid | |
146 | #define TCG_TARGET_deposit_i64_valid(ofs, len) 1 | |
147 | #endif | |
7ec8bab3 RH |
148 | #ifndef TCG_TARGET_extract_i32_valid |
149 | #define TCG_TARGET_extract_i32_valid(ofs, len) 1 | |
150 | #endif | |
151 | #ifndef TCG_TARGET_extract_i64_valid | |
152 | #define TCG_TARGET_extract_i64_valid(ofs, len) 1 | |
153 | #endif | |
a4773324 | 154 | |
25c4d9cc RH |
155 | /* Only one of DIV or DIV2 should be defined. */ |
156 | #if defined(TCG_TARGET_HAS_div_i32) | |
157 | #define TCG_TARGET_HAS_div2_i32 0 | |
158 | #elif defined(TCG_TARGET_HAS_div2_i32) | |
159 | #define TCG_TARGET_HAS_div_i32 0 | |
ca675f46 | 160 | #define TCG_TARGET_HAS_rem_i32 0 |
25c4d9cc RH |
161 | #endif |
162 | #if defined(TCG_TARGET_HAS_div_i64) | |
163 | #define TCG_TARGET_HAS_div2_i64 0 | |
164 | #elif defined(TCG_TARGET_HAS_div2_i64) | |
165 | #define TCG_TARGET_HAS_div_i64 0 | |
ca675f46 | 166 | #define TCG_TARGET_HAS_rem_i64 0 |
25c4d9cc RH |
167 | #endif |
168 | ||
df9ebea5 RH |
169 | /* For 32-bit targets, some sort of unsigned widening multiply is required. */ |
170 | #if TCG_TARGET_REG_BITS == 32 \ | |
171 | && !(defined(TCG_TARGET_HAS_mulu2_i32) \ | |
172 | || defined(TCG_TARGET_HAS_muluh_i32)) | |
173 | # error "Missing unsigned widening multiply" | |
174 | #endif | |
175 | ||
d2fd745f RH |
176 | #if !defined(TCG_TARGET_HAS_v64) \ |
177 | && !defined(TCG_TARGET_HAS_v128) \ | |
178 | && !defined(TCG_TARGET_HAS_v256) | |
179 | #define TCG_TARGET_MAYBE_vec 0 | |
bcefc902 | 180 | #define TCG_TARGET_HAS_abs_vec 0 |
d2fd745f RH |
181 | #define TCG_TARGET_HAS_neg_vec 0 |
182 | #define TCG_TARGET_HAS_not_vec 0 | |
183 | #define TCG_TARGET_HAS_andc_vec 0 | |
184 | #define TCG_TARGET_HAS_orc_vec 0 | |
b0f7e744 | 185 | #define TCG_TARGET_HAS_roti_vec 0 |
23850a74 | 186 | #define TCG_TARGET_HAS_rots_vec 0 |
5d0ceda9 | 187 | #define TCG_TARGET_HAS_rotv_vec 0 |
d0ec9796 RH |
188 | #define TCG_TARGET_HAS_shi_vec 0 |
189 | #define TCG_TARGET_HAS_shs_vec 0 | |
190 | #define TCG_TARGET_HAS_shv_vec 0 | |
3774030a | 191 | #define TCG_TARGET_HAS_mul_vec 0 |
8afaf050 | 192 | #define TCG_TARGET_HAS_sat_vec 0 |
dd0a0fcd | 193 | #define TCG_TARGET_HAS_minmax_vec 0 |
38dc1294 | 194 | #define TCG_TARGET_HAS_bitsel_vec 0 |
f75da298 | 195 | #define TCG_TARGET_HAS_cmpsel_vec 0 |
d2fd745f RH |
196 | #else |
197 | #define TCG_TARGET_MAYBE_vec 1 | |
198 | #endif | |
199 | #ifndef TCG_TARGET_HAS_v64 | |
200 | #define TCG_TARGET_HAS_v64 0 | |
201 | #endif | |
202 | #ifndef TCG_TARGET_HAS_v128 | |
203 | #define TCG_TARGET_HAS_v128 0 | |
204 | #endif | |
205 | #ifndef TCG_TARGET_HAS_v256 | |
206 | #define TCG_TARGET_HAS_v256 0 | |
207 | #endif | |
208 | ||
9aef40ed RH |
209 | #ifndef TARGET_INSN_START_EXTRA_WORDS |
210 | # define TARGET_INSN_START_WORDS 1 | |
211 | #else | |
212 | # define TARGET_INSN_START_WORDS (1 + TARGET_INSN_START_EXTRA_WORDS) | |
213 | #endif | |
214 | ||
a9751609 | 215 | typedef enum TCGOpcode { |
c61aaf7a | 216 | #define DEF(name, oargs, iargs, cargs, flags) INDEX_op_ ## name, |
dcb32f1d | 217 | #include "tcg/tcg-opc.h" |
c896fe29 FB |
218 | #undef DEF |
219 | NB_OPS, | |
a9751609 | 220 | } TCGOpcode; |
c896fe29 | 221 | |
80a8b9a9 RH |
222 | #define tcg_regset_set_reg(d, r) ((d) |= (TCGRegSet)1 << (r)) |
223 | #define tcg_regset_reset_reg(d, r) ((d) &= ~((TCGRegSet)1 << (r))) | |
224 | #define tcg_regset_test_reg(d, r) (((d) >> (r)) & 1) | |
c896fe29 | 225 | |
1813e175 | 226 | #ifndef TCG_TARGET_INSN_UNIT_SIZE |
5053361b RH |
227 | # error "Missing TCG_TARGET_INSN_UNIT_SIZE" |
228 | #elif TCG_TARGET_INSN_UNIT_SIZE == 1 | |
1813e175 RH |
229 | typedef uint8_t tcg_insn_unit; |
230 | #elif TCG_TARGET_INSN_UNIT_SIZE == 2 | |
231 | typedef uint16_t tcg_insn_unit; | |
232 | #elif TCG_TARGET_INSN_UNIT_SIZE == 4 | |
233 | typedef uint32_t tcg_insn_unit; | |
234 | #elif TCG_TARGET_INSN_UNIT_SIZE == 8 | |
235 | typedef uint64_t tcg_insn_unit; | |
236 | #else | |
237 | /* The port better have done this. */ | |
238 | #endif | |
239 | ||
240 | ||
8bff06a0 | 241 | #if defined CONFIG_DEBUG_TCG || defined QEMU_STATIC_ANALYSIS |
1f00b27f | 242 | # define tcg_debug_assert(X) do { assert(X); } while (0) |
6fa2cef2 | 243 | #else |
1f00b27f SS |
244 | # define tcg_debug_assert(X) \ |
245 | do { if (!(X)) { __builtin_unreachable(); } } while (0) | |
1f00b27f SS |
246 | #endif |
247 | ||
7ecd02a0 RH |
248 | typedef struct TCGRelocation TCGRelocation; |
249 | struct TCGRelocation { | |
250 | QSIMPLEQ_ENTRY(TCGRelocation) next; | |
1813e175 | 251 | tcg_insn_unit *ptr; |
2ba7fae2 | 252 | intptr_t addend; |
7ecd02a0 RH |
253 | int type; |
254 | }; | |
c896fe29 | 255 | |
bef16ab4 RH |
256 | typedef struct TCGLabel TCGLabel; |
257 | struct TCGLabel { | |
258 | unsigned present : 1; | |
51e3972c | 259 | unsigned has_value : 1; |
bef16ab4 | 260 | unsigned id : 14; |
d88a117e | 261 | unsigned refs : 16; |
c896fe29 | 262 | union { |
2ba7fae2 | 263 | uintptr_t value; |
ffd0e507 | 264 | const tcg_insn_unit *value_ptr; |
c896fe29 | 265 | } u; |
7ecd02a0 | 266 | QSIMPLEQ_HEAD(, TCGRelocation) relocs; |
bef16ab4 | 267 | QSIMPLEQ_ENTRY(TCGLabel) next; |
bef16ab4 | 268 | }; |
c896fe29 FB |
269 | |
270 | typedef struct TCGPool { | |
271 | struct TCGPool *next; | |
c44f945a | 272 | int size; |
f7795e40 | 273 | uint8_t data[] __attribute__ ((aligned)); |
c896fe29 FB |
274 | } TCGPool; |
275 | ||
276 | #define TCG_POOL_CHUNK_SIZE 32768 | |
277 | ||
c4071c90 | 278 | #define TCG_MAX_TEMPS 512 |
190ce7fb | 279 | #define TCG_MAX_INSNS 512 |
c896fe29 | 280 | |
b03cce8e FB |
281 | /* when the size of the arguments of a called function is smaller than |
282 | this value, they are statically allocated in the TB stack frame */ | |
283 | #define TCG_STATIC_CALL_ARGS_SIZE 128 | |
284 | ||
c02244a5 RH |
285 | typedef enum TCGType { |
286 | TCG_TYPE_I32, | |
287 | TCG_TYPE_I64, | |
d2fd745f RH |
288 | |
289 | TCG_TYPE_V64, | |
290 | TCG_TYPE_V128, | |
291 | TCG_TYPE_V256, | |
292 | ||
c02244a5 | 293 | TCG_TYPE_COUNT, /* number of different types */ |
c896fe29 | 294 | |
3b6dac34 | 295 | /* An alias for the size of the host register. */ |
c896fe29 | 296 | #if TCG_TARGET_REG_BITS == 32 |
3b6dac34 | 297 | TCG_TYPE_REG = TCG_TYPE_I32, |
c02244a5 | 298 | #else |
3b6dac34 | 299 | TCG_TYPE_REG = TCG_TYPE_I64, |
c02244a5 | 300 | #endif |
3b6dac34 | 301 | |
d289837e RH |
302 | /* An alias for the size of the native pointer. */ |
303 | #if UINTPTR_MAX == UINT32_MAX | |
304 | TCG_TYPE_PTR = TCG_TYPE_I32, | |
305 | #else | |
306 | TCG_TYPE_PTR = TCG_TYPE_I64, | |
307 | #endif | |
3b6dac34 RH |
308 | |
309 | /* An alias for the size of the target "long", aka register. */ | |
c02244a5 RH |
310 | #if TARGET_LONG_BITS == 64 |
311 | TCG_TYPE_TL = TCG_TYPE_I64, | |
c896fe29 | 312 | #else |
c02244a5 | 313 | TCG_TYPE_TL = TCG_TYPE_I32, |
c896fe29 | 314 | #endif |
c02244a5 | 315 | } TCGType; |
c896fe29 | 316 | |
1f00b27f SS |
317 | /** |
318 | * get_alignment_bits | |
14776ab5 | 319 | * @memop: MemOp value |
1f00b27f SS |
320 | * |
321 | * Extract the alignment size from the memop. | |
1f00b27f | 322 | */ |
14776ab5 | 323 | static inline unsigned get_alignment_bits(MemOp memop) |
1f00b27f | 324 | { |
85aa8081 | 325 | unsigned a = memop & MO_AMASK; |
1f00b27f SS |
326 | |
327 | if (a == MO_UNALN) { | |
85aa8081 RH |
328 | /* No alignment required. */ |
329 | a = 0; | |
1f00b27f | 330 | } else if (a == MO_ALIGN) { |
85aa8081 RH |
331 | /* A natural alignment requirement. */ |
332 | a = memop & MO_SIZE; | |
1f00b27f | 333 | } else { |
85aa8081 RH |
334 | /* A specific alignment requirement. */ |
335 | a = a >> MO_ASHIFT; | |
1f00b27f SS |
336 | } |
337 | #if defined(CONFIG_SOFTMMU) | |
338 | /* The requested alignment cannot overlap the TLB flags. */ | |
85aa8081 | 339 | tcg_debug_assert((TLB_FLAGS_MASK & ((1 << a) - 1)) == 0); |
1f00b27f | 340 | #endif |
85aa8081 | 341 | return a; |
1f00b27f SS |
342 | } |
343 | ||
c896fe29 FB |
344 | typedef tcg_target_ulong TCGArg; |
345 | ||
a40d4701 PM |
346 | /* Define type and accessor macros for TCG variables. |
347 | ||
348 | TCG variables are the inputs and outputs of TCG ops, as described | |
349 | in tcg/README. Target CPU front-end code uses these types to deal | |
350 | with TCG variables as it emits TCG code via the tcg_gen_* functions. | |
351 | They come in several flavours: | |
352 | * TCGv_i32 : 32 bit integer type | |
353 | * TCGv_i64 : 64 bit integer type | |
354 | * TCGv_ptr : a host pointer type | |
d2fd745f RH |
355 | * TCGv_vec : a host vector type; the exact size is not exposed |
356 | to the CPU front-end code. | |
a40d4701 PM |
357 | * TCGv : an integer type the same size as target_ulong |
358 | (an alias for either TCGv_i32 or TCGv_i64) | |
359 | The compiler's type checking will complain if you mix them | |
360 | up and pass the wrong sized TCGv to a function. | |
361 | ||
362 | Users of tcg_gen_* don't need to know about any of the internal | |
363 | details of these, and should treat them as opaque types. | |
364 | You won't be able to look inside them in a debugger either. | |
365 | ||
366 | Internal implementation details follow: | |
367 | ||
368 | Note that there is no definition of the structs TCGv_i32_d etc anywhere. | |
369 | This is deliberate, because the values we store in variables of type | |
370 | TCGv_i32 are not really pointers-to-structures. They're just small | |
371 | integers, but keeping them in pointer types like this means that the | |
372 | compiler will complain if you accidentally pass a TCGv_i32 to a | |
373 | function which takes a TCGv_i64, and so on. Only the internals of | |
dc41aa7d | 374 | TCG need to care about the actual contents of the types. */ |
ac56dd48 | 375 | |
b6c73a6d RH |
376 | typedef struct TCGv_i32_d *TCGv_i32; |
377 | typedef struct TCGv_i64_d *TCGv_i64; | |
378 | typedef struct TCGv_ptr_d *TCGv_ptr; | |
d2fd745f | 379 | typedef struct TCGv_vec_d *TCGv_vec; |
1bcea73e | 380 | typedef TCGv_ptr TCGv_env; |
5d4e1a10 LV |
381 | #if TARGET_LONG_BITS == 32 |
382 | #define TCGv TCGv_i32 | |
383 | #elif TARGET_LONG_BITS == 64 | |
384 | #define TCGv TCGv_i64 | |
385 | #else | |
386 | #error Unhandled TARGET_LONG_BITS value | |
387 | #endif | |
ac56dd48 | 388 | |
c896fe29 | 389 | /* call flags */ |
78505279 AJ |
390 | /* Helper does not read globals (either directly or through an exception). It |
391 | implies TCG_CALL_NO_WRITE_GLOBALS. */ | |
3b50352b | 392 | #define TCG_CALL_NO_READ_GLOBALS 0x0001 |
78505279 | 393 | /* Helper does not write globals */ |
3b50352b | 394 | #define TCG_CALL_NO_WRITE_GLOBALS 0x0002 |
78505279 | 395 | /* Helper can be safely suppressed if the return value is not used. */ |
3b50352b | 396 | #define TCG_CALL_NO_SIDE_EFFECTS 0x0004 |
15d74092 RH |
397 | /* Helper is QEMU_NORETURN. */ |
398 | #define TCG_CALL_NO_RETURN 0x0008 | |
78505279 AJ |
399 | |
400 | /* convenience version of most used call flags */ | |
401 | #define TCG_CALL_NO_RWG TCG_CALL_NO_READ_GLOBALS | |
402 | #define TCG_CALL_NO_WG TCG_CALL_NO_WRITE_GLOBALS | |
403 | #define TCG_CALL_NO_SE TCG_CALL_NO_SIDE_EFFECTS | |
404 | #define TCG_CALL_NO_RWG_SE (TCG_CALL_NO_RWG | TCG_CALL_NO_SE) | |
405 | #define TCG_CALL_NO_WG_SE (TCG_CALL_NO_WG | TCG_CALL_NO_SE) | |
406 | ||
e89b28a6 RH |
407 | /* Used to align parameters. See the comment before tcgv_i32_temp. */ |
408 | #define TCG_CALL_DUMMY_ARG ((TCGArg)0) | |
39cf05d3 | 409 | |
a93cf9df SW |
410 | /* Conditions. Note that these are laid out for easy manipulation by |
411 | the functions below: | |
0aed257f RH |
412 | bit 0 is used for inverting; |
413 | bit 1 is signed, | |
414 | bit 2 is unsigned, | |
415 | bit 3 is used with bit 0 for swapping signed/unsigned. */ | |
c896fe29 | 416 | typedef enum { |
0aed257f RH |
417 | /* non-signed */ |
418 | TCG_COND_NEVER = 0 | 0 | 0 | 0, | |
419 | TCG_COND_ALWAYS = 0 | 0 | 0 | 1, | |
420 | TCG_COND_EQ = 8 | 0 | 0 | 0, | |
421 | TCG_COND_NE = 8 | 0 | 0 | 1, | |
422 | /* signed */ | |
423 | TCG_COND_LT = 0 | 0 | 2 | 0, | |
424 | TCG_COND_GE = 0 | 0 | 2 | 1, | |
425 | TCG_COND_LE = 8 | 0 | 2 | 0, | |
426 | TCG_COND_GT = 8 | 0 | 2 | 1, | |
c896fe29 | 427 | /* unsigned */ |
0aed257f RH |
428 | TCG_COND_LTU = 0 | 4 | 0 | 0, |
429 | TCG_COND_GEU = 0 | 4 | 0 | 1, | |
430 | TCG_COND_LEU = 8 | 4 | 0 | 0, | |
431 | TCG_COND_GTU = 8 | 4 | 0 | 1, | |
c896fe29 FB |
432 | } TCGCond; |
433 | ||
1c086220 | 434 | /* Invert the sense of the comparison. */ |
401d466d RH |
435 | static inline TCGCond tcg_invert_cond(TCGCond c) |
436 | { | |
437 | return (TCGCond)(c ^ 1); | |
438 | } | |
439 | ||
1c086220 RH |
440 | /* Swap the operands in a comparison. */ |
441 | static inline TCGCond tcg_swap_cond(TCGCond c) | |
442 | { | |
0aed257f | 443 | return c & 6 ? (TCGCond)(c ^ 9) : c; |
1c086220 RH |
444 | } |
445 | ||
d1e321b8 | 446 | /* Create an "unsigned" version of a "signed" comparison. */ |
ff44c2f3 RH |
447 | static inline TCGCond tcg_unsigned_cond(TCGCond c) |
448 | { | |
0aed257f | 449 | return c & 2 ? (TCGCond)(c ^ 6) : c; |
ff44c2f3 RH |
450 | } |
451 | ||
923ed175 RH |
452 | /* Create a "signed" version of an "unsigned" comparison. */ |
453 | static inline TCGCond tcg_signed_cond(TCGCond c) | |
454 | { | |
455 | return c & 4 ? (TCGCond)(c ^ 6) : c; | |
456 | } | |
457 | ||
d1e321b8 | 458 | /* Must a comparison be considered unsigned? */ |
bcc66562 RH |
459 | static inline bool is_unsigned_cond(TCGCond c) |
460 | { | |
0aed257f | 461 | return (c & 4) != 0; |
bcc66562 RH |
462 | } |
463 | ||
d1e321b8 RH |
464 | /* Create a "high" version of a double-word comparison. |
465 | This removes equality from a LTE or GTE comparison. */ | |
466 | static inline TCGCond tcg_high_cond(TCGCond c) | |
467 | { | |
468 | switch (c) { | |
469 | case TCG_COND_GE: | |
470 | case TCG_COND_LE: | |
471 | case TCG_COND_GEU: | |
472 | case TCG_COND_LEU: | |
473 | return (TCGCond)(c ^ 8); | |
474 | default: | |
475 | return c; | |
476 | } | |
477 | } | |
478 | ||
00c8fa9f EC |
479 | typedef enum TCGTempVal { |
480 | TEMP_VAL_DEAD, | |
481 | TEMP_VAL_REG, | |
482 | TEMP_VAL_MEM, | |
483 | TEMP_VAL_CONST, | |
484 | } TCGTempVal; | |
c896fe29 | 485 | |
ee17db83 RH |
486 | typedef enum TCGTempKind { |
487 | /* Temp is dead at the end of all basic blocks. */ | |
488 | TEMP_NORMAL, | |
489 | /* Temp is saved across basic blocks but dead at the end of TBs. */ | |
490 | TEMP_LOCAL, | |
491 | /* Temp is saved across both basic blocks and translation blocks. */ | |
492 | TEMP_GLOBAL, | |
493 | /* Temp is in a fixed register. */ | |
494 | TEMP_FIXED, | |
c0522136 RH |
495 | /* Temp is a fixed constant. */ |
496 | TEMP_CONST, | |
ee17db83 RH |
497 | } TCGTempKind; |
498 | ||
c896fe29 | 499 | typedef struct TCGTemp { |
b6638662 | 500 | TCGReg reg:8; |
00c8fa9f EC |
501 | TCGTempVal val_type:8; |
502 | TCGType base_type:8; | |
503 | TCGType type:8; | |
ee17db83 | 504 | TCGTempKind kind:3; |
b3915dbb RH |
505 | unsigned int indirect_reg:1; |
506 | unsigned int indirect_base:1; | |
c896fe29 FB |
507 | unsigned int mem_coherent:1; |
508 | unsigned int mem_allocated:1; | |
fa477d25 | 509 | unsigned int temp_allocated:1; |
00c8fa9f | 510 | |
bdb38b95 | 511 | int64_t val; |
b3a62939 | 512 | struct TCGTemp *mem_base; |
00c8fa9f | 513 | intptr_t mem_offset; |
c896fe29 | 514 | const char *name; |
b83eabea RH |
515 | |
516 | /* Pass-specific information that can be stored for a temporary. | |
517 | One word worth of integer data, and one pointer to data | |
518 | allocated separately. */ | |
519 | uintptr_t state; | |
520 | void *state_ptr; | |
c896fe29 FB |
521 | } TCGTemp; |
522 | ||
c896fe29 FB |
523 | typedef struct TCGContext TCGContext; |
524 | ||
0ec9eabc RH |
525 | typedef struct TCGTempSet { |
526 | unsigned long l[BITS_TO_LONGS(TCG_MAX_TEMPS)]; | |
527 | } TCGTempSet; | |
528 | ||
a1b3c48d RH |
529 | /* While we limit helpers to 6 arguments, for 32-bit hosts, with padding, |
530 | this imples a max of 6*2 (64-bit in) + 2 (64-bit out) = 14 operands. | |
531 | There are never more than 2 outputs, which means that we can store all | |
532 | dead + sync data within 16 bits. */ | |
533 | #define DEAD_ARG 4 | |
534 | #define SYNC_ARG 1 | |
535 | typedef uint16_t TCGLifeData; | |
536 | ||
75e8b9b7 RH |
537 | /* The layout here is designed to avoid a bitfield crossing of |
538 | a 32-bit boundary, which would cause GCC to add extra padding. */ | |
c45cb8bb | 539 | typedef struct TCGOp { |
bee158cb RH |
540 | TCGOpcode opc : 8; /* 8 */ |
541 | ||
cd9090aa RH |
542 | /* Parameters for this opcode. See below. */ |
543 | unsigned param1 : 4; /* 12 */ | |
544 | unsigned param2 : 4; /* 16 */ | |
c45cb8bb | 545 | |
bee158cb | 546 | /* Lifetime data of the operands. */ |
15fa08f8 RH |
547 | unsigned life : 16; /* 32 */ |
548 | ||
549 | /* Next and previous opcodes. */ | |
550 | QTAILQ_ENTRY(TCGOp) link; | |
38b47b19 EC |
551 | #ifdef CONFIG_PLUGIN |
552 | QSIMPLEQ_ENTRY(TCGOp) plugin_link; | |
553 | #endif | |
75e8b9b7 RH |
554 | |
555 | /* Arguments for the opcode. */ | |
556 | TCGArg args[MAX_OPC_PARAM]; | |
69e3706d RH |
557 | |
558 | /* Register preferences for the output(s). */ | |
559 | TCGRegSet output_pref[2]; | |
c45cb8bb RH |
560 | } TCGOp; |
561 | ||
cd9090aa RH |
562 | #define TCGOP_CALLI(X) (X)->param1 |
563 | #define TCGOP_CALLO(X) (X)->param2 | |
564 | ||
d2fd745f RH |
565 | #define TCGOP_VECL(X) (X)->param1 |
566 | #define TCGOP_VECE(X) (X)->param2 | |
567 | ||
dcb8e758 RH |
568 | /* Make sure operands fit in the bitfields above. */ |
569 | QEMU_BUILD_BUG_ON(NB_OPS > (1 << 8)); | |
c45cb8bb | 570 | |
c3fac113 | 571 | typedef struct TCGProfile { |
72fd2efb | 572 | int64_t cpu_exec_time; |
c3fac113 EC |
573 | int64_t tb_count1; |
574 | int64_t tb_count; | |
575 | int64_t op_count; /* total insn count */ | |
576 | int op_count_max; /* max insn per TB */ | |
c3fac113 | 577 | int temp_count_max; |
dd1d7da2 | 578 | int64_t temp_count; |
c3fac113 EC |
579 | int64_t del_op_count; |
580 | int64_t code_in_len; | |
581 | int64_t code_out_len; | |
582 | int64_t search_out_len; | |
583 | int64_t interm_time; | |
584 | int64_t code_time; | |
585 | int64_t la_time; | |
586 | int64_t opt_time; | |
587 | int64_t restore_count; | |
588 | int64_t restore_time; | |
589 | int64_t table_op_count[NB_OPS]; | |
590 | } TCGProfile; | |
591 | ||
c896fe29 FB |
592 | struct TCGContext { |
593 | uint8_t *pool_cur, *pool_end; | |
4055299e | 594 | TCGPool *pool_first, *pool_current, *pool_first_large; |
c896fe29 | 595 | int nb_labels; |
c896fe29 FB |
596 | int nb_globals; |
597 | int nb_temps; | |
5a18407f | 598 | int nb_indirects; |
abebf925 | 599 | int nb_ops; |
c896fe29 FB |
600 | |
601 | /* goto_tb support */ | |
1813e175 | 602 | tcg_insn_unit *code_buf; |
f309101c | 603 | uint16_t *tb_jmp_reset_offset; /* tb->jmp_reset_offset */ |
a8583393 RH |
604 | uintptr_t *tb_jmp_insn_offset; /* tb->jmp_target_arg if direct_jump */ |
605 | uintptr_t *tb_jmp_target_addr; /* tb->jmp_target_arg if !direct_jump */ | |
c896fe29 | 606 | |
c896fe29 | 607 | TCGRegSet reserved_regs; |
e82d5a24 | 608 | uint32_t tb_cflags; /* cflags of the current TB */ |
e2c6d1b4 RH |
609 | intptr_t current_frame_offset; |
610 | intptr_t frame_start; | |
611 | intptr_t frame_end; | |
b3a62939 | 612 | TCGTemp *frame_temp; |
c896fe29 | 613 | |
1813e175 | 614 | tcg_insn_unit *code_ptr; |
c896fe29 | 615 | |
a23a9ec6 | 616 | #ifdef CONFIG_PROFILER |
c3fac113 | 617 | TCGProfile prof; |
a23a9ec6 | 618 | #endif |
27bfd83c PM |
619 | |
620 | #ifdef CONFIG_DEBUG_TCG | |
621 | int temps_in_use; | |
0a209d4b | 622 | int goto_tb_issue_mask; |
53229a77 | 623 | const TCGOpcode *vecop_list; |
27bfd83c | 624 | #endif |
b76f0d8c | 625 | |
1813e175 RH |
626 | /* Code generation. Note that we specifically do not use tcg_insn_unit |
627 | here, because there's too much arithmetic throughout that relies | |
628 | on addition and subtraction working on bytes. Rely on the GCC | |
629 | extension that allows arithmetic on void*. */ | |
1813e175 | 630 | void *code_gen_buffer; |
0b0d3320 | 631 | size_t code_gen_buffer_size; |
1813e175 | 632 | void *code_gen_ptr; |
57a26946 | 633 | void *data_gen_ptr; |
0b0d3320 | 634 | |
b125f9dc RH |
635 | /* Threshold to flush the translated code buffer. */ |
636 | void *code_gen_highwater; | |
637 | ||
128ed227 EC |
638 | size_t tb_phys_invalidate_count; |
639 | ||
7c255043 LV |
640 | /* Track which vCPU triggers events */ |
641 | CPUState *cpu; /* *_trans */ | |
7c255043 | 642 | |
139c1837 | 643 | /* These structures are private to tcg-target.c.inc. */ |
659ef5cb | 644 | #ifdef TCG_TARGET_NEED_LDST_LABELS |
b58deb34 | 645 | QSIMPLEQ_HEAD(, TCGLabelQemuLdst) ldst_labels; |
659ef5cb | 646 | #endif |
57a26946 RH |
647 | #ifdef TCG_TARGET_NEED_POOL_LABELS |
648 | struct TCGLabelPoolData *pool_labels; | |
649 | #endif | |
c45cb8bb | 650 | |
26689780 EC |
651 | TCGLabel *exitreq_label; |
652 | ||
38b47b19 EC |
653 | #ifdef CONFIG_PLUGIN |
654 | /* | |
655 | * We keep one plugin_tb struct per TCGContext. Note that on every TB | |
656 | * translation we clear but do not free its contents; this way we | |
657 | * avoid a lot of malloc/free churn, since after a few TB's it's | |
658 | * unlikely that we'll need to allocate either more instructions or more | |
659 | * space for instructions (for variable-instruction-length ISAs). | |
660 | */ | |
661 | struct qemu_plugin_tb *plugin_tb; | |
662 | ||
663 | /* descriptor of the instruction being translated */ | |
664 | struct qemu_plugin_insn *plugin_insn; | |
665 | ||
666 | /* list to quickly access the injected ops */ | |
667 | QSIMPLEQ_HEAD(, TCGOp) plugin_ops; | |
668 | #endif | |
669 | ||
c0522136 | 670 | GHashTable *const_table[TCG_TYPE_COUNT]; |
c45cb8bb RH |
671 | TCGTempSet free_temps[TCG_TYPE_COUNT * 2]; |
672 | TCGTemp temps[TCG_MAX_TEMPS]; /* globals first, temps after */ | |
673 | ||
eae3eb3e | 674 | QTAILQ_HEAD(, TCGOp) ops, free_ops; |
7ecd02a0 | 675 | QSIMPLEQ_HEAD(, TCGLabel) labels; |
15fa08f8 | 676 | |
f8b2f202 RH |
677 | /* Tells which temporary holds a given register. |
678 | It does not take into account fixed registers */ | |
679 | TCGTemp *reg_to_temp[TCG_TARGET_NB_REGS]; | |
c45cb8bb | 680 | |
fca8a500 RH |
681 | uint16_t gen_insn_end_off[TCG_MAX_INSNS]; |
682 | target_ulong gen_insn_data[TCG_MAX_INSNS][TARGET_INSN_START_WORDS]; | |
c896fe29 FB |
683 | }; |
684 | ||
e01fa97d RH |
685 | static inline bool temp_readonly(TCGTemp *ts) |
686 | { | |
c0522136 | 687 | return ts->kind >= TEMP_FIXED; |
e01fa97d RH |
688 | } |
689 | ||
b1311c4a | 690 | extern TCGContext tcg_init_ctx; |
3468b59e | 691 | extern __thread TCGContext *tcg_ctx; |
c8bc1168 | 692 | extern const void *tcg_code_gen_epilogue; |
db0c51a3 | 693 | extern uintptr_t tcg_splitwx_diff; |
1c2adb95 | 694 | extern TCGv_env cpu_env; |
c896fe29 | 695 | |
4846cd37 RH |
696 | static inline bool in_code_gen_buffer(const void *p) |
697 | { | |
698 | const TCGContext *s = &tcg_init_ctx; | |
699 | /* | |
700 | * Much like it is valid to have a pointer to the byte past the | |
701 | * end of an array (so long as you don't dereference it), allow | |
702 | * a pointer to the byte past the end of the code gen buffer. | |
703 | */ | |
704 | return (size_t)(p - s->code_gen_buffer) <= s->code_gen_buffer_size; | |
705 | } | |
706 | ||
db0c51a3 RH |
707 | #ifdef CONFIG_DEBUG_TCG |
708 | const void *tcg_splitwx_to_rx(void *rw); | |
709 | void *tcg_splitwx_to_rw(const void *rx); | |
710 | #else | |
711 | static inline const void *tcg_splitwx_to_rx(void *rw) | |
712 | { | |
713 | return rw ? rw + tcg_splitwx_diff : NULL; | |
714 | } | |
715 | ||
716 | static inline void *tcg_splitwx_to_rw(const void *rx) | |
717 | { | |
718 | return rx ? (void *)rx - tcg_splitwx_diff : NULL; | |
719 | } | |
720 | #endif | |
721 | ||
1807f4c4 RH |
722 | static inline size_t temp_idx(TCGTemp *ts) |
723 | { | |
b1311c4a EC |
724 | ptrdiff_t n = ts - tcg_ctx->temps; |
725 | tcg_debug_assert(n >= 0 && n < tcg_ctx->nb_temps); | |
1807f4c4 RH |
726 | return n; |
727 | } | |
728 | ||
729 | static inline TCGArg temp_arg(TCGTemp *ts) | |
730 | { | |
e89b28a6 | 731 | return (uintptr_t)ts; |
1807f4c4 RH |
732 | } |
733 | ||
43439139 RH |
734 | static inline TCGTemp *arg_temp(TCGArg a) |
735 | { | |
e89b28a6 | 736 | return (TCGTemp *)(uintptr_t)a; |
43439139 RH |
737 | } |
738 | ||
e89b28a6 RH |
739 | /* Using the offset of a temporary, relative to TCGContext, rather than |
740 | its index means that we don't use 0. That leaves offset 0 free for | |
741 | a NULL representation without having to leave index 0 unused. */ | |
742 | static inline TCGTemp *tcgv_i32_temp(TCGv_i32 v) | |
6349039d | 743 | { |
e89b28a6 | 744 | uintptr_t o = (uintptr_t)v; |
b1311c4a | 745 | TCGTemp *t = (void *)tcg_ctx + o; |
e89b28a6 RH |
746 | tcg_debug_assert(offsetof(TCGContext, temps[temp_idx(t)]) == o); |
747 | return t; | |
ae8b75dc RH |
748 | } |
749 | ||
e89b28a6 | 750 | static inline TCGTemp *tcgv_i64_temp(TCGv_i64 v) |
ae8b75dc | 751 | { |
e89b28a6 | 752 | return tcgv_i32_temp((TCGv_i32)v); |
ae8b75dc RH |
753 | } |
754 | ||
e89b28a6 | 755 | static inline TCGTemp *tcgv_ptr_temp(TCGv_ptr v) |
ae8b75dc | 756 | { |
e89b28a6 | 757 | return tcgv_i32_temp((TCGv_i32)v); |
ae8b75dc RH |
758 | } |
759 | ||
d2fd745f RH |
760 | static inline TCGTemp *tcgv_vec_temp(TCGv_vec v) |
761 | { | |
762 | return tcgv_i32_temp((TCGv_i32)v); | |
763 | } | |
764 | ||
e89b28a6 | 765 | static inline TCGArg tcgv_i32_arg(TCGv_i32 v) |
ae8b75dc | 766 | { |
e89b28a6 | 767 | return temp_arg(tcgv_i32_temp(v)); |
ae8b75dc RH |
768 | } |
769 | ||
e89b28a6 | 770 | static inline TCGArg tcgv_i64_arg(TCGv_i64 v) |
ae8b75dc | 771 | { |
e89b28a6 | 772 | return temp_arg(tcgv_i64_temp(v)); |
ae8b75dc RH |
773 | } |
774 | ||
e89b28a6 | 775 | static inline TCGArg tcgv_ptr_arg(TCGv_ptr v) |
ae8b75dc | 776 | { |
e89b28a6 | 777 | return temp_arg(tcgv_ptr_temp(v)); |
ae8b75dc RH |
778 | } |
779 | ||
d2fd745f RH |
780 | static inline TCGArg tcgv_vec_arg(TCGv_vec v) |
781 | { | |
782 | return temp_arg(tcgv_vec_temp(v)); | |
783 | } | |
784 | ||
085272b3 RH |
785 | static inline TCGv_i32 temp_tcgv_i32(TCGTemp *t) |
786 | { | |
e89b28a6 | 787 | (void)temp_idx(t); /* trigger embedded assert */ |
b1311c4a | 788 | return (TCGv_i32)((void *)t - (void *)tcg_ctx); |
085272b3 RH |
789 | } |
790 | ||
791 | static inline TCGv_i64 temp_tcgv_i64(TCGTemp *t) | |
792 | { | |
e89b28a6 | 793 | return (TCGv_i64)temp_tcgv_i32(t); |
085272b3 RH |
794 | } |
795 | ||
796 | static inline TCGv_ptr temp_tcgv_ptr(TCGTemp *t) | |
797 | { | |
e89b28a6 | 798 | return (TCGv_ptr)temp_tcgv_i32(t); |
085272b3 RH |
799 | } |
800 | ||
d2fd745f RH |
801 | static inline TCGv_vec temp_tcgv_vec(TCGTemp *t) |
802 | { | |
803 | return (TCGv_vec)temp_tcgv_i32(t); | |
804 | } | |
805 | ||
dc41aa7d RH |
806 | #if TCG_TARGET_REG_BITS == 32 |
807 | static inline TCGv_i32 TCGV_LOW(TCGv_i64 t) | |
808 | { | |
809 | return temp_tcgv_i32(tcgv_i64_temp(t)); | |
810 | } | |
811 | ||
812 | static inline TCGv_i32 TCGV_HIGH(TCGv_i64 t) | |
813 | { | |
814 | return temp_tcgv_i32(tcgv_i64_temp(t) + 1); | |
815 | } | |
816 | #endif | |
817 | ||
2271a6ac RH |
818 | static inline TCGArg tcg_get_insn_param(TCGOp *op, int arg) |
819 | { | |
820 | return op->args[arg]; | |
821 | } | |
822 | ||
15fa08f8 | 823 | static inline void tcg_set_insn_param(TCGOp *op, int arg, TCGArg v) |
1d41478f | 824 | { |
15fa08f8 | 825 | op->args[arg] = v; |
1d41478f EI |
826 | } |
827 | ||
2271a6ac RH |
828 | static inline target_ulong tcg_get_insn_start_param(TCGOp *op, int arg) |
829 | { | |
830 | #if TARGET_LONG_BITS <= TCG_TARGET_REG_BITS | |
831 | return tcg_get_insn_param(op, arg); | |
832 | #else | |
833 | return tcg_get_insn_param(op, arg * 2) | | |
834 | ((uint64_t)tcg_get_insn_param(op, arg * 2 + 1) << 32); | |
835 | #endif | |
836 | } | |
837 | ||
9743cd57 RH |
838 | static inline void tcg_set_insn_start_param(TCGOp *op, int arg, target_ulong v) |
839 | { | |
840 | #if TARGET_LONG_BITS <= TCG_TARGET_REG_BITS | |
841 | tcg_set_insn_param(op, arg, v); | |
842 | #else | |
843 | tcg_set_insn_param(op, arg * 2, v); | |
844 | tcg_set_insn_param(op, arg * 2 + 1, v >> 32); | |
845 | #endif | |
846 | } | |
847 | ||
15fa08f8 RH |
848 | /* The last op that was emitted. */ |
849 | static inline TCGOp *tcg_last_op(void) | |
fe700adb | 850 | { |
eae3eb3e | 851 | return QTAILQ_LAST(&tcg_ctx->ops); |
fe700adb RH |
852 | } |
853 | ||
854 | /* Test for whether to terminate the TB for using too many opcodes. */ | |
855 | static inline bool tcg_op_buf_full(void) | |
856 | { | |
abebf925 RH |
857 | /* This is not a hard limit, it merely stops translation when |
858 | * we have produced "enough" opcodes. We want to limit TB size | |
859 | * such that a RISC host can reasonably use a 16-bit signed | |
9f754620 RH |
860 | * branch within the TB. We also need to be mindful of the |
861 | * 16-bit unsigned offsets, TranslationBlock.jmp_reset_offset[] | |
862 | * and TCGContext.gen_insn_end_off[]. | |
abebf925 | 863 | */ |
9f754620 | 864 | return tcg_ctx->nb_ops >= 4000; |
fe700adb RH |
865 | } |
866 | ||
c896fe29 FB |
867 | /* pool based memory allocation */ |
868 | ||
0ac20318 | 869 | /* user-mode: mmap_lock must be held for tcg_malloc_internal. */ |
c896fe29 FB |
870 | void *tcg_malloc_internal(TCGContext *s, int size); |
871 | void tcg_pool_reset(TCGContext *s); | |
6e3b2bfd | 872 | TranslationBlock *tcg_tb_alloc(TCGContext *s); |
c896fe29 | 873 | |
e8feb96f | 874 | void tcg_region_init(void); |
938e897a | 875 | void tb_destroy(TranslationBlock *tb); |
e8feb96f EC |
876 | void tcg_region_reset_all(void); |
877 | ||
878 | size_t tcg_code_size(void); | |
879 | size_t tcg_code_capacity(void); | |
880 | ||
be2cdc5e EC |
881 | void tcg_tb_insert(TranslationBlock *tb); |
882 | void tcg_tb_remove(TranslationBlock *tb); | |
128ed227 | 883 | size_t tcg_tb_phys_invalidate_count(void); |
be2cdc5e EC |
884 | TranslationBlock *tcg_tb_lookup(uintptr_t tc_ptr); |
885 | void tcg_tb_foreach(GTraverseFunc func, gpointer user_data); | |
886 | size_t tcg_nb_tbs(void); | |
887 | ||
0ac20318 | 888 | /* user-mode: Called with mmap_lock held. */ |
c896fe29 FB |
889 | static inline void *tcg_malloc(int size) |
890 | { | |
b1311c4a | 891 | TCGContext *s = tcg_ctx; |
c896fe29 | 892 | uint8_t *ptr, *ptr_end; |
13aaef67 RH |
893 | |
894 | /* ??? This is a weak placeholder for minimum malloc alignment. */ | |
895 | size = QEMU_ALIGN_UP(size, 8); | |
896 | ||
c896fe29 FB |
897 | ptr = s->pool_cur; |
898 | ptr_end = ptr + size; | |
899 | if (unlikely(ptr_end > s->pool_end)) { | |
b1311c4a | 900 | return tcg_malloc_internal(tcg_ctx, size); |
c896fe29 FB |
901 | } else { |
902 | s->pool_cur = ptr_end; | |
903 | return ptr; | |
904 | } | |
905 | } | |
906 | ||
907 | void tcg_context_init(TCGContext *s); | |
3468b59e | 908 | void tcg_register_thread(void); |
9002ec79 | 909 | void tcg_prologue_init(TCGContext *s); |
c896fe29 FB |
910 | void tcg_func_start(TCGContext *s); |
911 | ||
5bd2ec3d | 912 | int tcg_gen_code(TCGContext *s, TranslationBlock *tb); |
c896fe29 | 913 | |
b6638662 | 914 | void tcg_set_frame(TCGContext *s, TCGReg reg, intptr_t start, intptr_t size); |
a7812ae4 | 915 | |
085272b3 RH |
916 | TCGTemp *tcg_global_mem_new_internal(TCGType, TCGv_ptr, |
917 | intptr_t, const char *); | |
5bfa8034 RH |
918 | TCGTemp *tcg_temp_new_internal(TCGType, bool); |
919 | void tcg_temp_free_internal(TCGTemp *); | |
d2fd745f RH |
920 | TCGv_vec tcg_temp_new_vec(TCGType type); |
921 | TCGv_vec tcg_temp_new_vec_matching(TCGv_vec match); | |
e1ccc054 | 922 | |
5bfa8034 RH |
923 | static inline void tcg_temp_free_i32(TCGv_i32 arg) |
924 | { | |
925 | tcg_temp_free_internal(tcgv_i32_temp(arg)); | |
926 | } | |
927 | ||
928 | static inline void tcg_temp_free_i64(TCGv_i64 arg) | |
929 | { | |
930 | tcg_temp_free_internal(tcgv_i64_temp(arg)); | |
931 | } | |
932 | ||
933 | static inline void tcg_temp_free_ptr(TCGv_ptr arg) | |
934 | { | |
935 | tcg_temp_free_internal(tcgv_ptr_temp(arg)); | |
936 | } | |
937 | ||
938 | static inline void tcg_temp_free_vec(TCGv_vec arg) | |
939 | { | |
940 | tcg_temp_free_internal(tcgv_vec_temp(arg)); | |
941 | } | |
e1ccc054 | 942 | |
e1ccc054 RH |
943 | static inline TCGv_i32 tcg_global_mem_new_i32(TCGv_ptr reg, intptr_t offset, |
944 | const char *name) | |
945 | { | |
085272b3 RH |
946 | TCGTemp *t = tcg_global_mem_new_internal(TCG_TYPE_I32, reg, offset, name); |
947 | return temp_tcgv_i32(t); | |
e1ccc054 RH |
948 | } |
949 | ||
a7812ae4 PB |
950 | static inline TCGv_i32 tcg_temp_new_i32(void) |
951 | { | |
5bfa8034 RH |
952 | TCGTemp *t = tcg_temp_new_internal(TCG_TYPE_I32, false); |
953 | return temp_tcgv_i32(t); | |
a7812ae4 | 954 | } |
e1ccc054 | 955 | |
a7812ae4 PB |
956 | static inline TCGv_i32 tcg_temp_local_new_i32(void) |
957 | { | |
5bfa8034 RH |
958 | TCGTemp *t = tcg_temp_new_internal(TCG_TYPE_I32, true); |
959 | return temp_tcgv_i32(t); | |
a7812ae4 | 960 | } |
a7812ae4 | 961 | |
e1ccc054 RH |
962 | static inline TCGv_i64 tcg_global_mem_new_i64(TCGv_ptr reg, intptr_t offset, |
963 | const char *name) | |
964 | { | |
085272b3 RH |
965 | TCGTemp *t = tcg_global_mem_new_internal(TCG_TYPE_I64, reg, offset, name); |
966 | return temp_tcgv_i64(t); | |
e1ccc054 RH |
967 | } |
968 | ||
a7812ae4 | 969 | static inline TCGv_i64 tcg_temp_new_i64(void) |
641d5fbe | 970 | { |
5bfa8034 RH |
971 | TCGTemp *t = tcg_temp_new_internal(TCG_TYPE_I64, false); |
972 | return temp_tcgv_i64(t); | |
641d5fbe | 973 | } |
e1ccc054 | 974 | |
a7812ae4 | 975 | static inline TCGv_i64 tcg_temp_local_new_i64(void) |
641d5fbe | 976 | { |
5bfa8034 RH |
977 | TCGTemp *t = tcg_temp_new_internal(TCG_TYPE_I64, true); |
978 | return temp_tcgv_i64(t); | |
979 | } | |
980 | ||
981 | static inline TCGv_ptr tcg_global_mem_new_ptr(TCGv_ptr reg, intptr_t offset, | |
982 | const char *name) | |
983 | { | |
984 | TCGTemp *t = tcg_global_mem_new_internal(TCG_TYPE_PTR, reg, offset, name); | |
985 | return temp_tcgv_ptr(t); | |
986 | } | |
987 | ||
988 | static inline TCGv_ptr tcg_temp_new_ptr(void) | |
989 | { | |
990 | TCGTemp *t = tcg_temp_new_internal(TCG_TYPE_PTR, false); | |
991 | return temp_tcgv_ptr(t); | |
992 | } | |
993 | ||
994 | static inline TCGv_ptr tcg_temp_local_new_ptr(void) | |
995 | { | |
996 | TCGTemp *t = tcg_temp_new_internal(TCG_TYPE_PTR, true); | |
997 | return temp_tcgv_ptr(t); | |
641d5fbe | 998 | } |
a7812ae4 | 999 | |
27bfd83c PM |
1000 | #if defined(CONFIG_DEBUG_TCG) |
1001 | /* If you call tcg_clear_temp_count() at the start of a section of | |
1002 | * code which is not supposed to leak any TCG temporaries, then | |
1003 | * calling tcg_check_temp_count() at the end of the section will | |
1004 | * return 1 if the section did in fact leak a temporary. | |
1005 | */ | |
1006 | void tcg_clear_temp_count(void); | |
1007 | int tcg_check_temp_count(void); | |
1008 | #else | |
1009 | #define tcg_clear_temp_count() do { } while (0) | |
1010 | #define tcg_check_temp_count() 0 | |
1011 | #endif | |
1012 | ||
72fd2efb | 1013 | int64_t tcg_cpu_exec_time(void); |
3de2faa9 | 1014 | void tcg_dump_info(void); |
d4c51a0a | 1015 | void tcg_dump_op_count(void); |
c896fe29 | 1016 | |
bc2b17e6 | 1017 | #define TCG_CT_CONST 1 /* any constant of register size */ |
c896fe29 FB |
1018 | |
1019 | typedef struct TCGArgConstraint { | |
bc2b17e6 RH |
1020 | unsigned ct : 16; |
1021 | unsigned alias_index : 4; | |
1022 | unsigned sort_index : 4; | |
1023 | bool oalias : 1; | |
1024 | bool ialias : 1; | |
1025 | bool newreg : 1; | |
9be0d080 | 1026 | TCGRegSet regs; |
c896fe29 FB |
1027 | } TCGArgConstraint; |
1028 | ||
1029 | #define TCG_MAX_OP_ARGS 16 | |
1030 | ||
b4cb76e6 | 1031 | /* Bits for TCGOpDef->flags, 8 bits available, all used. */ |
8399ad59 | 1032 | enum { |
ae36a246 RH |
1033 | /* Instruction exits the translation block. */ |
1034 | TCG_OPF_BB_EXIT = 0x01, | |
8399ad59 | 1035 | /* Instruction defines the end of a basic block. */ |
ae36a246 | 1036 | TCG_OPF_BB_END = 0x02, |
8399ad59 | 1037 | /* Instruction clobbers call registers and potentially update globals. */ |
ae36a246 | 1038 | TCG_OPF_CALL_CLOBBER = 0x04, |
3d5c5f87 AJ |
1039 | /* Instruction has side effects: it cannot be removed if its outputs |
1040 | are not used, and might trigger exceptions. */ | |
ae36a246 | 1041 | TCG_OPF_SIDE_EFFECTS = 0x08, |
8399ad59 | 1042 | /* Instruction operands are 64-bits (otherwise 32-bits). */ |
ae36a246 | 1043 | TCG_OPF_64BIT = 0x10, |
c1a61f6c RH |
1044 | /* Instruction is optional and not implemented by the host, or insn |
1045 | is generic and should not be implemened by the host. */ | |
ae36a246 | 1046 | TCG_OPF_NOT_PRESENT = 0x20, |
d2fd745f | 1047 | /* Instruction operands are vectors. */ |
ae36a246 | 1048 | TCG_OPF_VECTOR = 0x40, |
b4cb76e6 RH |
1049 | /* Instruction is a conditional branch. */ |
1050 | TCG_OPF_COND_BRANCH = 0x80 | |
8399ad59 | 1051 | }; |
c896fe29 FB |
1052 | |
1053 | typedef struct TCGOpDef { | |
1054 | const char *name; | |
1055 | uint8_t nb_oargs, nb_iargs, nb_cargs, nb_args; | |
1056 | uint8_t flags; | |
c896fe29 | 1057 | TCGArgConstraint *args_ct; |
c896fe29 | 1058 | } TCGOpDef; |
8399ad59 RH |
1059 | |
1060 | extern TCGOpDef tcg_op_defs[]; | |
2a24374a SW |
1061 | extern const size_t tcg_op_defs_max; |
1062 | ||
c896fe29 | 1063 | typedef struct TCGTargetOpDef { |
a9751609 | 1064 | TCGOpcode op; |
c896fe29 FB |
1065 | const char *args_ct_str[TCG_MAX_OP_ARGS]; |
1066 | } TCGTargetOpDef; | |
1067 | ||
c896fe29 FB |
1068 | #define tcg_abort() \ |
1069 | do {\ | |
1070 | fprintf(stderr, "%s:%d: tcg fatal error\n", __FILE__, __LINE__);\ | |
1071 | abort();\ | |
1072 | } while (0) | |
1073 | ||
be0f34b5 RH |
1074 | bool tcg_op_supported(TCGOpcode op); |
1075 | ||
ae8b75dc | 1076 | void tcg_gen_callN(void *func, TCGTemp *ret, int nargs, TCGTemp **args); |
a7812ae4 | 1077 | |
15fa08f8 | 1078 | TCGOp *tcg_emit_op(TCGOpcode opc); |
0c627cdc | 1079 | void tcg_op_remove(TCGContext *s, TCGOp *op); |
ac1043f6 EC |
1080 | TCGOp *tcg_op_insert_before(TCGContext *s, TCGOp *op, TCGOpcode opc); |
1081 | TCGOp *tcg_op_insert_after(TCGContext *s, TCGOp *op, TCGOpcode opc); | |
5a18407f | 1082 | |
c45cb8bb | 1083 | void tcg_optimize(TCGContext *s); |
a7812ae4 | 1084 | |
c0522136 | 1085 | /* Allocate a new temporary and initialize it with a constant. */ |
a7812ae4 PB |
1086 | TCGv_i32 tcg_const_i32(int32_t val); |
1087 | TCGv_i64 tcg_const_i64(int64_t val); | |
1088 | TCGv_i32 tcg_const_local_i32(int32_t val); | |
1089 | TCGv_i64 tcg_const_local_i64(int64_t val); | |
d2fd745f RH |
1090 | TCGv_vec tcg_const_zeros_vec(TCGType); |
1091 | TCGv_vec tcg_const_ones_vec(TCGType); | |
1092 | TCGv_vec tcg_const_zeros_vec_matching(TCGv_vec); | |
1093 | TCGv_vec tcg_const_ones_vec_matching(TCGv_vec); | |
a7812ae4 | 1094 | |
c0522136 RH |
1095 | /* |
1096 | * Locate or create a read-only temporary that is a constant. | |
1097 | * This kind of temporary need not and should not be freed. | |
1098 | */ | |
1099 | TCGTemp *tcg_constant_internal(TCGType type, int64_t val); | |
1100 | ||
1101 | static inline TCGv_i32 tcg_constant_i32(int32_t val) | |
1102 | { | |
1103 | return temp_tcgv_i32(tcg_constant_internal(TCG_TYPE_I32, val)); | |
1104 | } | |
1105 | ||
1106 | static inline TCGv_i64 tcg_constant_i64(int64_t val) | |
1107 | { | |
1108 | return temp_tcgv_i64(tcg_constant_internal(TCG_TYPE_I64, val)); | |
1109 | } | |
1110 | ||
1111 | TCGv_vec tcg_constant_vec(TCGType type, unsigned vece, int64_t val); | |
88d4005b | 1112 | TCGv_vec tcg_constant_vec_matching(TCGv_vec match, unsigned vece, int64_t val); |
c0522136 | 1113 | |
5bfa8034 RH |
1114 | #if UINTPTR_MAX == UINT32_MAX |
1115 | # define tcg_const_ptr(x) ((TCGv_ptr)tcg_const_i32((intptr_t)(x))) | |
1116 | # define tcg_const_local_ptr(x) ((TCGv_ptr)tcg_const_local_i32((intptr_t)(x))) | |
1117 | #else | |
1118 | # define tcg_const_ptr(x) ((TCGv_ptr)tcg_const_i64((intptr_t)(x))) | |
1119 | # define tcg_const_local_ptr(x) ((TCGv_ptr)tcg_const_local_i64((intptr_t)(x))) | |
1120 | #endif | |
1121 | ||
42a268c2 RH |
1122 | TCGLabel *gen_new_label(void); |
1123 | ||
1124 | /** | |
1125 | * label_arg | |
1126 | * @l: label | |
1127 | * | |
1128 | * Encode a label for storage in the TCG opcode stream. | |
1129 | */ | |
1130 | ||
1131 | static inline TCGArg label_arg(TCGLabel *l) | |
1132 | { | |
51e3972c | 1133 | return (uintptr_t)l; |
42a268c2 RH |
1134 | } |
1135 | ||
1136 | /** | |
1137 | * arg_label | |
1138 | * @i: value | |
1139 | * | |
1140 | * The opposite of label_arg. Retrieve a label from the | |
1141 | * encoding of the TCG opcode stream. | |
1142 | */ | |
1143 | ||
51e3972c | 1144 | static inline TCGLabel *arg_label(TCGArg i) |
42a268c2 | 1145 | { |
51e3972c | 1146 | return (TCGLabel *)(uintptr_t)i; |
42a268c2 RH |
1147 | } |
1148 | ||
52a1f64e RH |
1149 | /** |
1150 | * tcg_ptr_byte_diff | |
1151 | * @a, @b: addresses to be differenced | |
1152 | * | |
1153 | * There are many places within the TCG backends where we need a byte | |
1154 | * difference between two pointers. While this can be accomplished | |
1155 | * with local casting, it's easy to get wrong -- especially if one is | |
1156 | * concerned with the signedness of the result. | |
1157 | * | |
1158 | * This version relies on GCC's void pointer arithmetic to get the | |
1159 | * correct result. | |
1160 | */ | |
1161 | ||
db0c51a3 | 1162 | static inline ptrdiff_t tcg_ptr_byte_diff(const void *a, const void *b) |
52a1f64e RH |
1163 | { |
1164 | return a - b; | |
1165 | } | |
1166 | ||
1167 | /** | |
1168 | * tcg_pcrel_diff | |
1169 | * @s: the tcg context | |
1170 | * @target: address of the target | |
1171 | * | |
1172 | * Produce a pc-relative difference, from the current code_ptr | |
1173 | * to the destination address. | |
1174 | */ | |
1175 | ||
db0c51a3 | 1176 | static inline ptrdiff_t tcg_pcrel_diff(TCGContext *s, const void *target) |
52a1f64e | 1177 | { |
db0c51a3 | 1178 | return tcg_ptr_byte_diff(target, tcg_splitwx_to_rx(s->code_ptr)); |
52a1f64e RH |
1179 | } |
1180 | ||
44c7197f RH |
1181 | /** |
1182 | * tcg_tbrel_diff | |
1183 | * @s: the tcg context | |
1184 | * @target: address of the target | |
1185 | * | |
1186 | * Produce a difference, from the beginning of the current TB code | |
1187 | * to the destination address. | |
1188 | */ | |
1189 | static inline ptrdiff_t tcg_tbrel_diff(TCGContext *s, const void *target) | |
1190 | { | |
1191 | return tcg_ptr_byte_diff(target, tcg_splitwx_to_rx(s->code_buf)); | |
1192 | } | |
1193 | ||
52a1f64e RH |
1194 | /** |
1195 | * tcg_current_code_size | |
1196 | * @s: the tcg context | |
1197 | * | |
1198 | * Compute the current code size within the translation block. | |
1199 | * This is used to fill in qemu's data structures for goto_tb. | |
1200 | */ | |
1201 | ||
1202 | static inline size_t tcg_current_code_size(TCGContext *s) | |
1203 | { | |
1204 | return tcg_ptr_byte_diff(s->code_ptr, s->code_buf); | |
1205 | } | |
1206 | ||
14776ab5 | 1207 | /* Combine the MemOp and mmu_idx parameters into a single value. */ |
59227d5d RH |
1208 | typedef uint32_t TCGMemOpIdx; |
1209 | ||
1210 | /** | |
1211 | * make_memop_idx | |
1212 | * @op: memory operation | |
1213 | * @idx: mmu index | |
1214 | * | |
1215 | * Encode these values into a single parameter. | |
1216 | */ | |
14776ab5 | 1217 | static inline TCGMemOpIdx make_memop_idx(MemOp op, unsigned idx) |
59227d5d RH |
1218 | { |
1219 | tcg_debug_assert(idx <= 15); | |
1220 | return (op << 4) | idx; | |
1221 | } | |
1222 | ||
1223 | /** | |
1224 | * get_memop | |
1225 | * @oi: combined op/idx parameter | |
1226 | * | |
1227 | * Extract the memory operation from the combined value. | |
1228 | */ | |
14776ab5 | 1229 | static inline MemOp get_memop(TCGMemOpIdx oi) |
59227d5d RH |
1230 | { |
1231 | return oi >> 4; | |
1232 | } | |
1233 | ||
1234 | /** | |
1235 | * get_mmuidx | |
1236 | * @oi: combined op/idx parameter | |
1237 | * | |
1238 | * Extract the mmu index from the combined value. | |
1239 | */ | |
1240 | static inline unsigned get_mmuidx(TCGMemOpIdx oi) | |
1241 | { | |
1242 | return oi & 15; | |
1243 | } | |
1244 | ||
0980011b PM |
1245 | /** |
1246 | * tcg_qemu_tb_exec: | |
819af24b | 1247 | * @env: pointer to CPUArchState for the CPU |
0980011b PM |
1248 | * @tb_ptr: address of generated code for the TB to execute |
1249 | * | |
1250 | * Start executing code from a given translation block. | |
1251 | * Where translation blocks have been linked, execution | |
1252 | * may proceed from the given TB into successive ones. | |
1253 | * Control eventually returns only when some action is needed | |
1254 | * from the top-level loop: either control must pass to a TB | |
1255 | * which has not yet been directly linked, or an asynchronous | |
1256 | * event such as an interrupt needs handling. | |
1257 | * | |
819af24b SF |
1258 | * Return: The return value is the value passed to the corresponding |
1259 | * tcg_gen_exit_tb() at translation time of the last TB attempted to execute. | |
1260 | * The value is either zero or a 4-byte aligned pointer to that TB combined | |
1261 | * with additional information in its two least significant bits. The | |
1262 | * additional information is encoded as follows: | |
0980011b PM |
1263 | * 0, 1: the link between this TB and the next is via the specified |
1264 | * TB index (0 or 1). That is, we left the TB via (the equivalent | |
1265 | * of) "goto_tb <index>". The main loop uses this to determine | |
1266 | * how to link the TB just executed to the next. | |
1267 | * 2: we are using instruction counting code generation, and we | |
1268 | * did not start executing this TB because the instruction counter | |
819af24b | 1269 | * would hit zero midway through it. In this case the pointer |
0980011b PM |
1270 | * returned is the TB we were about to execute, and the caller must |
1271 | * arrange to execute the remaining count of instructions. | |
378df4b2 PM |
1272 | * 3: we stopped because the CPU's exit_request flag was set |
1273 | * (usually meaning that there is an interrupt that needs to be | |
819af24b SF |
1274 | * handled). The pointer returned is the TB we were about to execute |
1275 | * when we noticed the pending exit request. | |
0980011b PM |
1276 | * |
1277 | * If the bottom two bits indicate an exit-via-index then the CPU | |
1278 | * state is correctly synchronised and ready for execution of the next | |
1279 | * TB (and in particular the guest PC is the address to execute next). | |
1280 | * Otherwise, we gave up on execution of this TB before it started, and | |
fee068e4 | 1281 | * the caller must fix up the CPU state by calling the CPU's |
819af24b | 1282 | * synchronize_from_tb() method with the TB pointer we return (falling |
fee068e4 PC |
1283 | * back to calling the CPU's set_pc method with tb->pb if no |
1284 | * synchronize_from_tb() method exists). | |
0980011b PM |
1285 | * |
1286 | * Note that TCG targets may use a different definition of tcg_qemu_tb_exec | |
1287 | * to this default (which just calls the prologue.code emitted by | |
1288 | * tcg_target_qemu_prologue()). | |
1289 | */ | |
07ea28b4 RH |
1290 | #define TB_EXIT_MASK 3 |
1291 | #define TB_EXIT_IDX0 0 | |
1292 | #define TB_EXIT_IDX1 1 | |
1293 | #define TB_EXIT_IDXMAX 1 | |
378df4b2 | 1294 | #define TB_EXIT_REQUESTED 3 |
0980011b | 1295 | |
b91ccb31 | 1296 | #ifdef CONFIG_TCG_INTERPRETER |
db0c51a3 | 1297 | uintptr_t tcg_qemu_tb_exec(CPUArchState *env, const void *tb_ptr); |
5a58e884 | 1298 | #else |
db0c51a3 | 1299 | typedef uintptr_t tcg_prologue_fn(CPUArchState *env, const void *tb_ptr); |
b91ccb31 | 1300 | extern tcg_prologue_fn *tcg_qemu_tb_exec; |
932a6909 | 1301 | #endif |
813da627 | 1302 | |
755bf9e5 | 1303 | void tcg_register_jit(const void *buf, size_t buf_size); |
b76f0d8c | 1304 | |
db432672 RH |
1305 | #if TCG_TARGET_MAYBE_vec |
1306 | /* Return zero if the tuple (opc, type, vece) is unsupportable; | |
1307 | return > 0 if it is directly supportable; | |
1308 | return < 0 if we must call tcg_expand_vec_op. */ | |
1309 | int tcg_can_emit_vec_op(TCGOpcode, TCGType, unsigned); | |
1310 | #else | |
1311 | static inline int tcg_can_emit_vec_op(TCGOpcode o, TCGType t, unsigned ve) | |
1312 | { | |
1313 | return 0; | |
1314 | } | |
1315 | #endif | |
1316 | ||
1317 | /* Expand the tuple (opc, type, vece) on the given arguments. */ | |
1318 | void tcg_expand_vec_op(TCGOpcode, TCGType, unsigned, TCGArg, ...); | |
1319 | ||
1320 | /* Replicate a constant C accoring to the log2 of the element size. */ | |
1321 | uint64_t dup_const(unsigned vece, uint64_t c); | |
1322 | ||
1323 | #define dup_const(VECE, C) \ | |
1324 | (__builtin_constant_p(VECE) \ | |
1325 | ? ( (VECE) == MO_8 ? 0x0101010101010101ull * (uint8_t)(C) \ | |
1326 | : (VECE) == MO_16 ? 0x0001000100010001ull * (uint16_t)(C) \ | |
1327 | : (VECE) == MO_32 ? 0x0000000100000001ull * (uint32_t)(C) \ | |
1328 | : dup_const(VECE, C)) \ | |
1329 | : dup_const(VECE, C)) | |
1330 | ||
1331 | ||
e58eb534 RH |
1332 | /* |
1333 | * Memory helpers that will be used by TCG generated code. | |
1334 | */ | |
1335 | #ifdef CONFIG_SOFTMMU | |
c8f94df5 RH |
1336 | /* Value zero-extended to tcg register size. */ |
1337 | tcg_target_ulong helper_ret_ldub_mmu(CPUArchState *env, target_ulong addr, | |
3972ef6f | 1338 | TCGMemOpIdx oi, uintptr_t retaddr); |
867b3201 | 1339 | tcg_target_ulong helper_le_lduw_mmu(CPUArchState *env, target_ulong addr, |
3972ef6f | 1340 | TCGMemOpIdx oi, uintptr_t retaddr); |
867b3201 | 1341 | tcg_target_ulong helper_le_ldul_mmu(CPUArchState *env, target_ulong addr, |
3972ef6f | 1342 | TCGMemOpIdx oi, uintptr_t retaddr); |
867b3201 | 1343 | uint64_t helper_le_ldq_mmu(CPUArchState *env, target_ulong addr, |
3972ef6f | 1344 | TCGMemOpIdx oi, uintptr_t retaddr); |
867b3201 | 1345 | tcg_target_ulong helper_be_lduw_mmu(CPUArchState *env, target_ulong addr, |
3972ef6f | 1346 | TCGMemOpIdx oi, uintptr_t retaddr); |
867b3201 | 1347 | tcg_target_ulong helper_be_ldul_mmu(CPUArchState *env, target_ulong addr, |
3972ef6f | 1348 | TCGMemOpIdx oi, uintptr_t retaddr); |
867b3201 | 1349 | uint64_t helper_be_ldq_mmu(CPUArchState *env, target_ulong addr, |
3972ef6f | 1350 | TCGMemOpIdx oi, uintptr_t retaddr); |
e58eb534 | 1351 | |
c8f94df5 RH |
1352 | /* Value sign-extended to tcg register size. */ |
1353 | tcg_target_ulong helper_ret_ldsb_mmu(CPUArchState *env, target_ulong addr, | |
3972ef6f | 1354 | TCGMemOpIdx oi, uintptr_t retaddr); |
867b3201 | 1355 | tcg_target_ulong helper_le_ldsw_mmu(CPUArchState *env, target_ulong addr, |
3972ef6f | 1356 | TCGMemOpIdx oi, uintptr_t retaddr); |
867b3201 | 1357 | tcg_target_ulong helper_le_ldsl_mmu(CPUArchState *env, target_ulong addr, |
3972ef6f | 1358 | TCGMemOpIdx oi, uintptr_t retaddr); |
867b3201 | 1359 | tcg_target_ulong helper_be_ldsw_mmu(CPUArchState *env, target_ulong addr, |
3972ef6f | 1360 | TCGMemOpIdx oi, uintptr_t retaddr); |
867b3201 | 1361 | tcg_target_ulong helper_be_ldsl_mmu(CPUArchState *env, target_ulong addr, |
3972ef6f | 1362 | TCGMemOpIdx oi, uintptr_t retaddr); |
c8f94df5 | 1363 | |
e58eb534 | 1364 | void helper_ret_stb_mmu(CPUArchState *env, target_ulong addr, uint8_t val, |
3972ef6f | 1365 | TCGMemOpIdx oi, uintptr_t retaddr); |
867b3201 | 1366 | void helper_le_stw_mmu(CPUArchState *env, target_ulong addr, uint16_t val, |
3972ef6f | 1367 | TCGMemOpIdx oi, uintptr_t retaddr); |
867b3201 | 1368 | void helper_le_stl_mmu(CPUArchState *env, target_ulong addr, uint32_t val, |
3972ef6f | 1369 | TCGMemOpIdx oi, uintptr_t retaddr); |
867b3201 | 1370 | void helper_le_stq_mmu(CPUArchState *env, target_ulong addr, uint64_t val, |
3972ef6f | 1371 | TCGMemOpIdx oi, uintptr_t retaddr); |
867b3201 | 1372 | void helper_be_stw_mmu(CPUArchState *env, target_ulong addr, uint16_t val, |
3972ef6f | 1373 | TCGMemOpIdx oi, uintptr_t retaddr); |
867b3201 | 1374 | void helper_be_stl_mmu(CPUArchState *env, target_ulong addr, uint32_t val, |
3972ef6f | 1375 | TCGMemOpIdx oi, uintptr_t retaddr); |
867b3201 | 1376 | void helper_be_stq_mmu(CPUArchState *env, target_ulong addr, uint64_t val, |
3972ef6f | 1377 | TCGMemOpIdx oi, uintptr_t retaddr); |
867b3201 RH |
1378 | |
1379 | /* Temporary aliases until backends are converted. */ | |
1380 | #ifdef TARGET_WORDS_BIGENDIAN | |
1381 | # define helper_ret_ldsw_mmu helper_be_ldsw_mmu | |
1382 | # define helper_ret_lduw_mmu helper_be_lduw_mmu | |
1383 | # define helper_ret_ldsl_mmu helper_be_ldsl_mmu | |
1384 | # define helper_ret_ldul_mmu helper_be_ldul_mmu | |
282dffc8 | 1385 | # define helper_ret_ldl_mmu helper_be_ldul_mmu |
867b3201 RH |
1386 | # define helper_ret_ldq_mmu helper_be_ldq_mmu |
1387 | # define helper_ret_stw_mmu helper_be_stw_mmu | |
1388 | # define helper_ret_stl_mmu helper_be_stl_mmu | |
1389 | # define helper_ret_stq_mmu helper_be_stq_mmu | |
1390 | #else | |
1391 | # define helper_ret_ldsw_mmu helper_le_ldsw_mmu | |
1392 | # define helper_ret_lduw_mmu helper_le_lduw_mmu | |
1393 | # define helper_ret_ldsl_mmu helper_le_ldsl_mmu | |
1394 | # define helper_ret_ldul_mmu helper_le_ldul_mmu | |
282dffc8 | 1395 | # define helper_ret_ldl_mmu helper_le_ldul_mmu |
867b3201 RH |
1396 | # define helper_ret_ldq_mmu helper_le_ldq_mmu |
1397 | # define helper_ret_stw_mmu helper_le_stw_mmu | |
1398 | # define helper_ret_stl_mmu helper_le_stl_mmu | |
1399 | # define helper_ret_stq_mmu helper_le_stq_mmu | |
1400 | #endif | |
e58eb534 | 1401 | |
c482cb11 RH |
1402 | uint32_t helper_atomic_cmpxchgb_mmu(CPUArchState *env, target_ulong addr, |
1403 | uint32_t cmpv, uint32_t newv, | |
1404 | TCGMemOpIdx oi, uintptr_t retaddr); | |
1405 | uint32_t helper_atomic_cmpxchgw_le_mmu(CPUArchState *env, target_ulong addr, | |
1406 | uint32_t cmpv, uint32_t newv, | |
1407 | TCGMemOpIdx oi, uintptr_t retaddr); | |
1408 | uint32_t helper_atomic_cmpxchgl_le_mmu(CPUArchState *env, target_ulong addr, | |
1409 | uint32_t cmpv, uint32_t newv, | |
1410 | TCGMemOpIdx oi, uintptr_t retaddr); | |
1411 | uint64_t helper_atomic_cmpxchgq_le_mmu(CPUArchState *env, target_ulong addr, | |
1412 | uint64_t cmpv, uint64_t newv, | |
1413 | TCGMemOpIdx oi, uintptr_t retaddr); | |
1414 | uint32_t helper_atomic_cmpxchgw_be_mmu(CPUArchState *env, target_ulong addr, | |
1415 | uint32_t cmpv, uint32_t newv, | |
1416 | TCGMemOpIdx oi, uintptr_t retaddr); | |
1417 | uint32_t helper_atomic_cmpxchgl_be_mmu(CPUArchState *env, target_ulong addr, | |
1418 | uint32_t cmpv, uint32_t newv, | |
1419 | TCGMemOpIdx oi, uintptr_t retaddr); | |
1420 | uint64_t helper_atomic_cmpxchgq_be_mmu(CPUArchState *env, target_ulong addr, | |
1421 | uint64_t cmpv, uint64_t newv, | |
1422 | TCGMemOpIdx oi, uintptr_t retaddr); | |
1423 | ||
1424 | #define GEN_ATOMIC_HELPER(NAME, TYPE, SUFFIX) \ | |
1425 | TYPE helper_atomic_ ## NAME ## SUFFIX ## _mmu \ | |
1426 | (CPUArchState *env, target_ulong addr, TYPE val, \ | |
1427 | TCGMemOpIdx oi, uintptr_t retaddr); | |
1428 | ||
df79b996 | 1429 | #ifdef CONFIG_ATOMIC64 |
c482cb11 | 1430 | #define GEN_ATOMIC_HELPER_ALL(NAME) \ |
df79b996 | 1431 | GEN_ATOMIC_HELPER(NAME, uint32_t, b) \ |
c482cb11 | 1432 | GEN_ATOMIC_HELPER(NAME, uint32_t, w_le) \ |
c482cb11 | 1433 | GEN_ATOMIC_HELPER(NAME, uint32_t, w_be) \ |
df79b996 | 1434 | GEN_ATOMIC_HELPER(NAME, uint32_t, l_le) \ |
c482cb11 | 1435 | GEN_ATOMIC_HELPER(NAME, uint32_t, l_be) \ |
df79b996 | 1436 | GEN_ATOMIC_HELPER(NAME, uint64_t, q_le) \ |
c482cb11 | 1437 | GEN_ATOMIC_HELPER(NAME, uint64_t, q_be) |
df79b996 RH |
1438 | #else |
1439 | #define GEN_ATOMIC_HELPER_ALL(NAME) \ | |
1440 | GEN_ATOMIC_HELPER(NAME, uint32_t, b) \ | |
1441 | GEN_ATOMIC_HELPER(NAME, uint32_t, w_le) \ | |
1442 | GEN_ATOMIC_HELPER(NAME, uint32_t, w_be) \ | |
1443 | GEN_ATOMIC_HELPER(NAME, uint32_t, l_le) \ | |
1444 | GEN_ATOMIC_HELPER(NAME, uint32_t, l_be) | |
1445 | #endif | |
c482cb11 RH |
1446 | |
1447 | GEN_ATOMIC_HELPER_ALL(fetch_add) | |
1448 | GEN_ATOMIC_HELPER_ALL(fetch_sub) | |
1449 | GEN_ATOMIC_HELPER_ALL(fetch_and) | |
1450 | GEN_ATOMIC_HELPER_ALL(fetch_or) | |
1451 | GEN_ATOMIC_HELPER_ALL(fetch_xor) | |
5507c2bf RH |
1452 | GEN_ATOMIC_HELPER_ALL(fetch_smin) |
1453 | GEN_ATOMIC_HELPER_ALL(fetch_umin) | |
1454 | GEN_ATOMIC_HELPER_ALL(fetch_smax) | |
1455 | GEN_ATOMIC_HELPER_ALL(fetch_umax) | |
c482cb11 RH |
1456 | |
1457 | GEN_ATOMIC_HELPER_ALL(add_fetch) | |
1458 | GEN_ATOMIC_HELPER_ALL(sub_fetch) | |
1459 | GEN_ATOMIC_HELPER_ALL(and_fetch) | |
1460 | GEN_ATOMIC_HELPER_ALL(or_fetch) | |
1461 | GEN_ATOMIC_HELPER_ALL(xor_fetch) | |
5507c2bf RH |
1462 | GEN_ATOMIC_HELPER_ALL(smin_fetch) |
1463 | GEN_ATOMIC_HELPER_ALL(umin_fetch) | |
1464 | GEN_ATOMIC_HELPER_ALL(smax_fetch) | |
1465 | GEN_ATOMIC_HELPER_ALL(umax_fetch) | |
c482cb11 RH |
1466 | |
1467 | GEN_ATOMIC_HELPER_ALL(xchg) | |
1468 | ||
1469 | #undef GEN_ATOMIC_HELPER_ALL | |
1470 | #undef GEN_ATOMIC_HELPER | |
e58eb534 RH |
1471 | #endif /* CONFIG_SOFTMMU */ |
1472 | ||
e6cd4bb5 RH |
1473 | /* |
1474 | * These aren't really a "proper" helpers because TCG cannot manage Int128. | |
1475 | * However, use the same format as the others, for use by the backends. | |
1476 | * | |
1477 | * The cmpxchg functions are only defined if HAVE_CMPXCHG128; | |
1478 | * the ld/st functions are only defined if HAVE_ATOMIC128, | |
1479 | * as defined by <qemu/atomic128.h>. | |
1480 | */ | |
7ebee43e RH |
1481 | Int128 helper_atomic_cmpxchgo_le_mmu(CPUArchState *env, target_ulong addr, |
1482 | Int128 cmpv, Int128 newv, | |
1483 | TCGMemOpIdx oi, uintptr_t retaddr); | |
1484 | Int128 helper_atomic_cmpxchgo_be_mmu(CPUArchState *env, target_ulong addr, | |
1485 | Int128 cmpv, Int128 newv, | |
1486 | TCGMemOpIdx oi, uintptr_t retaddr); | |
1487 | ||
1488 | Int128 helper_atomic_ldo_le_mmu(CPUArchState *env, target_ulong addr, | |
1489 | TCGMemOpIdx oi, uintptr_t retaddr); | |
1490 | Int128 helper_atomic_ldo_be_mmu(CPUArchState *env, target_ulong addr, | |
1491 | TCGMemOpIdx oi, uintptr_t retaddr); | |
1492 | void helper_atomic_sto_le_mmu(CPUArchState *env, target_ulong addr, Int128 val, | |
1493 | TCGMemOpIdx oi, uintptr_t retaddr); | |
1494 | void helper_atomic_sto_be_mmu(CPUArchState *env, target_ulong addr, Int128 val, | |
1495 | TCGMemOpIdx oi, uintptr_t retaddr); | |
1496 | ||
53229a77 RH |
1497 | #ifdef CONFIG_DEBUG_TCG |
1498 | void tcg_assert_listed_vecop(TCGOpcode); | |
1499 | #else | |
1500 | static inline void tcg_assert_listed_vecop(TCGOpcode op) { } | |
1501 | #endif | |
1502 | ||
1503 | static inline const TCGOpcode *tcg_swap_vecop_list(const TCGOpcode *n) | |
1504 | { | |
1505 | #ifdef CONFIG_DEBUG_TCG | |
1506 | const TCGOpcode *o = tcg_ctx->vecop_list; | |
1507 | tcg_ctx->vecop_list = n; | |
1508 | return o; | |
1509 | #else | |
1510 | return NULL; | |
1511 | #endif | |
1512 | } | |
1513 | ||
1514 | bool tcg_can_emit_vecop_list(const TCGOpcode *, TCGType, unsigned); | |
1515 | ||
e58eb534 | 1516 | #endif /* TCG_H */ |