]>
Commit | Line | Data |
---|---|---|
c896fe29 FB |
1 | /* |
2 | * Tiny Code Generator for QEMU | |
3 | * | |
4 | * Copyright (c) 2008 Fabrice Bellard | |
5 | * | |
6 | * Permission is hereby granted, free of charge, to any person obtaining a copy | |
7 | * of this software and associated documentation files (the "Software"), to deal | |
8 | * in the Software without restriction, including without limitation the rights | |
9 | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell | |
10 | * copies of the Software, and to permit persons to whom the Software is | |
11 | * furnished to do so, subject to the following conditions: | |
12 | * | |
13 | * The above copyright notice and this permission notice shall be included in | |
14 | * all copies or substantial portions of the Software. | |
15 | * | |
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
19 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
20 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, | |
21 | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN | |
22 | * THE SOFTWARE. | |
23 | */ | |
e58eb534 RH |
24 | |
25 | #ifndef TCG_H | |
26 | #define TCG_H | |
27 | ||
33c11879 | 28 | #include "cpu.h" |
14776ab5 | 29 | #include "exec/memop.h" |
0ec9eabc | 30 | #include "qemu/bitops.h" |
e6d86bed | 31 | #include "qemu/plugin.h" |
15fa08f8 | 32 | #include "qemu/queue.h" |
dcb32f1d | 33 | #include "tcg/tcg-mo.h" |
78cd7b83 | 34 | #include "tcg-target.h" |
e6cd4bb5 | 35 | #include "qemu/int128.h" |
78cd7b83 | 36 | |
00f6da6a PB |
37 | /* XXX: make safe guess about sizes */ |
38 | #define MAX_OP_PER_INSTR 266 | |
39 | ||
40 | #if HOST_LONG_BITS == 32 | |
41 | #define MAX_OPC_PARAM_PER_ARG 2 | |
42 | #else | |
43 | #define MAX_OPC_PARAM_PER_ARG 1 | |
44 | #endif | |
1df3caa9 | 45 | #define MAX_OPC_PARAM_IARGS 6 |
00f6da6a PB |
46 | #define MAX_OPC_PARAM_OARGS 1 |
47 | #define MAX_OPC_PARAM_ARGS (MAX_OPC_PARAM_IARGS + MAX_OPC_PARAM_OARGS) | |
48 | ||
49 | /* A Call op needs up to 4 + 2N parameters on 32-bit archs, | |
50 | * and up to 4 + N parameters on 64-bit archs | |
51 | * (N = number of input arguments + output arguments). */ | |
52 | #define MAX_OPC_PARAM (4 + (MAX_OPC_PARAM_PER_ARG * MAX_OPC_PARAM_ARGS)) | |
00f6da6a | 53 | |
6e0b0730 PC |
54 | #define CPU_TEMP_BUF_NLONGS 128 |
55 | ||
78cd7b83 RH |
56 | /* Default target word size to pointer size. */ |
57 | #ifndef TCG_TARGET_REG_BITS | |
58 | # if UINTPTR_MAX == UINT32_MAX | |
59 | # define TCG_TARGET_REG_BITS 32 | |
60 | # elif UINTPTR_MAX == UINT64_MAX | |
61 | # define TCG_TARGET_REG_BITS 64 | |
62 | # else | |
63 | # error Unknown pointer size for tcg target | |
64 | # endif | |
817b838e SW |
65 | #endif |
66 | ||
c896fe29 FB |
67 | #if TCG_TARGET_REG_BITS == 32 |
68 | typedef int32_t tcg_target_long; | |
69 | typedef uint32_t tcg_target_ulong; | |
70 | #define TCG_PRIlx PRIx32 | |
71 | #define TCG_PRIld PRId32 | |
72 | #elif TCG_TARGET_REG_BITS == 64 | |
73 | typedef int64_t tcg_target_long; | |
74 | typedef uint64_t tcg_target_ulong; | |
75 | #define TCG_PRIlx PRIx64 | |
76 | #define TCG_PRIld PRId64 | |
77 | #else | |
78 | #error unsupported | |
79 | #endif | |
80 | ||
8d4e9146 FK |
81 | /* Oversized TCG guests make things like MTTCG hard |
82 | * as we can't use atomics for cputlb updates. | |
83 | */ | |
84 | #if TARGET_LONG_BITS > TCG_TARGET_REG_BITS | |
85 | #define TCG_OVERSIZED_GUEST 1 | |
86 | #else | |
87 | #define TCG_OVERSIZED_GUEST 0 | |
88 | #endif | |
89 | ||
c896fe29 FB |
90 | #if TCG_TARGET_NB_REGS <= 32 |
91 | typedef uint32_t TCGRegSet; | |
92 | #elif TCG_TARGET_NB_REGS <= 64 | |
93 | typedef uint64_t TCGRegSet; | |
94 | #else | |
95 | #error unsupported | |
96 | #endif | |
97 | ||
25c4d9cc | 98 | #if TCG_TARGET_REG_BITS == 32 |
e6a72734 | 99 | /* Turn some undef macros into false macros. */ |
609ad705 RH |
100 | #define TCG_TARGET_HAS_extrl_i64_i32 0 |
101 | #define TCG_TARGET_HAS_extrh_i64_i32 0 | |
25c4d9cc | 102 | #define TCG_TARGET_HAS_div_i64 0 |
ca675f46 | 103 | #define TCG_TARGET_HAS_rem_i64 0 |
25c4d9cc RH |
104 | #define TCG_TARGET_HAS_div2_i64 0 |
105 | #define TCG_TARGET_HAS_rot_i64 0 | |
106 | #define TCG_TARGET_HAS_ext8s_i64 0 | |
107 | #define TCG_TARGET_HAS_ext16s_i64 0 | |
108 | #define TCG_TARGET_HAS_ext32s_i64 0 | |
109 | #define TCG_TARGET_HAS_ext8u_i64 0 | |
110 | #define TCG_TARGET_HAS_ext16u_i64 0 | |
111 | #define TCG_TARGET_HAS_ext32u_i64 0 | |
112 | #define TCG_TARGET_HAS_bswap16_i64 0 | |
113 | #define TCG_TARGET_HAS_bswap32_i64 0 | |
114 | #define TCG_TARGET_HAS_bswap64_i64 0 | |
115 | #define TCG_TARGET_HAS_neg_i64 0 | |
116 | #define TCG_TARGET_HAS_not_i64 0 | |
117 | #define TCG_TARGET_HAS_andc_i64 0 | |
118 | #define TCG_TARGET_HAS_orc_i64 0 | |
119 | #define TCG_TARGET_HAS_eqv_i64 0 | |
120 | #define TCG_TARGET_HAS_nand_i64 0 | |
121 | #define TCG_TARGET_HAS_nor_i64 0 | |
0e28d006 RH |
122 | #define TCG_TARGET_HAS_clz_i64 0 |
123 | #define TCG_TARGET_HAS_ctz_i64 0 | |
a768e4e9 | 124 | #define TCG_TARGET_HAS_ctpop_i64 0 |
25c4d9cc | 125 | #define TCG_TARGET_HAS_deposit_i64 0 |
7ec8bab3 RH |
126 | #define TCG_TARGET_HAS_extract_i64 0 |
127 | #define TCG_TARGET_HAS_sextract_i64 0 | |
fce1296f | 128 | #define TCG_TARGET_HAS_extract2_i64 0 |
ffc5ea09 | 129 | #define TCG_TARGET_HAS_movcond_i64 0 |
d7156f7c RH |
130 | #define TCG_TARGET_HAS_add2_i64 0 |
131 | #define TCG_TARGET_HAS_sub2_i64 0 | |
132 | #define TCG_TARGET_HAS_mulu2_i64 0 | |
4d3203fd | 133 | #define TCG_TARGET_HAS_muls2_i64 0 |
03271524 RH |
134 | #define TCG_TARGET_HAS_muluh_i64 0 |
135 | #define TCG_TARGET_HAS_mulsh_i64 0 | |
e6a72734 RH |
136 | /* Turn some undef macros into true macros. */ |
137 | #define TCG_TARGET_HAS_add2_i32 1 | |
138 | #define TCG_TARGET_HAS_sub2_i32 1 | |
25c4d9cc RH |
139 | #endif |
140 | ||
a4773324 JK |
141 | #ifndef TCG_TARGET_deposit_i32_valid |
142 | #define TCG_TARGET_deposit_i32_valid(ofs, len) 1 | |
143 | #endif | |
144 | #ifndef TCG_TARGET_deposit_i64_valid | |
145 | #define TCG_TARGET_deposit_i64_valid(ofs, len) 1 | |
146 | #endif | |
7ec8bab3 RH |
147 | #ifndef TCG_TARGET_extract_i32_valid |
148 | #define TCG_TARGET_extract_i32_valid(ofs, len) 1 | |
149 | #endif | |
150 | #ifndef TCG_TARGET_extract_i64_valid | |
151 | #define TCG_TARGET_extract_i64_valid(ofs, len) 1 | |
152 | #endif | |
a4773324 | 153 | |
25c4d9cc RH |
154 | /* Only one of DIV or DIV2 should be defined. */ |
155 | #if defined(TCG_TARGET_HAS_div_i32) | |
156 | #define TCG_TARGET_HAS_div2_i32 0 | |
157 | #elif defined(TCG_TARGET_HAS_div2_i32) | |
158 | #define TCG_TARGET_HAS_div_i32 0 | |
ca675f46 | 159 | #define TCG_TARGET_HAS_rem_i32 0 |
25c4d9cc RH |
160 | #endif |
161 | #if defined(TCG_TARGET_HAS_div_i64) | |
162 | #define TCG_TARGET_HAS_div2_i64 0 | |
163 | #elif defined(TCG_TARGET_HAS_div2_i64) | |
164 | #define TCG_TARGET_HAS_div_i64 0 | |
ca675f46 | 165 | #define TCG_TARGET_HAS_rem_i64 0 |
25c4d9cc RH |
166 | #endif |
167 | ||
df9ebea5 RH |
168 | /* For 32-bit targets, some sort of unsigned widening multiply is required. */ |
169 | #if TCG_TARGET_REG_BITS == 32 \ | |
170 | && !(defined(TCG_TARGET_HAS_mulu2_i32) \ | |
171 | || defined(TCG_TARGET_HAS_muluh_i32)) | |
172 | # error "Missing unsigned widening multiply" | |
173 | #endif | |
174 | ||
d2fd745f RH |
175 | #if !defined(TCG_TARGET_HAS_v64) \ |
176 | && !defined(TCG_TARGET_HAS_v128) \ | |
177 | && !defined(TCG_TARGET_HAS_v256) | |
178 | #define TCG_TARGET_MAYBE_vec 0 | |
bcefc902 | 179 | #define TCG_TARGET_HAS_abs_vec 0 |
d2fd745f RH |
180 | #define TCG_TARGET_HAS_neg_vec 0 |
181 | #define TCG_TARGET_HAS_not_vec 0 | |
182 | #define TCG_TARGET_HAS_andc_vec 0 | |
183 | #define TCG_TARGET_HAS_orc_vec 0 | |
b0f7e744 | 184 | #define TCG_TARGET_HAS_roti_vec 0 |
23850a74 | 185 | #define TCG_TARGET_HAS_rots_vec 0 |
5d0ceda9 | 186 | #define TCG_TARGET_HAS_rotv_vec 0 |
d0ec9796 RH |
187 | #define TCG_TARGET_HAS_shi_vec 0 |
188 | #define TCG_TARGET_HAS_shs_vec 0 | |
189 | #define TCG_TARGET_HAS_shv_vec 0 | |
3774030a | 190 | #define TCG_TARGET_HAS_mul_vec 0 |
8afaf050 | 191 | #define TCG_TARGET_HAS_sat_vec 0 |
dd0a0fcd | 192 | #define TCG_TARGET_HAS_minmax_vec 0 |
38dc1294 | 193 | #define TCG_TARGET_HAS_bitsel_vec 0 |
f75da298 | 194 | #define TCG_TARGET_HAS_cmpsel_vec 0 |
d2fd745f RH |
195 | #else |
196 | #define TCG_TARGET_MAYBE_vec 1 | |
197 | #endif | |
198 | #ifndef TCG_TARGET_HAS_v64 | |
199 | #define TCG_TARGET_HAS_v64 0 | |
200 | #endif | |
201 | #ifndef TCG_TARGET_HAS_v128 | |
202 | #define TCG_TARGET_HAS_v128 0 | |
203 | #endif | |
204 | #ifndef TCG_TARGET_HAS_v256 | |
205 | #define TCG_TARGET_HAS_v256 0 | |
206 | #endif | |
207 | ||
9aef40ed RH |
208 | #ifndef TARGET_INSN_START_EXTRA_WORDS |
209 | # define TARGET_INSN_START_WORDS 1 | |
210 | #else | |
211 | # define TARGET_INSN_START_WORDS (1 + TARGET_INSN_START_EXTRA_WORDS) | |
212 | #endif | |
213 | ||
a9751609 | 214 | typedef enum TCGOpcode { |
c61aaf7a | 215 | #define DEF(name, oargs, iargs, cargs, flags) INDEX_op_ ## name, |
dcb32f1d | 216 | #include "tcg/tcg-opc.h" |
c896fe29 FB |
217 | #undef DEF |
218 | NB_OPS, | |
a9751609 | 219 | } TCGOpcode; |
c896fe29 | 220 | |
80a8b9a9 RH |
221 | #define tcg_regset_set_reg(d, r) ((d) |= (TCGRegSet)1 << (r)) |
222 | #define tcg_regset_reset_reg(d, r) ((d) &= ~((TCGRegSet)1 << (r))) | |
223 | #define tcg_regset_test_reg(d, r) (((d) >> (r)) & 1) | |
c896fe29 | 224 | |
1813e175 | 225 | #ifndef TCG_TARGET_INSN_UNIT_SIZE |
5053361b RH |
226 | # error "Missing TCG_TARGET_INSN_UNIT_SIZE" |
227 | #elif TCG_TARGET_INSN_UNIT_SIZE == 1 | |
1813e175 RH |
228 | typedef uint8_t tcg_insn_unit; |
229 | #elif TCG_TARGET_INSN_UNIT_SIZE == 2 | |
230 | typedef uint16_t tcg_insn_unit; | |
231 | #elif TCG_TARGET_INSN_UNIT_SIZE == 4 | |
232 | typedef uint32_t tcg_insn_unit; | |
233 | #elif TCG_TARGET_INSN_UNIT_SIZE == 8 | |
234 | typedef uint64_t tcg_insn_unit; | |
235 | #else | |
236 | /* The port better have done this. */ | |
237 | #endif | |
238 | ||
239 | ||
8bff06a0 | 240 | #if defined CONFIG_DEBUG_TCG || defined QEMU_STATIC_ANALYSIS |
1f00b27f | 241 | # define tcg_debug_assert(X) do { assert(X); } while (0) |
6fa2cef2 | 242 | #else |
1f00b27f SS |
243 | # define tcg_debug_assert(X) \ |
244 | do { if (!(X)) { __builtin_unreachable(); } } while (0) | |
1f00b27f SS |
245 | #endif |
246 | ||
7ecd02a0 RH |
247 | typedef struct TCGRelocation TCGRelocation; |
248 | struct TCGRelocation { | |
249 | QSIMPLEQ_ENTRY(TCGRelocation) next; | |
1813e175 | 250 | tcg_insn_unit *ptr; |
2ba7fae2 | 251 | intptr_t addend; |
7ecd02a0 RH |
252 | int type; |
253 | }; | |
c896fe29 | 254 | |
bef16ab4 RH |
255 | typedef struct TCGLabel TCGLabel; |
256 | struct TCGLabel { | |
257 | unsigned present : 1; | |
51e3972c | 258 | unsigned has_value : 1; |
bef16ab4 | 259 | unsigned id : 14; |
d88a117e | 260 | unsigned refs : 16; |
c896fe29 | 261 | union { |
2ba7fae2 | 262 | uintptr_t value; |
ffd0e507 | 263 | const tcg_insn_unit *value_ptr; |
c896fe29 | 264 | } u; |
7ecd02a0 | 265 | QSIMPLEQ_HEAD(, TCGRelocation) relocs; |
bef16ab4 | 266 | QSIMPLEQ_ENTRY(TCGLabel) next; |
bef16ab4 | 267 | }; |
c896fe29 FB |
268 | |
269 | typedef struct TCGPool { | |
270 | struct TCGPool *next; | |
c44f945a | 271 | int size; |
f7795e40 | 272 | uint8_t data[] __attribute__ ((aligned)); |
c896fe29 FB |
273 | } TCGPool; |
274 | ||
275 | #define TCG_POOL_CHUNK_SIZE 32768 | |
276 | ||
c4071c90 | 277 | #define TCG_MAX_TEMPS 512 |
190ce7fb | 278 | #define TCG_MAX_INSNS 512 |
c896fe29 | 279 | |
b03cce8e FB |
280 | /* when the size of the arguments of a called function is smaller than |
281 | this value, they are statically allocated in the TB stack frame */ | |
282 | #define TCG_STATIC_CALL_ARGS_SIZE 128 | |
283 | ||
c02244a5 RH |
284 | typedef enum TCGType { |
285 | TCG_TYPE_I32, | |
286 | TCG_TYPE_I64, | |
d2fd745f RH |
287 | |
288 | TCG_TYPE_V64, | |
289 | TCG_TYPE_V128, | |
290 | TCG_TYPE_V256, | |
291 | ||
c02244a5 | 292 | TCG_TYPE_COUNT, /* number of different types */ |
c896fe29 | 293 | |
3b6dac34 | 294 | /* An alias for the size of the host register. */ |
c896fe29 | 295 | #if TCG_TARGET_REG_BITS == 32 |
3b6dac34 | 296 | TCG_TYPE_REG = TCG_TYPE_I32, |
c02244a5 | 297 | #else |
3b6dac34 | 298 | TCG_TYPE_REG = TCG_TYPE_I64, |
c02244a5 | 299 | #endif |
3b6dac34 | 300 | |
d289837e RH |
301 | /* An alias for the size of the native pointer. */ |
302 | #if UINTPTR_MAX == UINT32_MAX | |
303 | TCG_TYPE_PTR = TCG_TYPE_I32, | |
304 | #else | |
305 | TCG_TYPE_PTR = TCG_TYPE_I64, | |
306 | #endif | |
3b6dac34 RH |
307 | |
308 | /* An alias for the size of the target "long", aka register. */ | |
c02244a5 RH |
309 | #if TARGET_LONG_BITS == 64 |
310 | TCG_TYPE_TL = TCG_TYPE_I64, | |
c896fe29 | 311 | #else |
c02244a5 | 312 | TCG_TYPE_TL = TCG_TYPE_I32, |
c896fe29 | 313 | #endif |
c02244a5 | 314 | } TCGType; |
c896fe29 | 315 | |
1f00b27f SS |
316 | /** |
317 | * get_alignment_bits | |
14776ab5 | 318 | * @memop: MemOp value |
1f00b27f SS |
319 | * |
320 | * Extract the alignment size from the memop. | |
1f00b27f | 321 | */ |
14776ab5 | 322 | static inline unsigned get_alignment_bits(MemOp memop) |
1f00b27f | 323 | { |
85aa8081 | 324 | unsigned a = memop & MO_AMASK; |
1f00b27f SS |
325 | |
326 | if (a == MO_UNALN) { | |
85aa8081 RH |
327 | /* No alignment required. */ |
328 | a = 0; | |
1f00b27f | 329 | } else if (a == MO_ALIGN) { |
85aa8081 RH |
330 | /* A natural alignment requirement. */ |
331 | a = memop & MO_SIZE; | |
1f00b27f | 332 | } else { |
85aa8081 RH |
333 | /* A specific alignment requirement. */ |
334 | a = a >> MO_ASHIFT; | |
1f00b27f SS |
335 | } |
336 | #if defined(CONFIG_SOFTMMU) | |
337 | /* The requested alignment cannot overlap the TLB flags. */ | |
85aa8081 | 338 | tcg_debug_assert((TLB_FLAGS_MASK & ((1 << a) - 1)) == 0); |
1f00b27f | 339 | #endif |
85aa8081 | 340 | return a; |
1f00b27f SS |
341 | } |
342 | ||
c896fe29 FB |
343 | typedef tcg_target_ulong TCGArg; |
344 | ||
a40d4701 PM |
345 | /* Define type and accessor macros for TCG variables. |
346 | ||
347 | TCG variables are the inputs and outputs of TCG ops, as described | |
348 | in tcg/README. Target CPU front-end code uses these types to deal | |
349 | with TCG variables as it emits TCG code via the tcg_gen_* functions. | |
350 | They come in several flavours: | |
351 | * TCGv_i32 : 32 bit integer type | |
352 | * TCGv_i64 : 64 bit integer type | |
353 | * TCGv_ptr : a host pointer type | |
d2fd745f RH |
354 | * TCGv_vec : a host vector type; the exact size is not exposed |
355 | to the CPU front-end code. | |
a40d4701 PM |
356 | * TCGv : an integer type the same size as target_ulong |
357 | (an alias for either TCGv_i32 or TCGv_i64) | |
358 | The compiler's type checking will complain if you mix them | |
359 | up and pass the wrong sized TCGv to a function. | |
360 | ||
361 | Users of tcg_gen_* don't need to know about any of the internal | |
362 | details of these, and should treat them as opaque types. | |
363 | You won't be able to look inside them in a debugger either. | |
364 | ||
365 | Internal implementation details follow: | |
366 | ||
367 | Note that there is no definition of the structs TCGv_i32_d etc anywhere. | |
368 | This is deliberate, because the values we store in variables of type | |
369 | TCGv_i32 are not really pointers-to-structures. They're just small | |
370 | integers, but keeping them in pointer types like this means that the | |
371 | compiler will complain if you accidentally pass a TCGv_i32 to a | |
372 | function which takes a TCGv_i64, and so on. Only the internals of | |
dc41aa7d | 373 | TCG need to care about the actual contents of the types. */ |
ac56dd48 | 374 | |
b6c73a6d RH |
375 | typedef struct TCGv_i32_d *TCGv_i32; |
376 | typedef struct TCGv_i64_d *TCGv_i64; | |
377 | typedef struct TCGv_ptr_d *TCGv_ptr; | |
d2fd745f | 378 | typedef struct TCGv_vec_d *TCGv_vec; |
1bcea73e | 379 | typedef TCGv_ptr TCGv_env; |
5d4e1a10 LV |
380 | #if TARGET_LONG_BITS == 32 |
381 | #define TCGv TCGv_i32 | |
382 | #elif TARGET_LONG_BITS == 64 | |
383 | #define TCGv TCGv_i64 | |
384 | #else | |
385 | #error Unhandled TARGET_LONG_BITS value | |
386 | #endif | |
ac56dd48 | 387 | |
c896fe29 | 388 | /* call flags */ |
78505279 AJ |
389 | /* Helper does not read globals (either directly or through an exception). It |
390 | implies TCG_CALL_NO_WRITE_GLOBALS. */ | |
3b50352b | 391 | #define TCG_CALL_NO_READ_GLOBALS 0x0001 |
78505279 | 392 | /* Helper does not write globals */ |
3b50352b | 393 | #define TCG_CALL_NO_WRITE_GLOBALS 0x0002 |
78505279 | 394 | /* Helper can be safely suppressed if the return value is not used. */ |
3b50352b | 395 | #define TCG_CALL_NO_SIDE_EFFECTS 0x0004 |
15d74092 RH |
396 | /* Helper is QEMU_NORETURN. */ |
397 | #define TCG_CALL_NO_RETURN 0x0008 | |
78505279 AJ |
398 | |
399 | /* convenience version of most used call flags */ | |
400 | #define TCG_CALL_NO_RWG TCG_CALL_NO_READ_GLOBALS | |
401 | #define TCG_CALL_NO_WG TCG_CALL_NO_WRITE_GLOBALS | |
402 | #define TCG_CALL_NO_SE TCG_CALL_NO_SIDE_EFFECTS | |
403 | #define TCG_CALL_NO_RWG_SE (TCG_CALL_NO_RWG | TCG_CALL_NO_SE) | |
404 | #define TCG_CALL_NO_WG_SE (TCG_CALL_NO_WG | TCG_CALL_NO_SE) | |
405 | ||
e89b28a6 RH |
406 | /* Used to align parameters. See the comment before tcgv_i32_temp. */ |
407 | #define TCG_CALL_DUMMY_ARG ((TCGArg)0) | |
39cf05d3 | 408 | |
a93cf9df SW |
409 | /* Conditions. Note that these are laid out for easy manipulation by |
410 | the functions below: | |
0aed257f RH |
411 | bit 0 is used for inverting; |
412 | bit 1 is signed, | |
413 | bit 2 is unsigned, | |
414 | bit 3 is used with bit 0 for swapping signed/unsigned. */ | |
c896fe29 | 415 | typedef enum { |
0aed257f RH |
416 | /* non-signed */ |
417 | TCG_COND_NEVER = 0 | 0 | 0 | 0, | |
418 | TCG_COND_ALWAYS = 0 | 0 | 0 | 1, | |
419 | TCG_COND_EQ = 8 | 0 | 0 | 0, | |
420 | TCG_COND_NE = 8 | 0 | 0 | 1, | |
421 | /* signed */ | |
422 | TCG_COND_LT = 0 | 0 | 2 | 0, | |
423 | TCG_COND_GE = 0 | 0 | 2 | 1, | |
424 | TCG_COND_LE = 8 | 0 | 2 | 0, | |
425 | TCG_COND_GT = 8 | 0 | 2 | 1, | |
c896fe29 | 426 | /* unsigned */ |
0aed257f RH |
427 | TCG_COND_LTU = 0 | 4 | 0 | 0, |
428 | TCG_COND_GEU = 0 | 4 | 0 | 1, | |
429 | TCG_COND_LEU = 8 | 4 | 0 | 0, | |
430 | TCG_COND_GTU = 8 | 4 | 0 | 1, | |
c896fe29 FB |
431 | } TCGCond; |
432 | ||
1c086220 | 433 | /* Invert the sense of the comparison. */ |
401d466d RH |
434 | static inline TCGCond tcg_invert_cond(TCGCond c) |
435 | { | |
436 | return (TCGCond)(c ^ 1); | |
437 | } | |
438 | ||
1c086220 RH |
439 | /* Swap the operands in a comparison. */ |
440 | static inline TCGCond tcg_swap_cond(TCGCond c) | |
441 | { | |
0aed257f | 442 | return c & 6 ? (TCGCond)(c ^ 9) : c; |
1c086220 RH |
443 | } |
444 | ||
d1e321b8 | 445 | /* Create an "unsigned" version of a "signed" comparison. */ |
ff44c2f3 RH |
446 | static inline TCGCond tcg_unsigned_cond(TCGCond c) |
447 | { | |
0aed257f | 448 | return c & 2 ? (TCGCond)(c ^ 6) : c; |
ff44c2f3 RH |
449 | } |
450 | ||
923ed175 RH |
451 | /* Create a "signed" version of an "unsigned" comparison. */ |
452 | static inline TCGCond tcg_signed_cond(TCGCond c) | |
453 | { | |
454 | return c & 4 ? (TCGCond)(c ^ 6) : c; | |
455 | } | |
456 | ||
d1e321b8 | 457 | /* Must a comparison be considered unsigned? */ |
bcc66562 RH |
458 | static inline bool is_unsigned_cond(TCGCond c) |
459 | { | |
0aed257f | 460 | return (c & 4) != 0; |
bcc66562 RH |
461 | } |
462 | ||
d1e321b8 RH |
463 | /* Create a "high" version of a double-word comparison. |
464 | This removes equality from a LTE or GTE comparison. */ | |
465 | static inline TCGCond tcg_high_cond(TCGCond c) | |
466 | { | |
467 | switch (c) { | |
468 | case TCG_COND_GE: | |
469 | case TCG_COND_LE: | |
470 | case TCG_COND_GEU: | |
471 | case TCG_COND_LEU: | |
472 | return (TCGCond)(c ^ 8); | |
473 | default: | |
474 | return c; | |
475 | } | |
476 | } | |
477 | ||
00c8fa9f EC |
478 | typedef enum TCGTempVal { |
479 | TEMP_VAL_DEAD, | |
480 | TEMP_VAL_REG, | |
481 | TEMP_VAL_MEM, | |
482 | TEMP_VAL_CONST, | |
483 | } TCGTempVal; | |
c896fe29 | 484 | |
ee17db83 RH |
485 | typedef enum TCGTempKind { |
486 | /* Temp is dead at the end of all basic blocks. */ | |
487 | TEMP_NORMAL, | |
488 | /* Temp is saved across basic blocks but dead at the end of TBs. */ | |
489 | TEMP_LOCAL, | |
490 | /* Temp is saved across both basic blocks and translation blocks. */ | |
491 | TEMP_GLOBAL, | |
492 | /* Temp is in a fixed register. */ | |
493 | TEMP_FIXED, | |
c0522136 RH |
494 | /* Temp is a fixed constant. */ |
495 | TEMP_CONST, | |
ee17db83 RH |
496 | } TCGTempKind; |
497 | ||
c896fe29 | 498 | typedef struct TCGTemp { |
b6638662 | 499 | TCGReg reg:8; |
00c8fa9f EC |
500 | TCGTempVal val_type:8; |
501 | TCGType base_type:8; | |
502 | TCGType type:8; | |
ee17db83 | 503 | TCGTempKind kind:3; |
b3915dbb RH |
504 | unsigned int indirect_reg:1; |
505 | unsigned int indirect_base:1; | |
c896fe29 FB |
506 | unsigned int mem_coherent:1; |
507 | unsigned int mem_allocated:1; | |
fa477d25 | 508 | unsigned int temp_allocated:1; |
00c8fa9f | 509 | |
bdb38b95 | 510 | int64_t val; |
b3a62939 | 511 | struct TCGTemp *mem_base; |
00c8fa9f | 512 | intptr_t mem_offset; |
c896fe29 | 513 | const char *name; |
b83eabea RH |
514 | |
515 | /* Pass-specific information that can be stored for a temporary. | |
516 | One word worth of integer data, and one pointer to data | |
517 | allocated separately. */ | |
518 | uintptr_t state; | |
519 | void *state_ptr; | |
c896fe29 FB |
520 | } TCGTemp; |
521 | ||
c896fe29 FB |
522 | typedef struct TCGContext TCGContext; |
523 | ||
0ec9eabc RH |
524 | typedef struct TCGTempSet { |
525 | unsigned long l[BITS_TO_LONGS(TCG_MAX_TEMPS)]; | |
526 | } TCGTempSet; | |
527 | ||
a1b3c48d RH |
528 | /* While we limit helpers to 6 arguments, for 32-bit hosts, with padding, |
529 | this imples a max of 6*2 (64-bit in) + 2 (64-bit out) = 14 operands. | |
530 | There are never more than 2 outputs, which means that we can store all | |
531 | dead + sync data within 16 bits. */ | |
532 | #define DEAD_ARG 4 | |
533 | #define SYNC_ARG 1 | |
534 | typedef uint16_t TCGLifeData; | |
535 | ||
75e8b9b7 RH |
536 | /* The layout here is designed to avoid a bitfield crossing of |
537 | a 32-bit boundary, which would cause GCC to add extra padding. */ | |
c45cb8bb | 538 | typedef struct TCGOp { |
bee158cb RH |
539 | TCGOpcode opc : 8; /* 8 */ |
540 | ||
cd9090aa RH |
541 | /* Parameters for this opcode. See below. */ |
542 | unsigned param1 : 4; /* 12 */ | |
543 | unsigned param2 : 4; /* 16 */ | |
c45cb8bb | 544 | |
bee158cb | 545 | /* Lifetime data of the operands. */ |
15fa08f8 RH |
546 | unsigned life : 16; /* 32 */ |
547 | ||
548 | /* Next and previous opcodes. */ | |
549 | QTAILQ_ENTRY(TCGOp) link; | |
38b47b19 EC |
550 | #ifdef CONFIG_PLUGIN |
551 | QSIMPLEQ_ENTRY(TCGOp) plugin_link; | |
552 | #endif | |
75e8b9b7 RH |
553 | |
554 | /* Arguments for the opcode. */ | |
555 | TCGArg args[MAX_OPC_PARAM]; | |
69e3706d RH |
556 | |
557 | /* Register preferences for the output(s). */ | |
558 | TCGRegSet output_pref[2]; | |
c45cb8bb RH |
559 | } TCGOp; |
560 | ||
cd9090aa RH |
561 | #define TCGOP_CALLI(X) (X)->param1 |
562 | #define TCGOP_CALLO(X) (X)->param2 | |
563 | ||
d2fd745f RH |
564 | #define TCGOP_VECL(X) (X)->param1 |
565 | #define TCGOP_VECE(X) (X)->param2 | |
566 | ||
dcb8e758 RH |
567 | /* Make sure operands fit in the bitfields above. */ |
568 | QEMU_BUILD_BUG_ON(NB_OPS > (1 << 8)); | |
c45cb8bb | 569 | |
c3fac113 | 570 | typedef struct TCGProfile { |
72fd2efb | 571 | int64_t cpu_exec_time; |
c3fac113 EC |
572 | int64_t tb_count1; |
573 | int64_t tb_count; | |
574 | int64_t op_count; /* total insn count */ | |
575 | int op_count_max; /* max insn per TB */ | |
c3fac113 | 576 | int temp_count_max; |
dd1d7da2 | 577 | int64_t temp_count; |
c3fac113 EC |
578 | int64_t del_op_count; |
579 | int64_t code_in_len; | |
580 | int64_t code_out_len; | |
581 | int64_t search_out_len; | |
582 | int64_t interm_time; | |
583 | int64_t code_time; | |
584 | int64_t la_time; | |
585 | int64_t opt_time; | |
586 | int64_t restore_count; | |
587 | int64_t restore_time; | |
588 | int64_t table_op_count[NB_OPS]; | |
589 | } TCGProfile; | |
590 | ||
c896fe29 FB |
591 | struct TCGContext { |
592 | uint8_t *pool_cur, *pool_end; | |
4055299e | 593 | TCGPool *pool_first, *pool_current, *pool_first_large; |
c896fe29 | 594 | int nb_labels; |
c896fe29 FB |
595 | int nb_globals; |
596 | int nb_temps; | |
5a18407f | 597 | int nb_indirects; |
abebf925 | 598 | int nb_ops; |
c896fe29 FB |
599 | |
600 | /* goto_tb support */ | |
1813e175 | 601 | tcg_insn_unit *code_buf; |
f309101c | 602 | uint16_t *tb_jmp_reset_offset; /* tb->jmp_reset_offset */ |
a8583393 RH |
603 | uintptr_t *tb_jmp_insn_offset; /* tb->jmp_target_arg if direct_jump */ |
604 | uintptr_t *tb_jmp_target_addr; /* tb->jmp_target_arg if !direct_jump */ | |
c896fe29 | 605 | |
c896fe29 | 606 | TCGRegSet reserved_regs; |
e82d5a24 | 607 | uint32_t tb_cflags; /* cflags of the current TB */ |
e2c6d1b4 RH |
608 | intptr_t current_frame_offset; |
609 | intptr_t frame_start; | |
610 | intptr_t frame_end; | |
b3a62939 | 611 | TCGTemp *frame_temp; |
c896fe29 | 612 | |
1813e175 | 613 | tcg_insn_unit *code_ptr; |
c896fe29 | 614 | |
a23a9ec6 | 615 | #ifdef CONFIG_PROFILER |
c3fac113 | 616 | TCGProfile prof; |
a23a9ec6 | 617 | #endif |
27bfd83c PM |
618 | |
619 | #ifdef CONFIG_DEBUG_TCG | |
620 | int temps_in_use; | |
0a209d4b | 621 | int goto_tb_issue_mask; |
53229a77 | 622 | const TCGOpcode *vecop_list; |
27bfd83c | 623 | #endif |
b76f0d8c | 624 | |
1813e175 RH |
625 | /* Code generation. Note that we specifically do not use tcg_insn_unit |
626 | here, because there's too much arithmetic throughout that relies | |
627 | on addition and subtraction working on bytes. Rely on the GCC | |
628 | extension that allows arithmetic on void*. */ | |
1813e175 | 629 | void *code_gen_buffer; |
0b0d3320 | 630 | size_t code_gen_buffer_size; |
1813e175 | 631 | void *code_gen_ptr; |
57a26946 | 632 | void *data_gen_ptr; |
0b0d3320 | 633 | |
b125f9dc RH |
634 | /* Threshold to flush the translated code buffer. */ |
635 | void *code_gen_highwater; | |
636 | ||
128ed227 EC |
637 | size_t tb_phys_invalidate_count; |
638 | ||
7c255043 LV |
639 | /* Track which vCPU triggers events */ |
640 | CPUState *cpu; /* *_trans */ | |
7c255043 | 641 | |
139c1837 | 642 | /* These structures are private to tcg-target.c.inc. */ |
659ef5cb | 643 | #ifdef TCG_TARGET_NEED_LDST_LABELS |
b58deb34 | 644 | QSIMPLEQ_HEAD(, TCGLabelQemuLdst) ldst_labels; |
659ef5cb | 645 | #endif |
57a26946 RH |
646 | #ifdef TCG_TARGET_NEED_POOL_LABELS |
647 | struct TCGLabelPoolData *pool_labels; | |
648 | #endif | |
c45cb8bb | 649 | |
26689780 EC |
650 | TCGLabel *exitreq_label; |
651 | ||
38b47b19 EC |
652 | #ifdef CONFIG_PLUGIN |
653 | /* | |
654 | * We keep one plugin_tb struct per TCGContext. Note that on every TB | |
655 | * translation we clear but do not free its contents; this way we | |
656 | * avoid a lot of malloc/free churn, since after a few TB's it's | |
657 | * unlikely that we'll need to allocate either more instructions or more | |
658 | * space for instructions (for variable-instruction-length ISAs). | |
659 | */ | |
660 | struct qemu_plugin_tb *plugin_tb; | |
661 | ||
662 | /* descriptor of the instruction being translated */ | |
663 | struct qemu_plugin_insn *plugin_insn; | |
664 | ||
665 | /* list to quickly access the injected ops */ | |
666 | QSIMPLEQ_HEAD(, TCGOp) plugin_ops; | |
667 | #endif | |
668 | ||
c0522136 | 669 | GHashTable *const_table[TCG_TYPE_COUNT]; |
c45cb8bb RH |
670 | TCGTempSet free_temps[TCG_TYPE_COUNT * 2]; |
671 | TCGTemp temps[TCG_MAX_TEMPS]; /* globals first, temps after */ | |
672 | ||
eae3eb3e | 673 | QTAILQ_HEAD(, TCGOp) ops, free_ops; |
7ecd02a0 | 674 | QSIMPLEQ_HEAD(, TCGLabel) labels; |
15fa08f8 | 675 | |
f8b2f202 RH |
676 | /* Tells which temporary holds a given register. |
677 | It does not take into account fixed registers */ | |
678 | TCGTemp *reg_to_temp[TCG_TARGET_NB_REGS]; | |
c45cb8bb | 679 | |
fca8a500 RH |
680 | uint16_t gen_insn_end_off[TCG_MAX_INSNS]; |
681 | target_ulong gen_insn_data[TCG_MAX_INSNS][TARGET_INSN_START_WORDS]; | |
ae30e866 RH |
682 | |
683 | /* Exit to translator on overflow. */ | |
684 | sigjmp_buf jmp_trans; | |
c896fe29 FB |
685 | }; |
686 | ||
e01fa97d RH |
687 | static inline bool temp_readonly(TCGTemp *ts) |
688 | { | |
c0522136 | 689 | return ts->kind >= TEMP_FIXED; |
e01fa97d RH |
690 | } |
691 | ||
b1311c4a | 692 | extern TCGContext tcg_init_ctx; |
3468b59e | 693 | extern __thread TCGContext *tcg_ctx; |
c8bc1168 | 694 | extern const void *tcg_code_gen_epilogue; |
db0c51a3 | 695 | extern uintptr_t tcg_splitwx_diff; |
1c2adb95 | 696 | extern TCGv_env cpu_env; |
c896fe29 | 697 | |
4846cd37 RH |
698 | static inline bool in_code_gen_buffer(const void *p) |
699 | { | |
700 | const TCGContext *s = &tcg_init_ctx; | |
701 | /* | |
702 | * Much like it is valid to have a pointer to the byte past the | |
703 | * end of an array (so long as you don't dereference it), allow | |
704 | * a pointer to the byte past the end of the code gen buffer. | |
705 | */ | |
706 | return (size_t)(p - s->code_gen_buffer) <= s->code_gen_buffer_size; | |
707 | } | |
708 | ||
db0c51a3 RH |
709 | #ifdef CONFIG_DEBUG_TCG |
710 | const void *tcg_splitwx_to_rx(void *rw); | |
711 | void *tcg_splitwx_to_rw(const void *rx); | |
712 | #else | |
713 | static inline const void *tcg_splitwx_to_rx(void *rw) | |
714 | { | |
715 | return rw ? rw + tcg_splitwx_diff : NULL; | |
716 | } | |
717 | ||
718 | static inline void *tcg_splitwx_to_rw(const void *rx) | |
719 | { | |
720 | return rx ? (void *)rx - tcg_splitwx_diff : NULL; | |
721 | } | |
722 | #endif | |
723 | ||
1807f4c4 RH |
724 | static inline size_t temp_idx(TCGTemp *ts) |
725 | { | |
b1311c4a EC |
726 | ptrdiff_t n = ts - tcg_ctx->temps; |
727 | tcg_debug_assert(n >= 0 && n < tcg_ctx->nb_temps); | |
1807f4c4 RH |
728 | return n; |
729 | } | |
730 | ||
731 | static inline TCGArg temp_arg(TCGTemp *ts) | |
732 | { | |
e89b28a6 | 733 | return (uintptr_t)ts; |
1807f4c4 RH |
734 | } |
735 | ||
43439139 RH |
736 | static inline TCGTemp *arg_temp(TCGArg a) |
737 | { | |
e89b28a6 | 738 | return (TCGTemp *)(uintptr_t)a; |
43439139 RH |
739 | } |
740 | ||
e89b28a6 RH |
741 | /* Using the offset of a temporary, relative to TCGContext, rather than |
742 | its index means that we don't use 0. That leaves offset 0 free for | |
743 | a NULL representation without having to leave index 0 unused. */ | |
744 | static inline TCGTemp *tcgv_i32_temp(TCGv_i32 v) | |
6349039d | 745 | { |
e89b28a6 | 746 | uintptr_t o = (uintptr_t)v; |
b1311c4a | 747 | TCGTemp *t = (void *)tcg_ctx + o; |
e89b28a6 RH |
748 | tcg_debug_assert(offsetof(TCGContext, temps[temp_idx(t)]) == o); |
749 | return t; | |
ae8b75dc RH |
750 | } |
751 | ||
e89b28a6 | 752 | static inline TCGTemp *tcgv_i64_temp(TCGv_i64 v) |
ae8b75dc | 753 | { |
e89b28a6 | 754 | return tcgv_i32_temp((TCGv_i32)v); |
ae8b75dc RH |
755 | } |
756 | ||
e89b28a6 | 757 | static inline TCGTemp *tcgv_ptr_temp(TCGv_ptr v) |
ae8b75dc | 758 | { |
e89b28a6 | 759 | return tcgv_i32_temp((TCGv_i32)v); |
ae8b75dc RH |
760 | } |
761 | ||
d2fd745f RH |
762 | static inline TCGTemp *tcgv_vec_temp(TCGv_vec v) |
763 | { | |
764 | return tcgv_i32_temp((TCGv_i32)v); | |
765 | } | |
766 | ||
e89b28a6 | 767 | static inline TCGArg tcgv_i32_arg(TCGv_i32 v) |
ae8b75dc | 768 | { |
e89b28a6 | 769 | return temp_arg(tcgv_i32_temp(v)); |
ae8b75dc RH |
770 | } |
771 | ||
e89b28a6 | 772 | static inline TCGArg tcgv_i64_arg(TCGv_i64 v) |
ae8b75dc | 773 | { |
e89b28a6 | 774 | return temp_arg(tcgv_i64_temp(v)); |
ae8b75dc RH |
775 | } |
776 | ||
e89b28a6 | 777 | static inline TCGArg tcgv_ptr_arg(TCGv_ptr v) |
ae8b75dc | 778 | { |
e89b28a6 | 779 | return temp_arg(tcgv_ptr_temp(v)); |
ae8b75dc RH |
780 | } |
781 | ||
d2fd745f RH |
782 | static inline TCGArg tcgv_vec_arg(TCGv_vec v) |
783 | { | |
784 | return temp_arg(tcgv_vec_temp(v)); | |
785 | } | |
786 | ||
085272b3 RH |
787 | static inline TCGv_i32 temp_tcgv_i32(TCGTemp *t) |
788 | { | |
e89b28a6 | 789 | (void)temp_idx(t); /* trigger embedded assert */ |
b1311c4a | 790 | return (TCGv_i32)((void *)t - (void *)tcg_ctx); |
085272b3 RH |
791 | } |
792 | ||
793 | static inline TCGv_i64 temp_tcgv_i64(TCGTemp *t) | |
794 | { | |
e89b28a6 | 795 | return (TCGv_i64)temp_tcgv_i32(t); |
085272b3 RH |
796 | } |
797 | ||
798 | static inline TCGv_ptr temp_tcgv_ptr(TCGTemp *t) | |
799 | { | |
e89b28a6 | 800 | return (TCGv_ptr)temp_tcgv_i32(t); |
085272b3 RH |
801 | } |
802 | ||
d2fd745f RH |
803 | static inline TCGv_vec temp_tcgv_vec(TCGTemp *t) |
804 | { | |
805 | return (TCGv_vec)temp_tcgv_i32(t); | |
806 | } | |
807 | ||
dc41aa7d RH |
808 | #if TCG_TARGET_REG_BITS == 32 |
809 | static inline TCGv_i32 TCGV_LOW(TCGv_i64 t) | |
810 | { | |
811 | return temp_tcgv_i32(tcgv_i64_temp(t)); | |
812 | } | |
813 | ||
814 | static inline TCGv_i32 TCGV_HIGH(TCGv_i64 t) | |
815 | { | |
816 | return temp_tcgv_i32(tcgv_i64_temp(t) + 1); | |
817 | } | |
818 | #endif | |
819 | ||
2271a6ac RH |
820 | static inline TCGArg tcg_get_insn_param(TCGOp *op, int arg) |
821 | { | |
822 | return op->args[arg]; | |
823 | } | |
824 | ||
15fa08f8 | 825 | static inline void tcg_set_insn_param(TCGOp *op, int arg, TCGArg v) |
1d41478f | 826 | { |
15fa08f8 | 827 | op->args[arg] = v; |
1d41478f EI |
828 | } |
829 | ||
2271a6ac RH |
830 | static inline target_ulong tcg_get_insn_start_param(TCGOp *op, int arg) |
831 | { | |
832 | #if TARGET_LONG_BITS <= TCG_TARGET_REG_BITS | |
833 | return tcg_get_insn_param(op, arg); | |
834 | #else | |
835 | return tcg_get_insn_param(op, arg * 2) | | |
836 | ((uint64_t)tcg_get_insn_param(op, arg * 2 + 1) << 32); | |
837 | #endif | |
838 | } | |
839 | ||
9743cd57 RH |
840 | static inline void tcg_set_insn_start_param(TCGOp *op, int arg, target_ulong v) |
841 | { | |
842 | #if TARGET_LONG_BITS <= TCG_TARGET_REG_BITS | |
843 | tcg_set_insn_param(op, arg, v); | |
844 | #else | |
845 | tcg_set_insn_param(op, arg * 2, v); | |
846 | tcg_set_insn_param(op, arg * 2 + 1, v >> 32); | |
847 | #endif | |
848 | } | |
849 | ||
15fa08f8 RH |
850 | /* The last op that was emitted. */ |
851 | static inline TCGOp *tcg_last_op(void) | |
fe700adb | 852 | { |
eae3eb3e | 853 | return QTAILQ_LAST(&tcg_ctx->ops); |
fe700adb RH |
854 | } |
855 | ||
856 | /* Test for whether to terminate the TB for using too many opcodes. */ | |
857 | static inline bool tcg_op_buf_full(void) | |
858 | { | |
abebf925 RH |
859 | /* This is not a hard limit, it merely stops translation when |
860 | * we have produced "enough" opcodes. We want to limit TB size | |
861 | * such that a RISC host can reasonably use a 16-bit signed | |
9f754620 RH |
862 | * branch within the TB. We also need to be mindful of the |
863 | * 16-bit unsigned offsets, TranslationBlock.jmp_reset_offset[] | |
864 | * and TCGContext.gen_insn_end_off[]. | |
abebf925 | 865 | */ |
9f754620 | 866 | return tcg_ctx->nb_ops >= 4000; |
fe700adb RH |
867 | } |
868 | ||
c896fe29 FB |
869 | /* pool based memory allocation */ |
870 | ||
0ac20318 | 871 | /* user-mode: mmap_lock must be held for tcg_malloc_internal. */ |
c896fe29 FB |
872 | void *tcg_malloc_internal(TCGContext *s, int size); |
873 | void tcg_pool_reset(TCGContext *s); | |
6e3b2bfd | 874 | TranslationBlock *tcg_tb_alloc(TCGContext *s); |
c896fe29 | 875 | |
938e897a | 876 | void tb_destroy(TranslationBlock *tb); |
e8feb96f EC |
877 | void tcg_region_reset_all(void); |
878 | ||
879 | size_t tcg_code_size(void); | |
880 | size_t tcg_code_capacity(void); | |
881 | ||
be2cdc5e EC |
882 | void tcg_tb_insert(TranslationBlock *tb); |
883 | void tcg_tb_remove(TranslationBlock *tb); | |
128ed227 | 884 | size_t tcg_tb_phys_invalidate_count(void); |
be2cdc5e EC |
885 | TranslationBlock *tcg_tb_lookup(uintptr_t tc_ptr); |
886 | void tcg_tb_foreach(GTraverseFunc func, gpointer user_data); | |
887 | size_t tcg_nb_tbs(void); | |
888 | ||
0ac20318 | 889 | /* user-mode: Called with mmap_lock held. */ |
c896fe29 FB |
890 | static inline void *tcg_malloc(int size) |
891 | { | |
b1311c4a | 892 | TCGContext *s = tcg_ctx; |
c896fe29 | 893 | uint8_t *ptr, *ptr_end; |
13aaef67 RH |
894 | |
895 | /* ??? This is a weak placeholder for minimum malloc alignment. */ | |
896 | size = QEMU_ALIGN_UP(size, 8); | |
897 | ||
c896fe29 FB |
898 | ptr = s->pool_cur; |
899 | ptr_end = ptr + size; | |
900 | if (unlikely(ptr_end > s->pool_end)) { | |
b1311c4a | 901 | return tcg_malloc_internal(tcg_ctx, size); |
c896fe29 FB |
902 | } else { |
903 | s->pool_cur = ptr_end; | |
904 | return ptr; | |
905 | } | |
906 | } | |
907 | ||
a76aabd3 | 908 | void tcg_init(size_t tb_size, int splitwx); |
3468b59e | 909 | void tcg_register_thread(void); |
9002ec79 | 910 | void tcg_prologue_init(TCGContext *s); |
c896fe29 FB |
911 | void tcg_func_start(TCGContext *s); |
912 | ||
5bd2ec3d | 913 | int tcg_gen_code(TCGContext *s, TranslationBlock *tb); |
c896fe29 | 914 | |
b6638662 | 915 | void tcg_set_frame(TCGContext *s, TCGReg reg, intptr_t start, intptr_t size); |
a7812ae4 | 916 | |
085272b3 RH |
917 | TCGTemp *tcg_global_mem_new_internal(TCGType, TCGv_ptr, |
918 | intptr_t, const char *); | |
5bfa8034 RH |
919 | TCGTemp *tcg_temp_new_internal(TCGType, bool); |
920 | void tcg_temp_free_internal(TCGTemp *); | |
d2fd745f RH |
921 | TCGv_vec tcg_temp_new_vec(TCGType type); |
922 | TCGv_vec tcg_temp_new_vec_matching(TCGv_vec match); | |
e1ccc054 | 923 | |
5bfa8034 RH |
924 | static inline void tcg_temp_free_i32(TCGv_i32 arg) |
925 | { | |
926 | tcg_temp_free_internal(tcgv_i32_temp(arg)); | |
927 | } | |
928 | ||
929 | static inline void tcg_temp_free_i64(TCGv_i64 arg) | |
930 | { | |
931 | tcg_temp_free_internal(tcgv_i64_temp(arg)); | |
932 | } | |
933 | ||
934 | static inline void tcg_temp_free_ptr(TCGv_ptr arg) | |
935 | { | |
936 | tcg_temp_free_internal(tcgv_ptr_temp(arg)); | |
937 | } | |
938 | ||
939 | static inline void tcg_temp_free_vec(TCGv_vec arg) | |
940 | { | |
941 | tcg_temp_free_internal(tcgv_vec_temp(arg)); | |
942 | } | |
e1ccc054 | 943 | |
e1ccc054 RH |
944 | static inline TCGv_i32 tcg_global_mem_new_i32(TCGv_ptr reg, intptr_t offset, |
945 | const char *name) | |
946 | { | |
085272b3 RH |
947 | TCGTemp *t = tcg_global_mem_new_internal(TCG_TYPE_I32, reg, offset, name); |
948 | return temp_tcgv_i32(t); | |
e1ccc054 RH |
949 | } |
950 | ||
a7812ae4 PB |
951 | static inline TCGv_i32 tcg_temp_new_i32(void) |
952 | { | |
5bfa8034 RH |
953 | TCGTemp *t = tcg_temp_new_internal(TCG_TYPE_I32, false); |
954 | return temp_tcgv_i32(t); | |
a7812ae4 | 955 | } |
e1ccc054 | 956 | |
a7812ae4 PB |
957 | static inline TCGv_i32 tcg_temp_local_new_i32(void) |
958 | { | |
5bfa8034 RH |
959 | TCGTemp *t = tcg_temp_new_internal(TCG_TYPE_I32, true); |
960 | return temp_tcgv_i32(t); | |
a7812ae4 | 961 | } |
a7812ae4 | 962 | |
e1ccc054 RH |
963 | static inline TCGv_i64 tcg_global_mem_new_i64(TCGv_ptr reg, intptr_t offset, |
964 | const char *name) | |
965 | { | |
085272b3 RH |
966 | TCGTemp *t = tcg_global_mem_new_internal(TCG_TYPE_I64, reg, offset, name); |
967 | return temp_tcgv_i64(t); | |
e1ccc054 RH |
968 | } |
969 | ||
a7812ae4 | 970 | static inline TCGv_i64 tcg_temp_new_i64(void) |
641d5fbe | 971 | { |
5bfa8034 RH |
972 | TCGTemp *t = tcg_temp_new_internal(TCG_TYPE_I64, false); |
973 | return temp_tcgv_i64(t); | |
641d5fbe | 974 | } |
e1ccc054 | 975 | |
a7812ae4 | 976 | static inline TCGv_i64 tcg_temp_local_new_i64(void) |
641d5fbe | 977 | { |
5bfa8034 RH |
978 | TCGTemp *t = tcg_temp_new_internal(TCG_TYPE_I64, true); |
979 | return temp_tcgv_i64(t); | |
980 | } | |
981 | ||
982 | static inline TCGv_ptr tcg_global_mem_new_ptr(TCGv_ptr reg, intptr_t offset, | |
983 | const char *name) | |
984 | { | |
985 | TCGTemp *t = tcg_global_mem_new_internal(TCG_TYPE_PTR, reg, offset, name); | |
986 | return temp_tcgv_ptr(t); | |
987 | } | |
988 | ||
989 | static inline TCGv_ptr tcg_temp_new_ptr(void) | |
990 | { | |
991 | TCGTemp *t = tcg_temp_new_internal(TCG_TYPE_PTR, false); | |
992 | return temp_tcgv_ptr(t); | |
993 | } | |
994 | ||
995 | static inline TCGv_ptr tcg_temp_local_new_ptr(void) | |
996 | { | |
997 | TCGTemp *t = tcg_temp_new_internal(TCG_TYPE_PTR, true); | |
998 | return temp_tcgv_ptr(t); | |
641d5fbe | 999 | } |
a7812ae4 | 1000 | |
27bfd83c PM |
1001 | #if defined(CONFIG_DEBUG_TCG) |
1002 | /* If you call tcg_clear_temp_count() at the start of a section of | |
1003 | * code which is not supposed to leak any TCG temporaries, then | |
1004 | * calling tcg_check_temp_count() at the end of the section will | |
1005 | * return 1 if the section did in fact leak a temporary. | |
1006 | */ | |
1007 | void tcg_clear_temp_count(void); | |
1008 | int tcg_check_temp_count(void); | |
1009 | #else | |
1010 | #define tcg_clear_temp_count() do { } while (0) | |
1011 | #define tcg_check_temp_count() 0 | |
1012 | #endif | |
1013 | ||
72fd2efb | 1014 | int64_t tcg_cpu_exec_time(void); |
3de2faa9 | 1015 | void tcg_dump_info(void); |
d4c51a0a | 1016 | void tcg_dump_op_count(void); |
c896fe29 | 1017 | |
bc2b17e6 | 1018 | #define TCG_CT_CONST 1 /* any constant of register size */ |
c896fe29 FB |
1019 | |
1020 | typedef struct TCGArgConstraint { | |
bc2b17e6 RH |
1021 | unsigned ct : 16; |
1022 | unsigned alias_index : 4; | |
1023 | unsigned sort_index : 4; | |
1024 | bool oalias : 1; | |
1025 | bool ialias : 1; | |
1026 | bool newreg : 1; | |
9be0d080 | 1027 | TCGRegSet regs; |
c896fe29 FB |
1028 | } TCGArgConstraint; |
1029 | ||
1030 | #define TCG_MAX_OP_ARGS 16 | |
1031 | ||
b4cb76e6 | 1032 | /* Bits for TCGOpDef->flags, 8 bits available, all used. */ |
8399ad59 | 1033 | enum { |
ae36a246 RH |
1034 | /* Instruction exits the translation block. */ |
1035 | TCG_OPF_BB_EXIT = 0x01, | |
8399ad59 | 1036 | /* Instruction defines the end of a basic block. */ |
ae36a246 | 1037 | TCG_OPF_BB_END = 0x02, |
8399ad59 | 1038 | /* Instruction clobbers call registers and potentially update globals. */ |
ae36a246 | 1039 | TCG_OPF_CALL_CLOBBER = 0x04, |
3d5c5f87 AJ |
1040 | /* Instruction has side effects: it cannot be removed if its outputs |
1041 | are not used, and might trigger exceptions. */ | |
ae36a246 | 1042 | TCG_OPF_SIDE_EFFECTS = 0x08, |
8399ad59 | 1043 | /* Instruction operands are 64-bits (otherwise 32-bits). */ |
ae36a246 | 1044 | TCG_OPF_64BIT = 0x10, |
c1a61f6c RH |
1045 | /* Instruction is optional and not implemented by the host, or insn |
1046 | is generic and should not be implemened by the host. */ | |
ae36a246 | 1047 | TCG_OPF_NOT_PRESENT = 0x20, |
d2fd745f | 1048 | /* Instruction operands are vectors. */ |
ae36a246 | 1049 | TCG_OPF_VECTOR = 0x40, |
b4cb76e6 RH |
1050 | /* Instruction is a conditional branch. */ |
1051 | TCG_OPF_COND_BRANCH = 0x80 | |
8399ad59 | 1052 | }; |
c896fe29 FB |
1053 | |
1054 | typedef struct TCGOpDef { | |
1055 | const char *name; | |
1056 | uint8_t nb_oargs, nb_iargs, nb_cargs, nb_args; | |
1057 | uint8_t flags; | |
c896fe29 | 1058 | TCGArgConstraint *args_ct; |
c896fe29 | 1059 | } TCGOpDef; |
8399ad59 RH |
1060 | |
1061 | extern TCGOpDef tcg_op_defs[]; | |
2a24374a SW |
1062 | extern const size_t tcg_op_defs_max; |
1063 | ||
c896fe29 | 1064 | typedef struct TCGTargetOpDef { |
a9751609 | 1065 | TCGOpcode op; |
c896fe29 FB |
1066 | const char *args_ct_str[TCG_MAX_OP_ARGS]; |
1067 | } TCGTargetOpDef; | |
1068 | ||
c896fe29 FB |
1069 | #define tcg_abort() \ |
1070 | do {\ | |
1071 | fprintf(stderr, "%s:%d: tcg fatal error\n", __FILE__, __LINE__);\ | |
1072 | abort();\ | |
1073 | } while (0) | |
1074 | ||
be0f34b5 RH |
1075 | bool tcg_op_supported(TCGOpcode op); |
1076 | ||
ae8b75dc | 1077 | void tcg_gen_callN(void *func, TCGTemp *ret, int nargs, TCGTemp **args); |
a7812ae4 | 1078 | |
15fa08f8 | 1079 | TCGOp *tcg_emit_op(TCGOpcode opc); |
0c627cdc | 1080 | void tcg_op_remove(TCGContext *s, TCGOp *op); |
ac1043f6 EC |
1081 | TCGOp *tcg_op_insert_before(TCGContext *s, TCGOp *op, TCGOpcode opc); |
1082 | TCGOp *tcg_op_insert_after(TCGContext *s, TCGOp *op, TCGOpcode opc); | |
5a18407f | 1083 | |
c45cb8bb | 1084 | void tcg_optimize(TCGContext *s); |
a7812ae4 | 1085 | |
c0522136 | 1086 | /* Allocate a new temporary and initialize it with a constant. */ |
a7812ae4 PB |
1087 | TCGv_i32 tcg_const_i32(int32_t val); |
1088 | TCGv_i64 tcg_const_i64(int64_t val); | |
1089 | TCGv_i32 tcg_const_local_i32(int32_t val); | |
1090 | TCGv_i64 tcg_const_local_i64(int64_t val); | |
d2fd745f RH |
1091 | TCGv_vec tcg_const_zeros_vec(TCGType); |
1092 | TCGv_vec tcg_const_ones_vec(TCGType); | |
1093 | TCGv_vec tcg_const_zeros_vec_matching(TCGv_vec); | |
1094 | TCGv_vec tcg_const_ones_vec_matching(TCGv_vec); | |
a7812ae4 | 1095 | |
c0522136 RH |
1096 | /* |
1097 | * Locate or create a read-only temporary that is a constant. | |
1098 | * This kind of temporary need not and should not be freed. | |
1099 | */ | |
1100 | TCGTemp *tcg_constant_internal(TCGType type, int64_t val); | |
1101 | ||
1102 | static inline TCGv_i32 tcg_constant_i32(int32_t val) | |
1103 | { | |
1104 | return temp_tcgv_i32(tcg_constant_internal(TCG_TYPE_I32, val)); | |
1105 | } | |
1106 | ||
1107 | static inline TCGv_i64 tcg_constant_i64(int64_t val) | |
1108 | { | |
1109 | return temp_tcgv_i64(tcg_constant_internal(TCG_TYPE_I64, val)); | |
1110 | } | |
1111 | ||
1112 | TCGv_vec tcg_constant_vec(TCGType type, unsigned vece, int64_t val); | |
88d4005b | 1113 | TCGv_vec tcg_constant_vec_matching(TCGv_vec match, unsigned vece, int64_t val); |
c0522136 | 1114 | |
5bfa8034 RH |
1115 | #if UINTPTR_MAX == UINT32_MAX |
1116 | # define tcg_const_ptr(x) ((TCGv_ptr)tcg_const_i32((intptr_t)(x))) | |
1117 | # define tcg_const_local_ptr(x) ((TCGv_ptr)tcg_const_local_i32((intptr_t)(x))) | |
1118 | #else | |
1119 | # define tcg_const_ptr(x) ((TCGv_ptr)tcg_const_i64((intptr_t)(x))) | |
1120 | # define tcg_const_local_ptr(x) ((TCGv_ptr)tcg_const_local_i64((intptr_t)(x))) | |
1121 | #endif | |
1122 | ||
42a268c2 RH |
1123 | TCGLabel *gen_new_label(void); |
1124 | ||
1125 | /** | |
1126 | * label_arg | |
1127 | * @l: label | |
1128 | * | |
1129 | * Encode a label for storage in the TCG opcode stream. | |
1130 | */ | |
1131 | ||
1132 | static inline TCGArg label_arg(TCGLabel *l) | |
1133 | { | |
51e3972c | 1134 | return (uintptr_t)l; |
42a268c2 RH |
1135 | } |
1136 | ||
1137 | /** | |
1138 | * arg_label | |
1139 | * @i: value | |
1140 | * | |
1141 | * The opposite of label_arg. Retrieve a label from the | |
1142 | * encoding of the TCG opcode stream. | |
1143 | */ | |
1144 | ||
51e3972c | 1145 | static inline TCGLabel *arg_label(TCGArg i) |
42a268c2 | 1146 | { |
51e3972c | 1147 | return (TCGLabel *)(uintptr_t)i; |
42a268c2 RH |
1148 | } |
1149 | ||
52a1f64e RH |
1150 | /** |
1151 | * tcg_ptr_byte_diff | |
1152 | * @a, @b: addresses to be differenced | |
1153 | * | |
1154 | * There are many places within the TCG backends where we need a byte | |
1155 | * difference between two pointers. While this can be accomplished | |
1156 | * with local casting, it's easy to get wrong -- especially if one is | |
1157 | * concerned with the signedness of the result. | |
1158 | * | |
1159 | * This version relies on GCC's void pointer arithmetic to get the | |
1160 | * correct result. | |
1161 | */ | |
1162 | ||
db0c51a3 | 1163 | static inline ptrdiff_t tcg_ptr_byte_diff(const void *a, const void *b) |
52a1f64e RH |
1164 | { |
1165 | return a - b; | |
1166 | } | |
1167 | ||
1168 | /** | |
1169 | * tcg_pcrel_diff | |
1170 | * @s: the tcg context | |
1171 | * @target: address of the target | |
1172 | * | |
1173 | * Produce a pc-relative difference, from the current code_ptr | |
1174 | * to the destination address. | |
1175 | */ | |
1176 | ||
db0c51a3 | 1177 | static inline ptrdiff_t tcg_pcrel_diff(TCGContext *s, const void *target) |
52a1f64e | 1178 | { |
db0c51a3 | 1179 | return tcg_ptr_byte_diff(target, tcg_splitwx_to_rx(s->code_ptr)); |
52a1f64e RH |
1180 | } |
1181 | ||
44c7197f RH |
1182 | /** |
1183 | * tcg_tbrel_diff | |
1184 | * @s: the tcg context | |
1185 | * @target: address of the target | |
1186 | * | |
1187 | * Produce a difference, from the beginning of the current TB code | |
1188 | * to the destination address. | |
1189 | */ | |
1190 | static inline ptrdiff_t tcg_tbrel_diff(TCGContext *s, const void *target) | |
1191 | { | |
1192 | return tcg_ptr_byte_diff(target, tcg_splitwx_to_rx(s->code_buf)); | |
1193 | } | |
1194 | ||
52a1f64e RH |
1195 | /** |
1196 | * tcg_current_code_size | |
1197 | * @s: the tcg context | |
1198 | * | |
1199 | * Compute the current code size within the translation block. | |
1200 | * This is used to fill in qemu's data structures for goto_tb. | |
1201 | */ | |
1202 | ||
1203 | static inline size_t tcg_current_code_size(TCGContext *s) | |
1204 | { | |
1205 | return tcg_ptr_byte_diff(s->code_ptr, s->code_buf); | |
1206 | } | |
1207 | ||
14776ab5 | 1208 | /* Combine the MemOp and mmu_idx parameters into a single value. */ |
59227d5d RH |
1209 | typedef uint32_t TCGMemOpIdx; |
1210 | ||
1211 | /** | |
1212 | * make_memop_idx | |
1213 | * @op: memory operation | |
1214 | * @idx: mmu index | |
1215 | * | |
1216 | * Encode these values into a single parameter. | |
1217 | */ | |
14776ab5 | 1218 | static inline TCGMemOpIdx make_memop_idx(MemOp op, unsigned idx) |
59227d5d RH |
1219 | { |
1220 | tcg_debug_assert(idx <= 15); | |
1221 | return (op << 4) | idx; | |
1222 | } | |
1223 | ||
1224 | /** | |
1225 | * get_memop | |
1226 | * @oi: combined op/idx parameter | |
1227 | * | |
1228 | * Extract the memory operation from the combined value. | |
1229 | */ | |
14776ab5 | 1230 | static inline MemOp get_memop(TCGMemOpIdx oi) |
59227d5d RH |
1231 | { |
1232 | return oi >> 4; | |
1233 | } | |
1234 | ||
1235 | /** | |
1236 | * get_mmuidx | |
1237 | * @oi: combined op/idx parameter | |
1238 | * | |
1239 | * Extract the mmu index from the combined value. | |
1240 | */ | |
1241 | static inline unsigned get_mmuidx(TCGMemOpIdx oi) | |
1242 | { | |
1243 | return oi & 15; | |
1244 | } | |
1245 | ||
0980011b PM |
1246 | /** |
1247 | * tcg_qemu_tb_exec: | |
819af24b | 1248 | * @env: pointer to CPUArchState for the CPU |
0980011b PM |
1249 | * @tb_ptr: address of generated code for the TB to execute |
1250 | * | |
1251 | * Start executing code from a given translation block. | |
1252 | * Where translation blocks have been linked, execution | |
1253 | * may proceed from the given TB into successive ones. | |
1254 | * Control eventually returns only when some action is needed | |
1255 | * from the top-level loop: either control must pass to a TB | |
1256 | * which has not yet been directly linked, or an asynchronous | |
1257 | * event such as an interrupt needs handling. | |
1258 | * | |
819af24b SF |
1259 | * Return: The return value is the value passed to the corresponding |
1260 | * tcg_gen_exit_tb() at translation time of the last TB attempted to execute. | |
1261 | * The value is either zero or a 4-byte aligned pointer to that TB combined | |
1262 | * with additional information in its two least significant bits. The | |
1263 | * additional information is encoded as follows: | |
0980011b PM |
1264 | * 0, 1: the link between this TB and the next is via the specified |
1265 | * TB index (0 or 1). That is, we left the TB via (the equivalent | |
1266 | * of) "goto_tb <index>". The main loop uses this to determine | |
1267 | * how to link the TB just executed to the next. | |
1268 | * 2: we are using instruction counting code generation, and we | |
1269 | * did not start executing this TB because the instruction counter | |
819af24b | 1270 | * would hit zero midway through it. In this case the pointer |
0980011b PM |
1271 | * returned is the TB we were about to execute, and the caller must |
1272 | * arrange to execute the remaining count of instructions. | |
378df4b2 PM |
1273 | * 3: we stopped because the CPU's exit_request flag was set |
1274 | * (usually meaning that there is an interrupt that needs to be | |
819af24b SF |
1275 | * handled). The pointer returned is the TB we were about to execute |
1276 | * when we noticed the pending exit request. | |
0980011b PM |
1277 | * |
1278 | * If the bottom two bits indicate an exit-via-index then the CPU | |
1279 | * state is correctly synchronised and ready for execution of the next | |
1280 | * TB (and in particular the guest PC is the address to execute next). | |
1281 | * Otherwise, we gave up on execution of this TB before it started, and | |
fee068e4 | 1282 | * the caller must fix up the CPU state by calling the CPU's |
819af24b | 1283 | * synchronize_from_tb() method with the TB pointer we return (falling |
fee068e4 PC |
1284 | * back to calling the CPU's set_pc method with tb->pb if no |
1285 | * synchronize_from_tb() method exists). | |
0980011b PM |
1286 | * |
1287 | * Note that TCG targets may use a different definition of tcg_qemu_tb_exec | |
1288 | * to this default (which just calls the prologue.code emitted by | |
1289 | * tcg_target_qemu_prologue()). | |
1290 | */ | |
07ea28b4 RH |
1291 | #define TB_EXIT_MASK 3 |
1292 | #define TB_EXIT_IDX0 0 | |
1293 | #define TB_EXIT_IDX1 1 | |
1294 | #define TB_EXIT_IDXMAX 1 | |
378df4b2 | 1295 | #define TB_EXIT_REQUESTED 3 |
0980011b | 1296 | |
b91ccb31 | 1297 | #ifdef CONFIG_TCG_INTERPRETER |
db0c51a3 | 1298 | uintptr_t tcg_qemu_tb_exec(CPUArchState *env, const void *tb_ptr); |
5a58e884 | 1299 | #else |
db0c51a3 | 1300 | typedef uintptr_t tcg_prologue_fn(CPUArchState *env, const void *tb_ptr); |
b91ccb31 | 1301 | extern tcg_prologue_fn *tcg_qemu_tb_exec; |
932a6909 | 1302 | #endif |
813da627 | 1303 | |
755bf9e5 | 1304 | void tcg_register_jit(const void *buf, size_t buf_size); |
b76f0d8c | 1305 | |
db432672 RH |
1306 | #if TCG_TARGET_MAYBE_vec |
1307 | /* Return zero if the tuple (opc, type, vece) is unsupportable; | |
1308 | return > 0 if it is directly supportable; | |
1309 | return < 0 if we must call tcg_expand_vec_op. */ | |
1310 | int tcg_can_emit_vec_op(TCGOpcode, TCGType, unsigned); | |
1311 | #else | |
1312 | static inline int tcg_can_emit_vec_op(TCGOpcode o, TCGType t, unsigned ve) | |
1313 | { | |
1314 | return 0; | |
1315 | } | |
1316 | #endif | |
1317 | ||
1318 | /* Expand the tuple (opc, type, vece) on the given arguments. */ | |
1319 | void tcg_expand_vec_op(TCGOpcode, TCGType, unsigned, TCGArg, ...); | |
1320 | ||
1321 | /* Replicate a constant C accoring to the log2 of the element size. */ | |
1322 | uint64_t dup_const(unsigned vece, uint64_t c); | |
1323 | ||
1324 | #define dup_const(VECE, C) \ | |
1325 | (__builtin_constant_p(VECE) \ | |
1326 | ? ( (VECE) == MO_8 ? 0x0101010101010101ull * (uint8_t)(C) \ | |
1327 | : (VECE) == MO_16 ? 0x0001000100010001ull * (uint16_t)(C) \ | |
1328 | : (VECE) == MO_32 ? 0x0000000100000001ull * (uint32_t)(C) \ | |
666cc794 RH |
1329 | : (VECE) == MO_64 ? (uint64_t)(C) \ |
1330 | : (qemu_build_not_reached_always(), 0)) \ | |
db432672 RH |
1331 | : dup_const(VECE, C)) |
1332 | ||
1333 | ||
e58eb534 RH |
1334 | /* |
1335 | * Memory helpers that will be used by TCG generated code. | |
1336 | */ | |
1337 | #ifdef CONFIG_SOFTMMU | |
c8f94df5 RH |
1338 | /* Value zero-extended to tcg register size. */ |
1339 | tcg_target_ulong helper_ret_ldub_mmu(CPUArchState *env, target_ulong addr, | |
3972ef6f | 1340 | TCGMemOpIdx oi, uintptr_t retaddr); |
867b3201 | 1341 | tcg_target_ulong helper_le_lduw_mmu(CPUArchState *env, target_ulong addr, |
3972ef6f | 1342 | TCGMemOpIdx oi, uintptr_t retaddr); |
867b3201 | 1343 | tcg_target_ulong helper_le_ldul_mmu(CPUArchState *env, target_ulong addr, |
3972ef6f | 1344 | TCGMemOpIdx oi, uintptr_t retaddr); |
867b3201 | 1345 | uint64_t helper_le_ldq_mmu(CPUArchState *env, target_ulong addr, |
3972ef6f | 1346 | TCGMemOpIdx oi, uintptr_t retaddr); |
867b3201 | 1347 | tcg_target_ulong helper_be_lduw_mmu(CPUArchState *env, target_ulong addr, |
3972ef6f | 1348 | TCGMemOpIdx oi, uintptr_t retaddr); |
867b3201 | 1349 | tcg_target_ulong helper_be_ldul_mmu(CPUArchState *env, target_ulong addr, |
3972ef6f | 1350 | TCGMemOpIdx oi, uintptr_t retaddr); |
867b3201 | 1351 | uint64_t helper_be_ldq_mmu(CPUArchState *env, target_ulong addr, |
3972ef6f | 1352 | TCGMemOpIdx oi, uintptr_t retaddr); |
e58eb534 | 1353 | |
c8f94df5 RH |
1354 | /* Value sign-extended to tcg register size. */ |
1355 | tcg_target_ulong helper_ret_ldsb_mmu(CPUArchState *env, target_ulong addr, | |
3972ef6f | 1356 | TCGMemOpIdx oi, uintptr_t retaddr); |
867b3201 | 1357 | tcg_target_ulong helper_le_ldsw_mmu(CPUArchState *env, target_ulong addr, |
3972ef6f | 1358 | TCGMemOpIdx oi, uintptr_t retaddr); |
867b3201 | 1359 | tcg_target_ulong helper_le_ldsl_mmu(CPUArchState *env, target_ulong addr, |
3972ef6f | 1360 | TCGMemOpIdx oi, uintptr_t retaddr); |
867b3201 | 1361 | tcg_target_ulong helper_be_ldsw_mmu(CPUArchState *env, target_ulong addr, |
3972ef6f | 1362 | TCGMemOpIdx oi, uintptr_t retaddr); |
867b3201 | 1363 | tcg_target_ulong helper_be_ldsl_mmu(CPUArchState *env, target_ulong addr, |
3972ef6f | 1364 | TCGMemOpIdx oi, uintptr_t retaddr); |
c8f94df5 | 1365 | |
e58eb534 | 1366 | void helper_ret_stb_mmu(CPUArchState *env, target_ulong addr, uint8_t val, |
3972ef6f | 1367 | TCGMemOpIdx oi, uintptr_t retaddr); |
867b3201 | 1368 | void helper_le_stw_mmu(CPUArchState *env, target_ulong addr, uint16_t val, |
3972ef6f | 1369 | TCGMemOpIdx oi, uintptr_t retaddr); |
867b3201 | 1370 | void helper_le_stl_mmu(CPUArchState *env, target_ulong addr, uint32_t val, |
3972ef6f | 1371 | TCGMemOpIdx oi, uintptr_t retaddr); |
867b3201 | 1372 | void helper_le_stq_mmu(CPUArchState *env, target_ulong addr, uint64_t val, |
3972ef6f | 1373 | TCGMemOpIdx oi, uintptr_t retaddr); |
867b3201 | 1374 | void helper_be_stw_mmu(CPUArchState *env, target_ulong addr, uint16_t val, |
3972ef6f | 1375 | TCGMemOpIdx oi, uintptr_t retaddr); |
867b3201 | 1376 | void helper_be_stl_mmu(CPUArchState *env, target_ulong addr, uint32_t val, |
3972ef6f | 1377 | TCGMemOpIdx oi, uintptr_t retaddr); |
867b3201 | 1378 | void helper_be_stq_mmu(CPUArchState *env, target_ulong addr, uint64_t val, |
3972ef6f | 1379 | TCGMemOpIdx oi, uintptr_t retaddr); |
867b3201 RH |
1380 | |
1381 | /* Temporary aliases until backends are converted. */ | |
1382 | #ifdef TARGET_WORDS_BIGENDIAN | |
1383 | # define helper_ret_ldsw_mmu helper_be_ldsw_mmu | |
1384 | # define helper_ret_lduw_mmu helper_be_lduw_mmu | |
1385 | # define helper_ret_ldsl_mmu helper_be_ldsl_mmu | |
1386 | # define helper_ret_ldul_mmu helper_be_ldul_mmu | |
282dffc8 | 1387 | # define helper_ret_ldl_mmu helper_be_ldul_mmu |
867b3201 RH |
1388 | # define helper_ret_ldq_mmu helper_be_ldq_mmu |
1389 | # define helper_ret_stw_mmu helper_be_stw_mmu | |
1390 | # define helper_ret_stl_mmu helper_be_stl_mmu | |
1391 | # define helper_ret_stq_mmu helper_be_stq_mmu | |
1392 | #else | |
1393 | # define helper_ret_ldsw_mmu helper_le_ldsw_mmu | |
1394 | # define helper_ret_lduw_mmu helper_le_lduw_mmu | |
1395 | # define helper_ret_ldsl_mmu helper_le_ldsl_mmu | |
1396 | # define helper_ret_ldul_mmu helper_le_ldul_mmu | |
282dffc8 | 1397 | # define helper_ret_ldl_mmu helper_le_ldul_mmu |
867b3201 RH |
1398 | # define helper_ret_ldq_mmu helper_le_ldq_mmu |
1399 | # define helper_ret_stw_mmu helper_le_stw_mmu | |
1400 | # define helper_ret_stl_mmu helper_le_stl_mmu | |
1401 | # define helper_ret_stq_mmu helper_le_stq_mmu | |
1402 | #endif | |
e58eb534 | 1403 | |
c482cb11 RH |
1404 | uint32_t helper_atomic_cmpxchgb_mmu(CPUArchState *env, target_ulong addr, |
1405 | uint32_t cmpv, uint32_t newv, | |
1406 | TCGMemOpIdx oi, uintptr_t retaddr); | |
1407 | uint32_t helper_atomic_cmpxchgw_le_mmu(CPUArchState *env, target_ulong addr, | |
1408 | uint32_t cmpv, uint32_t newv, | |
1409 | TCGMemOpIdx oi, uintptr_t retaddr); | |
1410 | uint32_t helper_atomic_cmpxchgl_le_mmu(CPUArchState *env, target_ulong addr, | |
1411 | uint32_t cmpv, uint32_t newv, | |
1412 | TCGMemOpIdx oi, uintptr_t retaddr); | |
1413 | uint64_t helper_atomic_cmpxchgq_le_mmu(CPUArchState *env, target_ulong addr, | |
1414 | uint64_t cmpv, uint64_t newv, | |
1415 | TCGMemOpIdx oi, uintptr_t retaddr); | |
1416 | uint32_t helper_atomic_cmpxchgw_be_mmu(CPUArchState *env, target_ulong addr, | |
1417 | uint32_t cmpv, uint32_t newv, | |
1418 | TCGMemOpIdx oi, uintptr_t retaddr); | |
1419 | uint32_t helper_atomic_cmpxchgl_be_mmu(CPUArchState *env, target_ulong addr, | |
1420 | uint32_t cmpv, uint32_t newv, | |
1421 | TCGMemOpIdx oi, uintptr_t retaddr); | |
1422 | uint64_t helper_atomic_cmpxchgq_be_mmu(CPUArchState *env, target_ulong addr, | |
1423 | uint64_t cmpv, uint64_t newv, | |
1424 | TCGMemOpIdx oi, uintptr_t retaddr); | |
1425 | ||
1426 | #define GEN_ATOMIC_HELPER(NAME, TYPE, SUFFIX) \ | |
1427 | TYPE helper_atomic_ ## NAME ## SUFFIX ## _mmu \ | |
1428 | (CPUArchState *env, target_ulong addr, TYPE val, \ | |
1429 | TCGMemOpIdx oi, uintptr_t retaddr); | |
1430 | ||
df79b996 | 1431 | #ifdef CONFIG_ATOMIC64 |
c482cb11 | 1432 | #define GEN_ATOMIC_HELPER_ALL(NAME) \ |
df79b996 | 1433 | GEN_ATOMIC_HELPER(NAME, uint32_t, b) \ |
c482cb11 | 1434 | GEN_ATOMIC_HELPER(NAME, uint32_t, w_le) \ |
c482cb11 | 1435 | GEN_ATOMIC_HELPER(NAME, uint32_t, w_be) \ |
df79b996 | 1436 | GEN_ATOMIC_HELPER(NAME, uint32_t, l_le) \ |
c482cb11 | 1437 | GEN_ATOMIC_HELPER(NAME, uint32_t, l_be) \ |
df79b996 | 1438 | GEN_ATOMIC_HELPER(NAME, uint64_t, q_le) \ |
c482cb11 | 1439 | GEN_ATOMIC_HELPER(NAME, uint64_t, q_be) |
df79b996 RH |
1440 | #else |
1441 | #define GEN_ATOMIC_HELPER_ALL(NAME) \ | |
1442 | GEN_ATOMIC_HELPER(NAME, uint32_t, b) \ | |
1443 | GEN_ATOMIC_HELPER(NAME, uint32_t, w_le) \ | |
1444 | GEN_ATOMIC_HELPER(NAME, uint32_t, w_be) \ | |
1445 | GEN_ATOMIC_HELPER(NAME, uint32_t, l_le) \ | |
1446 | GEN_ATOMIC_HELPER(NAME, uint32_t, l_be) | |
1447 | #endif | |
c482cb11 RH |
1448 | |
1449 | GEN_ATOMIC_HELPER_ALL(fetch_add) | |
1450 | GEN_ATOMIC_HELPER_ALL(fetch_sub) | |
1451 | GEN_ATOMIC_HELPER_ALL(fetch_and) | |
1452 | GEN_ATOMIC_HELPER_ALL(fetch_or) | |
1453 | GEN_ATOMIC_HELPER_ALL(fetch_xor) | |
5507c2bf RH |
1454 | GEN_ATOMIC_HELPER_ALL(fetch_smin) |
1455 | GEN_ATOMIC_HELPER_ALL(fetch_umin) | |
1456 | GEN_ATOMIC_HELPER_ALL(fetch_smax) | |
1457 | GEN_ATOMIC_HELPER_ALL(fetch_umax) | |
c482cb11 RH |
1458 | |
1459 | GEN_ATOMIC_HELPER_ALL(add_fetch) | |
1460 | GEN_ATOMIC_HELPER_ALL(sub_fetch) | |
1461 | GEN_ATOMIC_HELPER_ALL(and_fetch) | |
1462 | GEN_ATOMIC_HELPER_ALL(or_fetch) | |
1463 | GEN_ATOMIC_HELPER_ALL(xor_fetch) | |
5507c2bf RH |
1464 | GEN_ATOMIC_HELPER_ALL(smin_fetch) |
1465 | GEN_ATOMIC_HELPER_ALL(umin_fetch) | |
1466 | GEN_ATOMIC_HELPER_ALL(smax_fetch) | |
1467 | GEN_ATOMIC_HELPER_ALL(umax_fetch) | |
c482cb11 RH |
1468 | |
1469 | GEN_ATOMIC_HELPER_ALL(xchg) | |
1470 | ||
1471 | #undef GEN_ATOMIC_HELPER_ALL | |
1472 | #undef GEN_ATOMIC_HELPER | |
e58eb534 RH |
1473 | #endif /* CONFIG_SOFTMMU */ |
1474 | ||
e6cd4bb5 RH |
1475 | /* |
1476 | * These aren't really a "proper" helpers because TCG cannot manage Int128. | |
1477 | * However, use the same format as the others, for use by the backends. | |
1478 | * | |
1479 | * The cmpxchg functions are only defined if HAVE_CMPXCHG128; | |
1480 | * the ld/st functions are only defined if HAVE_ATOMIC128, | |
1481 | * as defined by <qemu/atomic128.h>. | |
1482 | */ | |
7ebee43e RH |
1483 | Int128 helper_atomic_cmpxchgo_le_mmu(CPUArchState *env, target_ulong addr, |
1484 | Int128 cmpv, Int128 newv, | |
1485 | TCGMemOpIdx oi, uintptr_t retaddr); | |
1486 | Int128 helper_atomic_cmpxchgo_be_mmu(CPUArchState *env, target_ulong addr, | |
1487 | Int128 cmpv, Int128 newv, | |
1488 | TCGMemOpIdx oi, uintptr_t retaddr); | |
1489 | ||
1490 | Int128 helper_atomic_ldo_le_mmu(CPUArchState *env, target_ulong addr, | |
1491 | TCGMemOpIdx oi, uintptr_t retaddr); | |
1492 | Int128 helper_atomic_ldo_be_mmu(CPUArchState *env, target_ulong addr, | |
1493 | TCGMemOpIdx oi, uintptr_t retaddr); | |
1494 | void helper_atomic_sto_le_mmu(CPUArchState *env, target_ulong addr, Int128 val, | |
1495 | TCGMemOpIdx oi, uintptr_t retaddr); | |
1496 | void helper_atomic_sto_be_mmu(CPUArchState *env, target_ulong addr, Int128 val, | |
1497 | TCGMemOpIdx oi, uintptr_t retaddr); | |
1498 | ||
53229a77 RH |
1499 | #ifdef CONFIG_DEBUG_TCG |
1500 | void tcg_assert_listed_vecop(TCGOpcode); | |
1501 | #else | |
1502 | static inline void tcg_assert_listed_vecop(TCGOpcode op) { } | |
1503 | #endif | |
1504 | ||
1505 | static inline const TCGOpcode *tcg_swap_vecop_list(const TCGOpcode *n) | |
1506 | { | |
1507 | #ifdef CONFIG_DEBUG_TCG | |
1508 | const TCGOpcode *o = tcg_ctx->vecop_list; | |
1509 | tcg_ctx->vecop_list = n; | |
1510 | return o; | |
1511 | #else | |
1512 | return NULL; | |
1513 | #endif | |
1514 | } | |
1515 | ||
1516 | bool tcg_can_emit_vecop_list(const TCGOpcode *, TCGType, unsigned); | |
1517 | ||
e58eb534 | 1518 | #endif /* TCG_H */ |