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81629cba AD |
1 | /* amdgpu_drm.h -- Public header for the amdgpu driver -*- linux-c -*- |
2 | * | |
3 | * Copyright 2000 Precision Insight, Inc., Cedar Park, Texas. | |
4 | * Copyright 2000 VA Linux Systems, Inc., Fremont, California. | |
5 | * Copyright 2002 Tungsten Graphics, Inc., Cedar Park, Texas. | |
6 | * Copyright 2014 Advanced Micro Devices, Inc. | |
7 | * | |
8 | * Permission is hereby granted, free of charge, to any person obtaining a | |
9 | * copy of this software and associated documentation files (the "Software"), | |
10 | * to deal in the Software without restriction, including without limitation | |
11 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
12 | * and/or sell copies of the Software, and to permit persons to whom the | |
13 | * Software is furnished to do so, subject to the following conditions: | |
14 | * | |
15 | * The above copyright notice and this permission notice shall be included in | |
16 | * all copies or substantial portions of the Software. | |
17 | * | |
18 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
19 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
20 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
21 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR | |
22 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, | |
23 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR | |
24 | * OTHER DEALINGS IN THE SOFTWARE. | |
25 | * | |
26 | * Authors: | |
27 | * Kevin E. Martin <martin@valinux.com> | |
28 | * Gareth Hughes <gareth@valinux.com> | |
29 | * Keith Whitwell <keith@tungstengraphics.com> | |
30 | */ | |
31 | ||
32 | #ifndef __AMDGPU_DRM_H__ | |
33 | #define __AMDGPU_DRM_H__ | |
34 | ||
b3fcf36a | 35 | #include "drm.h" |
81629cba | 36 | |
cfa7152f EV |
37 | #if defined(__cplusplus) |
38 | extern "C" { | |
39 | #endif | |
40 | ||
81629cba AD |
41 | #define DRM_AMDGPU_GEM_CREATE 0x00 |
42 | #define DRM_AMDGPU_GEM_MMAP 0x01 | |
43 | #define DRM_AMDGPU_CTX 0x02 | |
44 | #define DRM_AMDGPU_BO_LIST 0x03 | |
45 | #define DRM_AMDGPU_CS 0x04 | |
46 | #define DRM_AMDGPU_INFO 0x05 | |
47 | #define DRM_AMDGPU_GEM_METADATA 0x06 | |
48 | #define DRM_AMDGPU_GEM_WAIT_IDLE 0x07 | |
49 | #define DRM_AMDGPU_GEM_VA 0x08 | |
50 | #define DRM_AMDGPU_WAIT_CS 0x09 | |
51 | #define DRM_AMDGPU_GEM_OP 0x10 | |
52 | #define DRM_AMDGPU_GEM_USERPTR 0x11 | |
eef18a82 | 53 | #define DRM_AMDGPU_WAIT_FENCES 0x12 |
81629cba AD |
54 | |
55 | #define DRM_IOCTL_AMDGPU_GEM_CREATE DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_CREATE, union drm_amdgpu_gem_create) | |
56 | #define DRM_IOCTL_AMDGPU_GEM_MMAP DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_MMAP, union drm_amdgpu_gem_mmap) | |
57 | #define DRM_IOCTL_AMDGPU_CTX DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_CTX, union drm_amdgpu_ctx) | |
58 | #define DRM_IOCTL_AMDGPU_BO_LIST DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_BO_LIST, union drm_amdgpu_bo_list) | |
59 | #define DRM_IOCTL_AMDGPU_CS DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_CS, union drm_amdgpu_cs) | |
60 | #define DRM_IOCTL_AMDGPU_INFO DRM_IOW(DRM_COMMAND_BASE + DRM_AMDGPU_INFO, struct drm_amdgpu_info) | |
61 | #define DRM_IOCTL_AMDGPU_GEM_METADATA DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_METADATA, struct drm_amdgpu_gem_metadata) | |
62 | #define DRM_IOCTL_AMDGPU_GEM_WAIT_IDLE DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_WAIT_IDLE, union drm_amdgpu_gem_wait_idle) | |
34b5f6a6 | 63 | #define DRM_IOCTL_AMDGPU_GEM_VA DRM_IOW(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_VA, struct drm_amdgpu_gem_va) |
81629cba AD |
64 | #define DRM_IOCTL_AMDGPU_WAIT_CS DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_WAIT_CS, union drm_amdgpu_wait_cs) |
65 | #define DRM_IOCTL_AMDGPU_GEM_OP DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_OP, struct drm_amdgpu_gem_op) | |
66 | #define DRM_IOCTL_AMDGPU_GEM_USERPTR DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_USERPTR, struct drm_amdgpu_gem_userptr) | |
eef18a82 | 67 | #define DRM_IOCTL_AMDGPU_WAIT_FENCES DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_WAIT_FENCES, union drm_amdgpu_wait_fences) |
81629cba AD |
68 | |
69 | #define AMDGPU_GEM_DOMAIN_CPU 0x1 | |
70 | #define AMDGPU_GEM_DOMAIN_GTT 0x2 | |
71 | #define AMDGPU_GEM_DOMAIN_VRAM 0x4 | |
72 | #define AMDGPU_GEM_DOMAIN_GDS 0x8 | |
73 | #define AMDGPU_GEM_DOMAIN_GWS 0x10 | |
74 | #define AMDGPU_GEM_DOMAIN_OA 0x20 | |
75 | ||
81629cba AD |
76 | /* Flag that CPU access will be required for the case of VRAM domain */ |
77 | #define AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED (1 << 0) | |
78 | /* Flag that CPU access will not work, this VRAM domain is invisible */ | |
79 | #define AMDGPU_GEM_CREATE_NO_CPU_ACCESS (1 << 1) | |
81629cba | 80 | /* Flag that USWC attributes should be used for GTT */ |
88671288 | 81 | #define AMDGPU_GEM_CREATE_CPU_GTT_USWC (1 << 2) |
4fea83ff FC |
82 | /* Flag that the memory should be in VRAM and cleared */ |
83 | #define AMDGPU_GEM_CREATE_VRAM_CLEARED (1 << 3) | |
e7893c4b CZ |
84 | /* Flag that create shadow bo(GTT) while allocating vram bo */ |
85 | #define AMDGPU_GEM_CREATE_SHADOW (1 << 4) | |
03f48dd5 CK |
86 | /* Flag that allocating the BO should use linear VRAM */ |
87 | #define AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS (1 << 5) | |
81629cba | 88 | |
81629cba AD |
89 | struct drm_amdgpu_gem_create_in { |
90 | /** the requested memory size */ | |
2ce9dde0 | 91 | __u64 bo_size; |
81629cba | 92 | /** physical start_addr alignment in bytes for some HW requirements */ |
2ce9dde0 | 93 | __u64 alignment; |
81629cba | 94 | /** the requested memory domains */ |
2ce9dde0 | 95 | __u64 domains; |
81629cba | 96 | /** allocation flags */ |
2ce9dde0 | 97 | __u64 domain_flags; |
81629cba AD |
98 | }; |
99 | ||
100 | struct drm_amdgpu_gem_create_out { | |
101 | /** returned GEM object handle */ | |
2ce9dde0 MR |
102 | __u32 handle; |
103 | __u32 _pad; | |
81629cba AD |
104 | }; |
105 | ||
106 | union drm_amdgpu_gem_create { | |
107 | struct drm_amdgpu_gem_create_in in; | |
108 | struct drm_amdgpu_gem_create_out out; | |
109 | }; | |
110 | ||
111 | /** Opcode to create new residency list. */ | |
112 | #define AMDGPU_BO_LIST_OP_CREATE 0 | |
113 | /** Opcode to destroy previously created residency list */ | |
114 | #define AMDGPU_BO_LIST_OP_DESTROY 1 | |
115 | /** Opcode to update resource information in the list */ | |
116 | #define AMDGPU_BO_LIST_OP_UPDATE 2 | |
117 | ||
118 | struct drm_amdgpu_bo_list_in { | |
119 | /** Type of operation */ | |
2ce9dde0 | 120 | __u32 operation; |
81629cba | 121 | /** Handle of list or 0 if we want to create one */ |
2ce9dde0 | 122 | __u32 list_handle; |
81629cba | 123 | /** Number of BOs in list */ |
2ce9dde0 | 124 | __u32 bo_number; |
81629cba | 125 | /** Size of each element describing BO */ |
2ce9dde0 | 126 | __u32 bo_info_size; |
81629cba | 127 | /** Pointer to array describing BOs */ |
2ce9dde0 | 128 | __u64 bo_info_ptr; |
81629cba AD |
129 | }; |
130 | ||
131 | struct drm_amdgpu_bo_list_entry { | |
132 | /** Handle of BO */ | |
2ce9dde0 | 133 | __u32 bo_handle; |
81629cba | 134 | /** New (if specified) BO priority to be used during migration */ |
2ce9dde0 | 135 | __u32 bo_priority; |
81629cba AD |
136 | }; |
137 | ||
138 | struct drm_amdgpu_bo_list_out { | |
139 | /** Handle of resource list */ | |
2ce9dde0 MR |
140 | __u32 list_handle; |
141 | __u32 _pad; | |
81629cba AD |
142 | }; |
143 | ||
144 | union drm_amdgpu_bo_list { | |
145 | struct drm_amdgpu_bo_list_in in; | |
146 | struct drm_amdgpu_bo_list_out out; | |
147 | }; | |
148 | ||
149 | /* context related */ | |
150 | #define AMDGPU_CTX_OP_ALLOC_CTX 1 | |
151 | #define AMDGPU_CTX_OP_FREE_CTX 2 | |
152 | #define AMDGPU_CTX_OP_QUERY_STATE 3 | |
153 | ||
d94aed5a MO |
154 | /* GPU reset status */ |
155 | #define AMDGPU_CTX_NO_RESET 0 | |
675da0dd CK |
156 | /* this the context caused it */ |
157 | #define AMDGPU_CTX_GUILTY_RESET 1 | |
158 | /* some other context caused it */ | |
159 | #define AMDGPU_CTX_INNOCENT_RESET 2 | |
160 | /* unknown cause */ | |
161 | #define AMDGPU_CTX_UNKNOWN_RESET 3 | |
d94aed5a | 162 | |
81629cba | 163 | struct drm_amdgpu_ctx_in { |
675da0dd | 164 | /** AMDGPU_CTX_OP_* */ |
2ce9dde0 | 165 | __u32 op; |
675da0dd | 166 | /** For future use, no flags defined so far */ |
2ce9dde0 MR |
167 | __u32 flags; |
168 | __u32 ctx_id; | |
169 | __u32 _pad; | |
81629cba AD |
170 | }; |
171 | ||
172 | union drm_amdgpu_ctx_out { | |
173 | struct { | |
2ce9dde0 MR |
174 | __u32 ctx_id; |
175 | __u32 _pad; | |
81629cba AD |
176 | } alloc; |
177 | ||
178 | struct { | |
675da0dd | 179 | /** For future use, no flags defined so far */ |
2ce9dde0 | 180 | __u64 flags; |
d94aed5a | 181 | /** Number of resets caused by this context so far. */ |
2ce9dde0 | 182 | __u32 hangs; |
d94aed5a | 183 | /** Reset status since the last call of the ioctl. */ |
2ce9dde0 | 184 | __u32 reset_status; |
81629cba AD |
185 | } state; |
186 | }; | |
187 | ||
188 | union drm_amdgpu_ctx { | |
189 | struct drm_amdgpu_ctx_in in; | |
190 | union drm_amdgpu_ctx_out out; | |
191 | }; | |
192 | ||
193 | /* | |
194 | * This is not a reliable API and you should expect it to fail for any | |
195 | * number of reasons and have fallback path that do not use userptr to | |
196 | * perform any operation. | |
197 | */ | |
198 | #define AMDGPU_GEM_USERPTR_READONLY (1 << 0) | |
199 | #define AMDGPU_GEM_USERPTR_ANONONLY (1 << 1) | |
200 | #define AMDGPU_GEM_USERPTR_VALIDATE (1 << 2) | |
201 | #define AMDGPU_GEM_USERPTR_REGISTER (1 << 3) | |
202 | ||
203 | struct drm_amdgpu_gem_userptr { | |
2ce9dde0 MR |
204 | __u64 addr; |
205 | __u64 size; | |
675da0dd | 206 | /* AMDGPU_GEM_USERPTR_* */ |
2ce9dde0 | 207 | __u32 flags; |
675da0dd | 208 | /* Resulting GEM handle */ |
2ce9dde0 | 209 | __u32 handle; |
81629cba AD |
210 | }; |
211 | ||
00ac6f6b | 212 | /* SI-CI-VI: */ |
fbd76d59 MO |
213 | /* same meaning as the GB_TILE_MODE and GL_MACRO_TILE_MODE fields */ |
214 | #define AMDGPU_TILING_ARRAY_MODE_SHIFT 0 | |
215 | #define AMDGPU_TILING_ARRAY_MODE_MASK 0xf | |
216 | #define AMDGPU_TILING_PIPE_CONFIG_SHIFT 4 | |
217 | #define AMDGPU_TILING_PIPE_CONFIG_MASK 0x1f | |
218 | #define AMDGPU_TILING_TILE_SPLIT_SHIFT 9 | |
219 | #define AMDGPU_TILING_TILE_SPLIT_MASK 0x7 | |
220 | #define AMDGPU_TILING_MICRO_TILE_MODE_SHIFT 12 | |
221 | #define AMDGPU_TILING_MICRO_TILE_MODE_MASK 0x7 | |
222 | #define AMDGPU_TILING_BANK_WIDTH_SHIFT 15 | |
223 | #define AMDGPU_TILING_BANK_WIDTH_MASK 0x3 | |
224 | #define AMDGPU_TILING_BANK_HEIGHT_SHIFT 17 | |
225 | #define AMDGPU_TILING_BANK_HEIGHT_MASK 0x3 | |
226 | #define AMDGPU_TILING_MACRO_TILE_ASPECT_SHIFT 19 | |
227 | #define AMDGPU_TILING_MACRO_TILE_ASPECT_MASK 0x3 | |
228 | #define AMDGPU_TILING_NUM_BANKS_SHIFT 21 | |
229 | #define AMDGPU_TILING_NUM_BANKS_MASK 0x3 | |
230 | ||
00ac6f6b AD |
231 | /* GFX9 and later: */ |
232 | #define AMDGPU_TILING_SWIZZLE_MODE_SHIFT 0 | |
233 | #define AMDGPU_TILING_SWIZZLE_MODE_MASK 0x1f | |
234 | ||
235 | /* Set/Get helpers for tiling flags. */ | |
fbd76d59 | 236 | #define AMDGPU_TILING_SET(field, value) \ |
00ac6f6b | 237 | (((__u64)(value) & AMDGPU_TILING_##field##_MASK) << AMDGPU_TILING_##field##_SHIFT) |
fbd76d59 | 238 | #define AMDGPU_TILING_GET(value, field) \ |
00ac6f6b | 239 | (((__u64)(value) >> AMDGPU_TILING_##field##_SHIFT) & AMDGPU_TILING_##field##_MASK) |
81629cba AD |
240 | |
241 | #define AMDGPU_GEM_METADATA_OP_SET_METADATA 1 | |
242 | #define AMDGPU_GEM_METADATA_OP_GET_METADATA 2 | |
243 | ||
244 | /** The same structure is shared for input/output */ | |
245 | struct drm_amdgpu_gem_metadata { | |
675da0dd | 246 | /** GEM Object handle */ |
2ce9dde0 | 247 | __u32 handle; |
675da0dd | 248 | /** Do we want get or set metadata */ |
2ce9dde0 | 249 | __u32 op; |
81629cba | 250 | struct { |
675da0dd | 251 | /** For future use, no flags defined so far */ |
2ce9dde0 | 252 | __u64 flags; |
675da0dd | 253 | /** family specific tiling info */ |
2ce9dde0 MR |
254 | __u64 tiling_info; |
255 | __u32 data_size_bytes; | |
256 | __u32 data[64]; | |
81629cba AD |
257 | } data; |
258 | }; | |
259 | ||
260 | struct drm_amdgpu_gem_mmap_in { | |
675da0dd | 261 | /** the GEM object handle */ |
2ce9dde0 MR |
262 | __u32 handle; |
263 | __u32 _pad; | |
81629cba AD |
264 | }; |
265 | ||
266 | struct drm_amdgpu_gem_mmap_out { | |
675da0dd | 267 | /** mmap offset from the vma offset manager */ |
2ce9dde0 | 268 | __u64 addr_ptr; |
81629cba AD |
269 | }; |
270 | ||
271 | union drm_amdgpu_gem_mmap { | |
272 | struct drm_amdgpu_gem_mmap_in in; | |
273 | struct drm_amdgpu_gem_mmap_out out; | |
274 | }; | |
275 | ||
276 | struct drm_amdgpu_gem_wait_idle_in { | |
675da0dd | 277 | /** GEM object handle */ |
2ce9dde0 | 278 | __u32 handle; |
675da0dd | 279 | /** For future use, no flags defined so far */ |
2ce9dde0 | 280 | __u32 flags; |
675da0dd | 281 | /** Absolute timeout to wait */ |
2ce9dde0 | 282 | __u64 timeout; |
81629cba AD |
283 | }; |
284 | ||
285 | struct drm_amdgpu_gem_wait_idle_out { | |
675da0dd | 286 | /** BO status: 0 - BO is idle, 1 - BO is busy */ |
2ce9dde0 | 287 | __u32 status; |
675da0dd | 288 | /** Returned current memory domain */ |
2ce9dde0 | 289 | __u32 domain; |
81629cba AD |
290 | }; |
291 | ||
292 | union drm_amdgpu_gem_wait_idle { | |
293 | struct drm_amdgpu_gem_wait_idle_in in; | |
294 | struct drm_amdgpu_gem_wait_idle_out out; | |
295 | }; | |
296 | ||
297 | struct drm_amdgpu_wait_cs_in { | |
d7b1eeb2 ML |
298 | /* Command submission handle |
299 | * handle equals 0 means none to wait for | |
080b24eb | 300 | * handle equals ~0ull means wait for the latest sequence number |
d7b1eeb2 | 301 | */ |
2ce9dde0 | 302 | __u64 handle; |
675da0dd | 303 | /** Absolute timeout to wait */ |
2ce9dde0 MR |
304 | __u64 timeout; |
305 | __u32 ip_type; | |
306 | __u32 ip_instance; | |
307 | __u32 ring; | |
308 | __u32 ctx_id; | |
81629cba AD |
309 | }; |
310 | ||
311 | struct drm_amdgpu_wait_cs_out { | |
675da0dd | 312 | /** CS status: 0 - CS completed, 1 - CS still busy */ |
2ce9dde0 | 313 | __u64 status; |
81629cba AD |
314 | }; |
315 | ||
316 | union drm_amdgpu_wait_cs { | |
317 | struct drm_amdgpu_wait_cs_in in; | |
318 | struct drm_amdgpu_wait_cs_out out; | |
319 | }; | |
320 | ||
eef18a82 JZ |
321 | struct drm_amdgpu_fence { |
322 | __u32 ctx_id; | |
323 | __u32 ip_type; | |
324 | __u32 ip_instance; | |
325 | __u32 ring; | |
326 | __u64 seq_no; | |
327 | }; | |
328 | ||
329 | struct drm_amdgpu_wait_fences_in { | |
330 | /** This points to uint64_t * which points to fences */ | |
331 | __u64 fences; | |
332 | __u32 fence_count; | |
333 | __u32 wait_all; | |
334 | __u64 timeout_ns; | |
335 | }; | |
336 | ||
337 | struct drm_amdgpu_wait_fences_out { | |
338 | __u32 status; | |
339 | __u32 first_signaled; | |
340 | }; | |
341 | ||
342 | union drm_amdgpu_wait_fences { | |
343 | struct drm_amdgpu_wait_fences_in in; | |
344 | struct drm_amdgpu_wait_fences_out out; | |
345 | }; | |
346 | ||
675da0dd CK |
347 | #define AMDGPU_GEM_OP_GET_GEM_CREATE_INFO 0 |
348 | #define AMDGPU_GEM_OP_SET_PLACEMENT 1 | |
349 | ||
81629cba AD |
350 | /* Sets or returns a value associated with a buffer. */ |
351 | struct drm_amdgpu_gem_op { | |
675da0dd | 352 | /** GEM object handle */ |
2ce9dde0 | 353 | __u32 handle; |
675da0dd | 354 | /** AMDGPU_GEM_OP_* */ |
2ce9dde0 | 355 | __u32 op; |
675da0dd | 356 | /** Input or return value */ |
2ce9dde0 | 357 | __u64 value; |
81629cba AD |
358 | }; |
359 | ||
81629cba AD |
360 | #define AMDGPU_VA_OP_MAP 1 |
361 | #define AMDGPU_VA_OP_UNMAP 2 | |
dc54d3d1 | 362 | #define AMDGPU_VA_OP_CLEAR 3 |
80f95c57 | 363 | #define AMDGPU_VA_OP_REPLACE 4 |
81629cba | 364 | |
fc220f65 CK |
365 | /* Delay the page table update till the next CS */ |
366 | #define AMDGPU_VM_DELAY_UPDATE (1 << 0) | |
367 | ||
81629cba AD |
368 | /* Mapping flags */ |
369 | /* readable mapping */ | |
370 | #define AMDGPU_VM_PAGE_READABLE (1 << 1) | |
371 | /* writable mapping */ | |
372 | #define AMDGPU_VM_PAGE_WRITEABLE (1 << 2) | |
373 | /* executable mapping, new for VI */ | |
374 | #define AMDGPU_VM_PAGE_EXECUTABLE (1 << 3) | |
b85891bd JZ |
375 | /* partially resident texture */ |
376 | #define AMDGPU_VM_PAGE_PRT (1 << 4) | |
66e02bc3 AX |
377 | /* MTYPE flags use bit 5 to 8 */ |
378 | #define AMDGPU_VM_MTYPE_MASK (0xf << 5) | |
379 | /* Default MTYPE. Pre-AI must use this. Recommended for newer ASICs. */ | |
380 | #define AMDGPU_VM_MTYPE_DEFAULT (0 << 5) | |
381 | /* Use NC MTYPE instead of default MTYPE */ | |
382 | #define AMDGPU_VM_MTYPE_NC (1 << 5) | |
383 | /* Use WC MTYPE instead of default MTYPE */ | |
384 | #define AMDGPU_VM_MTYPE_WC (2 << 5) | |
385 | /* Use CC MTYPE instead of default MTYPE */ | |
386 | #define AMDGPU_VM_MTYPE_CC (3 << 5) | |
387 | /* Use UC MTYPE instead of default MTYPE */ | |
388 | #define AMDGPU_VM_MTYPE_UC (4 << 5) | |
81629cba | 389 | |
34b5f6a6 | 390 | struct drm_amdgpu_gem_va { |
675da0dd | 391 | /** GEM object handle */ |
2ce9dde0 MR |
392 | __u32 handle; |
393 | __u32 _pad; | |
675da0dd | 394 | /** AMDGPU_VA_OP_* */ |
2ce9dde0 | 395 | __u32 operation; |
675da0dd | 396 | /** AMDGPU_VM_PAGE_* */ |
2ce9dde0 | 397 | __u32 flags; |
675da0dd | 398 | /** va address to assign . Must be correctly aligned.*/ |
2ce9dde0 | 399 | __u64 va_address; |
675da0dd | 400 | /** Specify offset inside of BO to assign. Must be correctly aligned.*/ |
2ce9dde0 | 401 | __u64 offset_in_bo; |
675da0dd | 402 | /** Specify mapping size. Must be correctly aligned. */ |
2ce9dde0 | 403 | __u64 map_size; |
81629cba AD |
404 | }; |
405 | ||
81629cba AD |
406 | #define AMDGPU_HW_IP_GFX 0 |
407 | #define AMDGPU_HW_IP_COMPUTE 1 | |
408 | #define AMDGPU_HW_IP_DMA 2 | |
409 | #define AMDGPU_HW_IP_UVD 3 | |
410 | #define AMDGPU_HW_IP_VCE 4 | |
a50798b6 LL |
411 | #define AMDGPU_HW_IP_UVD_ENC 5 |
412 | #define AMDGPU_HW_IP_NUM 6 | |
81629cba AD |
413 | |
414 | #define AMDGPU_HW_IP_INSTANCE_MAX_COUNT 1 | |
415 | ||
416 | #define AMDGPU_CHUNK_ID_IB 0x01 | |
417 | #define AMDGPU_CHUNK_ID_FENCE 0x02 | |
2b48d323 | 418 | #define AMDGPU_CHUNK_ID_DEPENDENCIES 0x03 |
675da0dd | 419 | |
81629cba | 420 | struct drm_amdgpu_cs_chunk { |
2ce9dde0 MR |
421 | __u32 chunk_id; |
422 | __u32 length_dw; | |
423 | __u64 chunk_data; | |
81629cba AD |
424 | }; |
425 | ||
426 | struct drm_amdgpu_cs_in { | |
427 | /** Rendering context id */ | |
2ce9dde0 | 428 | __u32 ctx_id; |
81629cba | 429 | /** Handle of resource list associated with CS */ |
2ce9dde0 MR |
430 | __u32 bo_list_handle; |
431 | __u32 num_chunks; | |
432 | __u32 _pad; | |
433 | /** this points to __u64 * which point to cs chunks */ | |
434 | __u64 chunks; | |
81629cba AD |
435 | }; |
436 | ||
437 | struct drm_amdgpu_cs_out { | |
2ce9dde0 | 438 | __u64 handle; |
81629cba AD |
439 | }; |
440 | ||
441 | union drm_amdgpu_cs { | |
675da0dd CK |
442 | struct drm_amdgpu_cs_in in; |
443 | struct drm_amdgpu_cs_out out; | |
81629cba AD |
444 | }; |
445 | ||
446 | /* Specify flags to be used for IB */ | |
447 | ||
448 | /* This IB should be submitted to CE */ | |
449 | #define AMDGPU_IB_FLAG_CE (1<<0) | |
450 | ||
ed834af2 | 451 | /* Preamble flag, which means the IB could be dropped if no context switch */ |
cab6d57c | 452 | #define AMDGPU_IB_FLAG_PREAMBLE (1<<1) |
aa2bdb24 | 453 | |
71aec257 ML |
454 | /* Preempt flag, IB should set Pre_enb bit if PREEMPT flag detected */ |
455 | #define AMDGPU_IB_FLAG_PREEMPT (1<<2) | |
456 | ||
81629cba | 457 | struct drm_amdgpu_cs_chunk_ib { |
2ce9dde0 | 458 | __u32 _pad; |
675da0dd | 459 | /** AMDGPU_IB_FLAG_* */ |
2ce9dde0 | 460 | __u32 flags; |
675da0dd | 461 | /** Virtual address to begin IB execution */ |
2ce9dde0 | 462 | __u64 va_start; |
675da0dd | 463 | /** Size of submission */ |
2ce9dde0 | 464 | __u32 ib_bytes; |
675da0dd | 465 | /** HW IP to submit to */ |
2ce9dde0 | 466 | __u32 ip_type; |
675da0dd | 467 | /** HW IP index of the same type to submit to */ |
2ce9dde0 | 468 | __u32 ip_instance; |
675da0dd | 469 | /** Ring index to submit to */ |
2ce9dde0 | 470 | __u32 ring; |
81629cba AD |
471 | }; |
472 | ||
2b48d323 | 473 | struct drm_amdgpu_cs_chunk_dep { |
2ce9dde0 MR |
474 | __u32 ip_type; |
475 | __u32 ip_instance; | |
476 | __u32 ring; | |
477 | __u32 ctx_id; | |
478 | __u64 handle; | |
2b48d323 CK |
479 | }; |
480 | ||
81629cba | 481 | struct drm_amdgpu_cs_chunk_fence { |
2ce9dde0 MR |
482 | __u32 handle; |
483 | __u32 offset; | |
81629cba AD |
484 | }; |
485 | ||
486 | struct drm_amdgpu_cs_chunk_data { | |
487 | union { | |
488 | struct drm_amdgpu_cs_chunk_ib ib_data; | |
489 | struct drm_amdgpu_cs_chunk_fence fence_data; | |
490 | }; | |
491 | }; | |
492 | ||
493 | /** | |
494 | * Query h/w info: Flag that this is integrated (a.h.a. fusion) GPU | |
495 | * | |
496 | */ | |
497 | #define AMDGPU_IDS_FLAGS_FUSION 0x1 | |
aafcafa0 | 498 | #define AMDGPU_IDS_FLAGS_PREEMPTION 0x2 |
81629cba AD |
499 | |
500 | /* indicate if acceleration can be working */ | |
501 | #define AMDGPU_INFO_ACCEL_WORKING 0x00 | |
502 | /* get the crtc_id from the mode object id? */ | |
503 | #define AMDGPU_INFO_CRTC_FROM_ID 0x01 | |
504 | /* query hw IP info */ | |
505 | #define AMDGPU_INFO_HW_IP_INFO 0x02 | |
506 | /* query hw IP instance count for the specified type */ | |
507 | #define AMDGPU_INFO_HW_IP_COUNT 0x03 | |
508 | /* timestamp for GL_ARB_timer_query */ | |
509 | #define AMDGPU_INFO_TIMESTAMP 0x05 | |
510 | /* Query the firmware version */ | |
511 | #define AMDGPU_INFO_FW_VERSION 0x0e | |
512 | /* Subquery id: Query VCE firmware version */ | |
513 | #define AMDGPU_INFO_FW_VCE 0x1 | |
514 | /* Subquery id: Query UVD firmware version */ | |
515 | #define AMDGPU_INFO_FW_UVD 0x2 | |
516 | /* Subquery id: Query GMC firmware version */ | |
517 | #define AMDGPU_INFO_FW_GMC 0x03 | |
518 | /* Subquery id: Query GFX ME firmware version */ | |
519 | #define AMDGPU_INFO_FW_GFX_ME 0x04 | |
520 | /* Subquery id: Query GFX PFP firmware version */ | |
521 | #define AMDGPU_INFO_FW_GFX_PFP 0x05 | |
522 | /* Subquery id: Query GFX CE firmware version */ | |
523 | #define AMDGPU_INFO_FW_GFX_CE 0x06 | |
524 | /* Subquery id: Query GFX RLC firmware version */ | |
525 | #define AMDGPU_INFO_FW_GFX_RLC 0x07 | |
526 | /* Subquery id: Query GFX MEC firmware version */ | |
527 | #define AMDGPU_INFO_FW_GFX_MEC 0x08 | |
528 | /* Subquery id: Query SMC firmware version */ | |
529 | #define AMDGPU_INFO_FW_SMC 0x0a | |
530 | /* Subquery id: Query SDMA firmware version */ | |
531 | #define AMDGPU_INFO_FW_SDMA 0x0b | |
6a7ed07e HR |
532 | /* Subquery id: Query PSP SOS firmware version */ |
533 | #define AMDGPU_INFO_FW_SOS 0x0c | |
534 | /* Subquery id: Query PSP ASD firmware version */ | |
535 | #define AMDGPU_INFO_FW_ASD 0x0d | |
81629cba AD |
536 | /* number of bytes moved for TTM migration */ |
537 | #define AMDGPU_INFO_NUM_BYTES_MOVED 0x0f | |
538 | /* the used VRAM size */ | |
539 | #define AMDGPU_INFO_VRAM_USAGE 0x10 | |
540 | /* the used GTT size */ | |
541 | #define AMDGPU_INFO_GTT_USAGE 0x11 | |
542 | /* Information about GDS, etc. resource configuration */ | |
543 | #define AMDGPU_INFO_GDS_CONFIG 0x13 | |
544 | /* Query information about VRAM and GTT domains */ | |
545 | #define AMDGPU_INFO_VRAM_GTT 0x14 | |
546 | /* Query information about register in MMR address space*/ | |
547 | #define AMDGPU_INFO_READ_MMR_REG 0x15 | |
548 | /* Query information about device: rev id, family, etc. */ | |
549 | #define AMDGPU_INFO_DEV_INFO 0x16 | |
550 | /* visible vram usage */ | |
551 | #define AMDGPU_INFO_VIS_VRAM_USAGE 0x17 | |
83a59b63 MO |
552 | /* number of TTM buffer evictions */ |
553 | #define AMDGPU_INFO_NUM_EVICTIONS 0x18 | |
e0adf6c8 JZ |
554 | /* Query memory about VRAM and GTT domains */ |
555 | #define AMDGPU_INFO_MEMORY 0x19 | |
bbe87974 AD |
556 | /* Query vce clock table */ |
557 | #define AMDGPU_INFO_VCE_CLOCK_TABLE 0x1A | |
40ee5888 EQ |
558 | /* Query vbios related information */ |
559 | #define AMDGPU_INFO_VBIOS 0x1B | |
560 | /* Subquery id: Query vbios size */ | |
561 | #define AMDGPU_INFO_VBIOS_SIZE 0x1 | |
562 | /* Subquery id: Query vbios image */ | |
563 | #define AMDGPU_INFO_VBIOS_IMAGE 0x2 | |
44879b62 AN |
564 | /* Query UVD handles */ |
565 | #define AMDGPU_INFO_NUM_HANDLES 0x1C | |
5ebbac4b AD |
566 | /* Query sensor related information */ |
567 | #define AMDGPU_INFO_SENSOR 0x1D | |
568 | /* Subquery id: Query GPU shader clock */ | |
569 | #define AMDGPU_INFO_SENSOR_GFX_SCLK 0x1 | |
570 | /* Subquery id: Query GPU memory clock */ | |
571 | #define AMDGPU_INFO_SENSOR_GFX_MCLK 0x2 | |
572 | /* Subquery id: Query GPU temperature */ | |
573 | #define AMDGPU_INFO_SENSOR_GPU_TEMP 0x3 | |
574 | /* Subquery id: Query GPU load */ | |
575 | #define AMDGPU_INFO_SENSOR_GPU_LOAD 0x4 | |
576 | /* Subquery id: Query average GPU power */ | |
577 | #define AMDGPU_INFO_SENSOR_GPU_AVG_POWER 0x5 | |
578 | /* Subquery id: Query northbridge voltage */ | |
579 | #define AMDGPU_INFO_SENSOR_VDDNB 0x6 | |
580 | /* Subquery id: Query graphics voltage */ | |
581 | #define AMDGPU_INFO_SENSOR_VDDGFX 0x7 | |
81629cba AD |
582 | |
583 | #define AMDGPU_INFO_MMR_SE_INDEX_SHIFT 0 | |
584 | #define AMDGPU_INFO_MMR_SE_INDEX_MASK 0xff | |
585 | #define AMDGPU_INFO_MMR_SH_INDEX_SHIFT 8 | |
586 | #define AMDGPU_INFO_MMR_SH_INDEX_MASK 0xff | |
587 | ||
000cab9a HR |
588 | struct drm_amdgpu_query_fw { |
589 | /** AMDGPU_INFO_FW_* */ | |
590 | __u32 fw_type; | |
591 | /** | |
592 | * Index of the IP if there are more IPs of | |
593 | * the same type. | |
594 | */ | |
595 | __u32 ip_instance; | |
596 | /** | |
597 | * Index of the engine. Whether this is used depends | |
598 | * on the firmware type. (e.g. MEC, SDMA) | |
599 | */ | |
600 | __u32 index; | |
601 | __u32 _pad; | |
602 | }; | |
603 | ||
81629cba AD |
604 | /* Input structure for the INFO ioctl */ |
605 | struct drm_amdgpu_info { | |
606 | /* Where the return value will be stored */ | |
2ce9dde0 | 607 | __u64 return_pointer; |
81629cba AD |
608 | /* The size of the return value. Just like "size" in "snprintf", |
609 | * it limits how many bytes the kernel can write. */ | |
2ce9dde0 | 610 | __u32 return_size; |
81629cba | 611 | /* The query request id. */ |
2ce9dde0 | 612 | __u32 query; |
81629cba AD |
613 | |
614 | union { | |
615 | struct { | |
2ce9dde0 MR |
616 | __u32 id; |
617 | __u32 _pad; | |
81629cba AD |
618 | } mode_crtc; |
619 | ||
620 | struct { | |
621 | /** AMDGPU_HW_IP_* */ | |
2ce9dde0 | 622 | __u32 type; |
81629cba | 623 | /** |
675da0dd CK |
624 | * Index of the IP if there are more IPs of the same |
625 | * type. Ignored by AMDGPU_INFO_HW_IP_COUNT. | |
81629cba | 626 | */ |
2ce9dde0 | 627 | __u32 ip_instance; |
81629cba AD |
628 | } query_hw_ip; |
629 | ||
630 | struct { | |
2ce9dde0 | 631 | __u32 dword_offset; |
675da0dd | 632 | /** number of registers to read */ |
2ce9dde0 MR |
633 | __u32 count; |
634 | __u32 instance; | |
675da0dd | 635 | /** For future use, no flags defined so far */ |
2ce9dde0 | 636 | __u32 flags; |
81629cba AD |
637 | } read_mmr_reg; |
638 | ||
000cab9a | 639 | struct drm_amdgpu_query_fw query_fw; |
40ee5888 EQ |
640 | |
641 | struct { | |
642 | __u32 type; | |
643 | __u32 offset; | |
644 | } vbios_info; | |
5ebbac4b AD |
645 | |
646 | struct { | |
647 | __u32 type; | |
648 | } sensor_info; | |
81629cba AD |
649 | }; |
650 | }; | |
651 | ||
652 | struct drm_amdgpu_info_gds { | |
653 | /** GDS GFX partition size */ | |
2ce9dde0 | 654 | __u32 gds_gfx_partition_size; |
81629cba | 655 | /** GDS compute partition size */ |
2ce9dde0 | 656 | __u32 compute_partition_size; |
81629cba | 657 | /** total GDS memory size */ |
2ce9dde0 | 658 | __u32 gds_total_size; |
81629cba | 659 | /** GWS size per GFX partition */ |
2ce9dde0 | 660 | __u32 gws_per_gfx_partition; |
81629cba | 661 | /** GSW size per compute partition */ |
2ce9dde0 | 662 | __u32 gws_per_compute_partition; |
81629cba | 663 | /** OA size per GFX partition */ |
2ce9dde0 | 664 | __u32 oa_per_gfx_partition; |
81629cba | 665 | /** OA size per compute partition */ |
2ce9dde0 MR |
666 | __u32 oa_per_compute_partition; |
667 | __u32 _pad; | |
81629cba AD |
668 | }; |
669 | ||
670 | struct drm_amdgpu_info_vram_gtt { | |
2ce9dde0 MR |
671 | __u64 vram_size; |
672 | __u64 vram_cpu_accessible_size; | |
673 | __u64 gtt_size; | |
81629cba AD |
674 | }; |
675 | ||
e0adf6c8 JZ |
676 | struct drm_amdgpu_heap_info { |
677 | /** max. physical memory */ | |
678 | __u64 total_heap_size; | |
679 | ||
680 | /** Theoretical max. available memory in the given heap */ | |
681 | __u64 usable_heap_size; | |
682 | ||
683 | /** | |
684 | * Number of bytes allocated in the heap. This includes all processes | |
685 | * and private allocations in the kernel. It changes when new buffers | |
686 | * are allocated, freed, and moved. It cannot be larger than | |
687 | * heap_size. | |
688 | */ | |
689 | __u64 heap_usage; | |
690 | ||
691 | /** | |
692 | * Theoretical possible max. size of buffer which | |
693 | * could be allocated in the given heap | |
694 | */ | |
695 | __u64 max_allocation; | |
9f6163e7 JZ |
696 | }; |
697 | ||
e0adf6c8 JZ |
698 | struct drm_amdgpu_memory_info { |
699 | struct drm_amdgpu_heap_info vram; | |
700 | struct drm_amdgpu_heap_info cpu_accessible_vram; | |
701 | struct drm_amdgpu_heap_info gtt; | |
cfa32556 JZ |
702 | }; |
703 | ||
81629cba | 704 | struct drm_amdgpu_info_firmware { |
2ce9dde0 MR |
705 | __u32 ver; |
706 | __u32 feature; | |
81629cba AD |
707 | }; |
708 | ||
81c59f54 KW |
709 | #define AMDGPU_VRAM_TYPE_UNKNOWN 0 |
710 | #define AMDGPU_VRAM_TYPE_GDDR1 1 | |
711 | #define AMDGPU_VRAM_TYPE_DDR2 2 | |
712 | #define AMDGPU_VRAM_TYPE_GDDR3 3 | |
713 | #define AMDGPU_VRAM_TYPE_GDDR4 4 | |
714 | #define AMDGPU_VRAM_TYPE_GDDR5 5 | |
715 | #define AMDGPU_VRAM_TYPE_HBM 6 | |
716 | #define AMDGPU_VRAM_TYPE_DDR3 7 | |
717 | ||
81629cba AD |
718 | struct drm_amdgpu_info_device { |
719 | /** PCI Device ID */ | |
2ce9dde0 | 720 | __u32 device_id; |
81629cba | 721 | /** Internal chip revision: A0, A1, etc.) */ |
2ce9dde0 MR |
722 | __u32 chip_rev; |
723 | __u32 external_rev; | |
81629cba | 724 | /** Revision id in PCI Config space */ |
2ce9dde0 MR |
725 | __u32 pci_rev; |
726 | __u32 family; | |
727 | __u32 num_shader_engines; | |
728 | __u32 num_shader_arrays_per_engine; | |
675da0dd | 729 | /* in KHz */ |
2ce9dde0 MR |
730 | __u32 gpu_counter_freq; |
731 | __u64 max_engine_clock; | |
732 | __u64 max_memory_clock; | |
81629cba | 733 | /* cu information */ |
2ce9dde0 MR |
734 | __u32 cu_active_number; |
735 | __u32 cu_ao_mask; | |
736 | __u32 cu_bitmap[4][4]; | |
81629cba | 737 | /** Render backend pipe mask. One render backend is CB+DB. */ |
2ce9dde0 MR |
738 | __u32 enabled_rb_pipes_mask; |
739 | __u32 num_rb_pipes; | |
740 | __u32 num_hw_gfx_contexts; | |
741 | __u32 _pad; | |
742 | __u64 ids_flags; | |
81629cba | 743 | /** Starting virtual address for UMDs. */ |
2ce9dde0 | 744 | __u64 virtual_address_offset; |
02b70c8c | 745 | /** The maximum virtual address */ |
2ce9dde0 | 746 | __u64 virtual_address_max; |
81629cba | 747 | /** Required alignment of virtual addresses. */ |
2ce9dde0 | 748 | __u32 virtual_address_alignment; |
81629cba | 749 | /** Page table entry - fragment size */ |
2ce9dde0 MR |
750 | __u32 pte_fragment_size; |
751 | __u32 gart_page_size; | |
a101a899 | 752 | /** constant engine ram size*/ |
2ce9dde0 | 753 | __u32 ce_ram_size; |
cab6d57c | 754 | /** video memory type info*/ |
2ce9dde0 | 755 | __u32 vram_type; |
81c59f54 | 756 | /** video memory bit width*/ |
2ce9dde0 | 757 | __u32 vram_bit_width; |
fa92754e | 758 | /* vce harvesting instance */ |
2ce9dde0 | 759 | __u32 vce_harvest_config; |
df6e2c4a JZ |
760 | /* gfx double offchip LDS buffers */ |
761 | __u32 gc_double_offchip_lds_buf; | |
bce23e00 AD |
762 | /* NGG Primitive Buffer */ |
763 | __u64 prim_buf_gpu_addr; | |
764 | /* NGG Position Buffer */ | |
765 | __u64 pos_buf_gpu_addr; | |
766 | /* NGG Control Sideband */ | |
767 | __u64 cntl_sb_buf_gpu_addr; | |
768 | /* NGG Parameter Cache */ | |
769 | __u64 param_buf_gpu_addr; | |
408bfe7c JZ |
770 | __u32 prim_buf_size; |
771 | __u32 pos_buf_size; | |
772 | __u32 cntl_sb_buf_size; | |
773 | __u32 param_buf_size; | |
774 | /* wavefront size*/ | |
775 | __u32 wave_front_size; | |
776 | /* shader visible vgprs*/ | |
777 | __u32 num_shader_visible_vgprs; | |
778 | /* CU per shader array*/ | |
779 | __u32 num_cu_per_sh; | |
780 | /* number of tcc blocks*/ | |
781 | __u32 num_tcc_blocks; | |
782 | /* gs vgt table depth*/ | |
783 | __u32 gs_vgt_table_depth; | |
784 | /* gs primitive buffer depth*/ | |
785 | __u32 gs_prim_buffer_depth; | |
786 | /* max gs wavefront per vgt*/ | |
787 | __u32 max_gs_waves_per_vgt; | |
788 | __u32 _pad1; | |
81629cba AD |
789 | }; |
790 | ||
791 | struct drm_amdgpu_info_hw_ip { | |
792 | /** Version of h/w IP */ | |
2ce9dde0 MR |
793 | __u32 hw_ip_version_major; |
794 | __u32 hw_ip_version_minor; | |
81629cba | 795 | /** Capabilities */ |
2ce9dde0 | 796 | __u64 capabilities_flags; |
71062f43 | 797 | /** command buffer address start alignment*/ |
2ce9dde0 | 798 | __u32 ib_start_alignment; |
71062f43 | 799 | /** command buffer size alignment*/ |
2ce9dde0 | 800 | __u32 ib_size_alignment; |
81629cba | 801 | /** Bitmask of available rings. Bit 0 means ring 0, etc. */ |
2ce9dde0 MR |
802 | __u32 available_rings; |
803 | __u32 _pad; | |
81629cba AD |
804 | }; |
805 | ||
44879b62 AN |
806 | struct drm_amdgpu_info_num_handles { |
807 | /** Max handles as supported by firmware for UVD */ | |
808 | __u32 uvd_max_handles; | |
809 | /** Handles currently in use for UVD */ | |
810 | __u32 uvd_used_handles; | |
811 | }; | |
812 | ||
bbe87974 AD |
813 | #define AMDGPU_VCE_CLOCK_TABLE_ENTRIES 6 |
814 | ||
815 | struct drm_amdgpu_info_vce_clock_table_entry { | |
816 | /** System clock */ | |
817 | __u32 sclk; | |
818 | /** Memory clock */ | |
819 | __u32 mclk; | |
820 | /** VCE clock */ | |
821 | __u32 eclk; | |
822 | __u32 pad; | |
823 | }; | |
824 | ||
825 | struct drm_amdgpu_info_vce_clock_table { | |
826 | struct drm_amdgpu_info_vce_clock_table_entry entries[AMDGPU_VCE_CLOCK_TABLE_ENTRIES]; | |
827 | __u32 num_valid_entries; | |
828 | __u32 pad; | |
829 | }; | |
830 | ||
81629cba AD |
831 | /* |
832 | * Supported GPU families | |
833 | */ | |
834 | #define AMDGPU_FAMILY_UNKNOWN 0 | |
295d0daf | 835 | #define AMDGPU_FAMILY_SI 110 /* Hainan, Oland, Verde, Pitcairn, Tahiti */ |
81629cba AD |
836 | #define AMDGPU_FAMILY_CI 120 /* Bonaire, Hawaii */ |
837 | #define AMDGPU_FAMILY_KV 125 /* Kaveri, Kabini, Mullins */ | |
838 | #define AMDGPU_FAMILY_VI 130 /* Iceland, Tonga */ | |
39bb0c92 | 839 | #define AMDGPU_FAMILY_CZ 135 /* Carrizo, Stoney */ |
a8f1f1ce | 840 | #define AMDGPU_FAMILY_AI 141 /* Vega10 */ |
81629cba | 841 | |
cfa7152f EV |
842 | #if defined(__cplusplus) |
843 | } | |
844 | #endif | |
845 | ||
81629cba | 846 | #endif |