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81629cba AD |
1 | /* amdgpu_drm.h -- Public header for the amdgpu driver -*- linux-c -*- |
2 | * | |
3 | * Copyright 2000 Precision Insight, Inc., Cedar Park, Texas. | |
4 | * Copyright 2000 VA Linux Systems, Inc., Fremont, California. | |
5 | * Copyright 2002 Tungsten Graphics, Inc., Cedar Park, Texas. | |
6 | * Copyright 2014 Advanced Micro Devices, Inc. | |
7 | * | |
8 | * Permission is hereby granted, free of charge, to any person obtaining a | |
9 | * copy of this software and associated documentation files (the "Software"), | |
10 | * to deal in the Software without restriction, including without limitation | |
11 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
12 | * and/or sell copies of the Software, and to permit persons to whom the | |
13 | * Software is furnished to do so, subject to the following conditions: | |
14 | * | |
15 | * The above copyright notice and this permission notice shall be included in | |
16 | * all copies or substantial portions of the Software. | |
17 | * | |
18 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
19 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
20 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
21 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR | |
22 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, | |
23 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR | |
24 | * OTHER DEALINGS IN THE SOFTWARE. | |
25 | * | |
26 | * Authors: | |
27 | * Kevin E. Martin <martin@valinux.com> | |
28 | * Gareth Hughes <gareth@valinux.com> | |
29 | * Keith Whitwell <keith@tungstengraphics.com> | |
30 | */ | |
31 | ||
32 | #ifndef __AMDGPU_DRM_H__ | |
33 | #define __AMDGPU_DRM_H__ | |
34 | ||
b3fcf36a | 35 | #include "drm.h" |
81629cba | 36 | |
cfa7152f EV |
37 | #if defined(__cplusplus) |
38 | extern "C" { | |
39 | #endif | |
40 | ||
81629cba AD |
41 | #define DRM_AMDGPU_GEM_CREATE 0x00 |
42 | #define DRM_AMDGPU_GEM_MMAP 0x01 | |
43 | #define DRM_AMDGPU_CTX 0x02 | |
44 | #define DRM_AMDGPU_BO_LIST 0x03 | |
45 | #define DRM_AMDGPU_CS 0x04 | |
46 | #define DRM_AMDGPU_INFO 0x05 | |
47 | #define DRM_AMDGPU_GEM_METADATA 0x06 | |
48 | #define DRM_AMDGPU_GEM_WAIT_IDLE 0x07 | |
49 | #define DRM_AMDGPU_GEM_VA 0x08 | |
50 | #define DRM_AMDGPU_WAIT_CS 0x09 | |
51 | #define DRM_AMDGPU_GEM_OP 0x10 | |
52 | #define DRM_AMDGPU_GEM_USERPTR 0x11 | |
53 | ||
54 | #define DRM_IOCTL_AMDGPU_GEM_CREATE DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_CREATE, union drm_amdgpu_gem_create) | |
55 | #define DRM_IOCTL_AMDGPU_GEM_MMAP DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_MMAP, union drm_amdgpu_gem_mmap) | |
56 | #define DRM_IOCTL_AMDGPU_CTX DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_CTX, union drm_amdgpu_ctx) | |
57 | #define DRM_IOCTL_AMDGPU_BO_LIST DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_BO_LIST, union drm_amdgpu_bo_list) | |
58 | #define DRM_IOCTL_AMDGPU_CS DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_CS, union drm_amdgpu_cs) | |
59 | #define DRM_IOCTL_AMDGPU_INFO DRM_IOW(DRM_COMMAND_BASE + DRM_AMDGPU_INFO, struct drm_amdgpu_info) | |
60 | #define DRM_IOCTL_AMDGPU_GEM_METADATA DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_METADATA, struct drm_amdgpu_gem_metadata) | |
61 | #define DRM_IOCTL_AMDGPU_GEM_WAIT_IDLE DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_WAIT_IDLE, union drm_amdgpu_gem_wait_idle) | |
34b5f6a6 | 62 | #define DRM_IOCTL_AMDGPU_GEM_VA DRM_IOW(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_VA, struct drm_amdgpu_gem_va) |
81629cba AD |
63 | #define DRM_IOCTL_AMDGPU_WAIT_CS DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_WAIT_CS, union drm_amdgpu_wait_cs) |
64 | #define DRM_IOCTL_AMDGPU_GEM_OP DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_OP, struct drm_amdgpu_gem_op) | |
65 | #define DRM_IOCTL_AMDGPU_GEM_USERPTR DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_USERPTR, struct drm_amdgpu_gem_userptr) | |
66 | ||
67 | #define AMDGPU_GEM_DOMAIN_CPU 0x1 | |
68 | #define AMDGPU_GEM_DOMAIN_GTT 0x2 | |
69 | #define AMDGPU_GEM_DOMAIN_VRAM 0x4 | |
70 | #define AMDGPU_GEM_DOMAIN_GDS 0x8 | |
71 | #define AMDGPU_GEM_DOMAIN_GWS 0x10 | |
72 | #define AMDGPU_GEM_DOMAIN_OA 0x20 | |
73 | ||
81629cba AD |
74 | /* Flag that CPU access will be required for the case of VRAM domain */ |
75 | #define AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED (1 << 0) | |
76 | /* Flag that CPU access will not work, this VRAM domain is invisible */ | |
77 | #define AMDGPU_GEM_CREATE_NO_CPU_ACCESS (1 << 1) | |
81629cba | 78 | /* Flag that USWC attributes should be used for GTT */ |
88671288 | 79 | #define AMDGPU_GEM_CREATE_CPU_GTT_USWC (1 << 2) |
4fea83ff FC |
80 | /* Flag that the memory should be in VRAM and cleared */ |
81 | #define AMDGPU_GEM_CREATE_VRAM_CLEARED (1 << 3) | |
e7893c4b CZ |
82 | /* Flag that create shadow bo(GTT) while allocating vram bo */ |
83 | #define AMDGPU_GEM_CREATE_SHADOW (1 << 4) | |
03f48dd5 CK |
84 | /* Flag that allocating the BO should use linear VRAM */ |
85 | #define AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS (1 << 5) | |
81629cba | 86 | |
81629cba AD |
87 | struct drm_amdgpu_gem_create_in { |
88 | /** the requested memory size */ | |
2ce9dde0 | 89 | __u64 bo_size; |
81629cba | 90 | /** physical start_addr alignment in bytes for some HW requirements */ |
2ce9dde0 | 91 | __u64 alignment; |
81629cba | 92 | /** the requested memory domains */ |
2ce9dde0 | 93 | __u64 domains; |
81629cba | 94 | /** allocation flags */ |
2ce9dde0 | 95 | __u64 domain_flags; |
81629cba AD |
96 | }; |
97 | ||
98 | struct drm_amdgpu_gem_create_out { | |
99 | /** returned GEM object handle */ | |
2ce9dde0 MR |
100 | __u32 handle; |
101 | __u32 _pad; | |
81629cba AD |
102 | }; |
103 | ||
104 | union drm_amdgpu_gem_create { | |
105 | struct drm_amdgpu_gem_create_in in; | |
106 | struct drm_amdgpu_gem_create_out out; | |
107 | }; | |
108 | ||
109 | /** Opcode to create new residency list. */ | |
110 | #define AMDGPU_BO_LIST_OP_CREATE 0 | |
111 | /** Opcode to destroy previously created residency list */ | |
112 | #define AMDGPU_BO_LIST_OP_DESTROY 1 | |
113 | /** Opcode to update resource information in the list */ | |
114 | #define AMDGPU_BO_LIST_OP_UPDATE 2 | |
115 | ||
116 | struct drm_amdgpu_bo_list_in { | |
117 | /** Type of operation */ | |
2ce9dde0 | 118 | __u32 operation; |
81629cba | 119 | /** Handle of list or 0 if we want to create one */ |
2ce9dde0 | 120 | __u32 list_handle; |
81629cba | 121 | /** Number of BOs in list */ |
2ce9dde0 | 122 | __u32 bo_number; |
81629cba | 123 | /** Size of each element describing BO */ |
2ce9dde0 | 124 | __u32 bo_info_size; |
81629cba | 125 | /** Pointer to array describing BOs */ |
2ce9dde0 | 126 | __u64 bo_info_ptr; |
81629cba AD |
127 | }; |
128 | ||
129 | struct drm_amdgpu_bo_list_entry { | |
130 | /** Handle of BO */ | |
2ce9dde0 | 131 | __u32 bo_handle; |
81629cba | 132 | /** New (if specified) BO priority to be used during migration */ |
2ce9dde0 | 133 | __u32 bo_priority; |
81629cba AD |
134 | }; |
135 | ||
136 | struct drm_amdgpu_bo_list_out { | |
137 | /** Handle of resource list */ | |
2ce9dde0 MR |
138 | __u32 list_handle; |
139 | __u32 _pad; | |
81629cba AD |
140 | }; |
141 | ||
142 | union drm_amdgpu_bo_list { | |
143 | struct drm_amdgpu_bo_list_in in; | |
144 | struct drm_amdgpu_bo_list_out out; | |
145 | }; | |
146 | ||
147 | /* context related */ | |
148 | #define AMDGPU_CTX_OP_ALLOC_CTX 1 | |
149 | #define AMDGPU_CTX_OP_FREE_CTX 2 | |
150 | #define AMDGPU_CTX_OP_QUERY_STATE 3 | |
151 | ||
d94aed5a MO |
152 | /* GPU reset status */ |
153 | #define AMDGPU_CTX_NO_RESET 0 | |
675da0dd CK |
154 | /* this the context caused it */ |
155 | #define AMDGPU_CTX_GUILTY_RESET 1 | |
156 | /* some other context caused it */ | |
157 | #define AMDGPU_CTX_INNOCENT_RESET 2 | |
158 | /* unknown cause */ | |
159 | #define AMDGPU_CTX_UNKNOWN_RESET 3 | |
d94aed5a | 160 | |
81629cba | 161 | struct drm_amdgpu_ctx_in { |
675da0dd | 162 | /** AMDGPU_CTX_OP_* */ |
2ce9dde0 | 163 | __u32 op; |
675da0dd | 164 | /** For future use, no flags defined so far */ |
2ce9dde0 MR |
165 | __u32 flags; |
166 | __u32 ctx_id; | |
167 | __u32 _pad; | |
81629cba AD |
168 | }; |
169 | ||
170 | union drm_amdgpu_ctx_out { | |
171 | struct { | |
2ce9dde0 MR |
172 | __u32 ctx_id; |
173 | __u32 _pad; | |
81629cba AD |
174 | } alloc; |
175 | ||
176 | struct { | |
675da0dd | 177 | /** For future use, no flags defined so far */ |
2ce9dde0 | 178 | __u64 flags; |
d94aed5a | 179 | /** Number of resets caused by this context so far. */ |
2ce9dde0 | 180 | __u32 hangs; |
d94aed5a | 181 | /** Reset status since the last call of the ioctl. */ |
2ce9dde0 | 182 | __u32 reset_status; |
81629cba AD |
183 | } state; |
184 | }; | |
185 | ||
186 | union drm_amdgpu_ctx { | |
187 | struct drm_amdgpu_ctx_in in; | |
188 | union drm_amdgpu_ctx_out out; | |
189 | }; | |
190 | ||
191 | /* | |
192 | * This is not a reliable API and you should expect it to fail for any | |
193 | * number of reasons and have fallback path that do not use userptr to | |
194 | * perform any operation. | |
195 | */ | |
196 | #define AMDGPU_GEM_USERPTR_READONLY (1 << 0) | |
197 | #define AMDGPU_GEM_USERPTR_ANONONLY (1 << 1) | |
198 | #define AMDGPU_GEM_USERPTR_VALIDATE (1 << 2) | |
199 | #define AMDGPU_GEM_USERPTR_REGISTER (1 << 3) | |
200 | ||
201 | struct drm_amdgpu_gem_userptr { | |
2ce9dde0 MR |
202 | __u64 addr; |
203 | __u64 size; | |
675da0dd | 204 | /* AMDGPU_GEM_USERPTR_* */ |
2ce9dde0 | 205 | __u32 flags; |
675da0dd | 206 | /* Resulting GEM handle */ |
2ce9dde0 | 207 | __u32 handle; |
81629cba AD |
208 | }; |
209 | ||
fbd76d59 MO |
210 | /* same meaning as the GB_TILE_MODE and GL_MACRO_TILE_MODE fields */ |
211 | #define AMDGPU_TILING_ARRAY_MODE_SHIFT 0 | |
212 | #define AMDGPU_TILING_ARRAY_MODE_MASK 0xf | |
213 | #define AMDGPU_TILING_PIPE_CONFIG_SHIFT 4 | |
214 | #define AMDGPU_TILING_PIPE_CONFIG_MASK 0x1f | |
215 | #define AMDGPU_TILING_TILE_SPLIT_SHIFT 9 | |
216 | #define AMDGPU_TILING_TILE_SPLIT_MASK 0x7 | |
217 | #define AMDGPU_TILING_MICRO_TILE_MODE_SHIFT 12 | |
218 | #define AMDGPU_TILING_MICRO_TILE_MODE_MASK 0x7 | |
219 | #define AMDGPU_TILING_BANK_WIDTH_SHIFT 15 | |
220 | #define AMDGPU_TILING_BANK_WIDTH_MASK 0x3 | |
221 | #define AMDGPU_TILING_BANK_HEIGHT_SHIFT 17 | |
222 | #define AMDGPU_TILING_BANK_HEIGHT_MASK 0x3 | |
223 | #define AMDGPU_TILING_MACRO_TILE_ASPECT_SHIFT 19 | |
224 | #define AMDGPU_TILING_MACRO_TILE_ASPECT_MASK 0x3 | |
225 | #define AMDGPU_TILING_NUM_BANKS_SHIFT 21 | |
226 | #define AMDGPU_TILING_NUM_BANKS_MASK 0x3 | |
227 | ||
228 | #define AMDGPU_TILING_SET(field, value) \ | |
229 | (((value) & AMDGPU_TILING_##field##_MASK) << AMDGPU_TILING_##field##_SHIFT) | |
230 | #define AMDGPU_TILING_GET(value, field) \ | |
231 | (((value) >> AMDGPU_TILING_##field##_SHIFT) & AMDGPU_TILING_##field##_MASK) | |
81629cba AD |
232 | |
233 | #define AMDGPU_GEM_METADATA_OP_SET_METADATA 1 | |
234 | #define AMDGPU_GEM_METADATA_OP_GET_METADATA 2 | |
235 | ||
236 | /** The same structure is shared for input/output */ | |
237 | struct drm_amdgpu_gem_metadata { | |
675da0dd | 238 | /** GEM Object handle */ |
2ce9dde0 | 239 | __u32 handle; |
675da0dd | 240 | /** Do we want get or set metadata */ |
2ce9dde0 | 241 | __u32 op; |
81629cba | 242 | struct { |
675da0dd | 243 | /** For future use, no flags defined so far */ |
2ce9dde0 | 244 | __u64 flags; |
675da0dd | 245 | /** family specific tiling info */ |
2ce9dde0 MR |
246 | __u64 tiling_info; |
247 | __u32 data_size_bytes; | |
248 | __u32 data[64]; | |
81629cba AD |
249 | } data; |
250 | }; | |
251 | ||
252 | struct drm_amdgpu_gem_mmap_in { | |
675da0dd | 253 | /** the GEM object handle */ |
2ce9dde0 MR |
254 | __u32 handle; |
255 | __u32 _pad; | |
81629cba AD |
256 | }; |
257 | ||
258 | struct drm_amdgpu_gem_mmap_out { | |
675da0dd | 259 | /** mmap offset from the vma offset manager */ |
2ce9dde0 | 260 | __u64 addr_ptr; |
81629cba AD |
261 | }; |
262 | ||
263 | union drm_amdgpu_gem_mmap { | |
264 | struct drm_amdgpu_gem_mmap_in in; | |
265 | struct drm_amdgpu_gem_mmap_out out; | |
266 | }; | |
267 | ||
268 | struct drm_amdgpu_gem_wait_idle_in { | |
675da0dd | 269 | /** GEM object handle */ |
2ce9dde0 | 270 | __u32 handle; |
675da0dd | 271 | /** For future use, no flags defined so far */ |
2ce9dde0 | 272 | __u32 flags; |
675da0dd | 273 | /** Absolute timeout to wait */ |
2ce9dde0 | 274 | __u64 timeout; |
81629cba AD |
275 | }; |
276 | ||
277 | struct drm_amdgpu_gem_wait_idle_out { | |
675da0dd | 278 | /** BO status: 0 - BO is idle, 1 - BO is busy */ |
2ce9dde0 | 279 | __u32 status; |
675da0dd | 280 | /** Returned current memory domain */ |
2ce9dde0 | 281 | __u32 domain; |
81629cba AD |
282 | }; |
283 | ||
284 | union drm_amdgpu_gem_wait_idle { | |
285 | struct drm_amdgpu_gem_wait_idle_in in; | |
286 | struct drm_amdgpu_gem_wait_idle_out out; | |
287 | }; | |
288 | ||
289 | struct drm_amdgpu_wait_cs_in { | |
675da0dd | 290 | /** Command submission handle */ |
2ce9dde0 | 291 | __u64 handle; |
675da0dd | 292 | /** Absolute timeout to wait */ |
2ce9dde0 MR |
293 | __u64 timeout; |
294 | __u32 ip_type; | |
295 | __u32 ip_instance; | |
296 | __u32 ring; | |
297 | __u32 ctx_id; | |
81629cba AD |
298 | }; |
299 | ||
300 | struct drm_amdgpu_wait_cs_out { | |
675da0dd | 301 | /** CS status: 0 - CS completed, 1 - CS still busy */ |
2ce9dde0 | 302 | __u64 status; |
81629cba AD |
303 | }; |
304 | ||
305 | union drm_amdgpu_wait_cs { | |
306 | struct drm_amdgpu_wait_cs_in in; | |
307 | struct drm_amdgpu_wait_cs_out out; | |
308 | }; | |
309 | ||
675da0dd CK |
310 | #define AMDGPU_GEM_OP_GET_GEM_CREATE_INFO 0 |
311 | #define AMDGPU_GEM_OP_SET_PLACEMENT 1 | |
312 | ||
81629cba AD |
313 | /* Sets or returns a value associated with a buffer. */ |
314 | struct drm_amdgpu_gem_op { | |
675da0dd | 315 | /** GEM object handle */ |
2ce9dde0 | 316 | __u32 handle; |
675da0dd | 317 | /** AMDGPU_GEM_OP_* */ |
2ce9dde0 | 318 | __u32 op; |
675da0dd | 319 | /** Input or return value */ |
2ce9dde0 | 320 | __u64 value; |
81629cba AD |
321 | }; |
322 | ||
81629cba AD |
323 | #define AMDGPU_VA_OP_MAP 1 |
324 | #define AMDGPU_VA_OP_UNMAP 2 | |
325 | ||
fc220f65 CK |
326 | /* Delay the page table update till the next CS */ |
327 | #define AMDGPU_VM_DELAY_UPDATE (1 << 0) | |
328 | ||
81629cba AD |
329 | /* Mapping flags */ |
330 | /* readable mapping */ | |
331 | #define AMDGPU_VM_PAGE_READABLE (1 << 1) | |
332 | /* writable mapping */ | |
333 | #define AMDGPU_VM_PAGE_WRITEABLE (1 << 2) | |
334 | /* executable mapping, new for VI */ | |
335 | #define AMDGPU_VM_PAGE_EXECUTABLE (1 << 3) | |
336 | ||
34b5f6a6 | 337 | struct drm_amdgpu_gem_va { |
675da0dd | 338 | /** GEM object handle */ |
2ce9dde0 MR |
339 | __u32 handle; |
340 | __u32 _pad; | |
675da0dd | 341 | /** AMDGPU_VA_OP_* */ |
2ce9dde0 | 342 | __u32 operation; |
675da0dd | 343 | /** AMDGPU_VM_PAGE_* */ |
2ce9dde0 | 344 | __u32 flags; |
675da0dd | 345 | /** va address to assign . Must be correctly aligned.*/ |
2ce9dde0 | 346 | __u64 va_address; |
675da0dd | 347 | /** Specify offset inside of BO to assign. Must be correctly aligned.*/ |
2ce9dde0 | 348 | __u64 offset_in_bo; |
675da0dd | 349 | /** Specify mapping size. Must be correctly aligned. */ |
2ce9dde0 | 350 | __u64 map_size; |
81629cba AD |
351 | }; |
352 | ||
81629cba AD |
353 | #define AMDGPU_HW_IP_GFX 0 |
354 | #define AMDGPU_HW_IP_COMPUTE 1 | |
355 | #define AMDGPU_HW_IP_DMA 2 | |
356 | #define AMDGPU_HW_IP_UVD 3 | |
357 | #define AMDGPU_HW_IP_VCE 4 | |
358 | #define AMDGPU_HW_IP_NUM 5 | |
359 | ||
360 | #define AMDGPU_HW_IP_INSTANCE_MAX_COUNT 1 | |
361 | ||
362 | #define AMDGPU_CHUNK_ID_IB 0x01 | |
363 | #define AMDGPU_CHUNK_ID_FENCE 0x02 | |
2b48d323 | 364 | #define AMDGPU_CHUNK_ID_DEPENDENCIES 0x03 |
675da0dd | 365 | |
81629cba | 366 | struct drm_amdgpu_cs_chunk { |
2ce9dde0 MR |
367 | __u32 chunk_id; |
368 | __u32 length_dw; | |
369 | __u64 chunk_data; | |
81629cba AD |
370 | }; |
371 | ||
372 | struct drm_amdgpu_cs_in { | |
373 | /** Rendering context id */ | |
2ce9dde0 | 374 | __u32 ctx_id; |
81629cba | 375 | /** Handle of resource list associated with CS */ |
2ce9dde0 MR |
376 | __u32 bo_list_handle; |
377 | __u32 num_chunks; | |
378 | __u32 _pad; | |
379 | /** this points to __u64 * which point to cs chunks */ | |
380 | __u64 chunks; | |
81629cba AD |
381 | }; |
382 | ||
383 | struct drm_amdgpu_cs_out { | |
2ce9dde0 | 384 | __u64 handle; |
81629cba AD |
385 | }; |
386 | ||
387 | union drm_amdgpu_cs { | |
675da0dd CK |
388 | struct drm_amdgpu_cs_in in; |
389 | struct drm_amdgpu_cs_out out; | |
81629cba AD |
390 | }; |
391 | ||
392 | /* Specify flags to be used for IB */ | |
393 | ||
394 | /* This IB should be submitted to CE */ | |
395 | #define AMDGPU_IB_FLAG_CE (1<<0) | |
396 | ||
aa2bdb24 | 397 | /* CE Preamble */ |
cab6d57c | 398 | #define AMDGPU_IB_FLAG_PREAMBLE (1<<1) |
aa2bdb24 | 399 | |
81629cba | 400 | struct drm_amdgpu_cs_chunk_ib { |
2ce9dde0 | 401 | __u32 _pad; |
675da0dd | 402 | /** AMDGPU_IB_FLAG_* */ |
2ce9dde0 | 403 | __u32 flags; |
675da0dd | 404 | /** Virtual address to begin IB execution */ |
2ce9dde0 | 405 | __u64 va_start; |
675da0dd | 406 | /** Size of submission */ |
2ce9dde0 | 407 | __u32 ib_bytes; |
675da0dd | 408 | /** HW IP to submit to */ |
2ce9dde0 | 409 | __u32 ip_type; |
675da0dd | 410 | /** HW IP index of the same type to submit to */ |
2ce9dde0 | 411 | __u32 ip_instance; |
675da0dd | 412 | /** Ring index to submit to */ |
2ce9dde0 | 413 | __u32 ring; |
81629cba AD |
414 | }; |
415 | ||
2b48d323 | 416 | struct drm_amdgpu_cs_chunk_dep { |
2ce9dde0 MR |
417 | __u32 ip_type; |
418 | __u32 ip_instance; | |
419 | __u32 ring; | |
420 | __u32 ctx_id; | |
421 | __u64 handle; | |
2b48d323 CK |
422 | }; |
423 | ||
81629cba | 424 | struct drm_amdgpu_cs_chunk_fence { |
2ce9dde0 MR |
425 | __u32 handle; |
426 | __u32 offset; | |
81629cba AD |
427 | }; |
428 | ||
429 | struct drm_amdgpu_cs_chunk_data { | |
430 | union { | |
431 | struct drm_amdgpu_cs_chunk_ib ib_data; | |
432 | struct drm_amdgpu_cs_chunk_fence fence_data; | |
433 | }; | |
434 | }; | |
435 | ||
436 | /** | |
437 | * Query h/w info: Flag that this is integrated (a.h.a. fusion) GPU | |
438 | * | |
439 | */ | |
440 | #define AMDGPU_IDS_FLAGS_FUSION 0x1 | |
441 | ||
442 | /* indicate if acceleration can be working */ | |
443 | #define AMDGPU_INFO_ACCEL_WORKING 0x00 | |
444 | /* get the crtc_id from the mode object id? */ | |
445 | #define AMDGPU_INFO_CRTC_FROM_ID 0x01 | |
446 | /* query hw IP info */ | |
447 | #define AMDGPU_INFO_HW_IP_INFO 0x02 | |
448 | /* query hw IP instance count for the specified type */ | |
449 | #define AMDGPU_INFO_HW_IP_COUNT 0x03 | |
450 | /* timestamp for GL_ARB_timer_query */ | |
451 | #define AMDGPU_INFO_TIMESTAMP 0x05 | |
452 | /* Query the firmware version */ | |
453 | #define AMDGPU_INFO_FW_VERSION 0x0e | |
454 | /* Subquery id: Query VCE firmware version */ | |
455 | #define AMDGPU_INFO_FW_VCE 0x1 | |
456 | /* Subquery id: Query UVD firmware version */ | |
457 | #define AMDGPU_INFO_FW_UVD 0x2 | |
458 | /* Subquery id: Query GMC firmware version */ | |
459 | #define AMDGPU_INFO_FW_GMC 0x03 | |
460 | /* Subquery id: Query GFX ME firmware version */ | |
461 | #define AMDGPU_INFO_FW_GFX_ME 0x04 | |
462 | /* Subquery id: Query GFX PFP firmware version */ | |
463 | #define AMDGPU_INFO_FW_GFX_PFP 0x05 | |
464 | /* Subquery id: Query GFX CE firmware version */ | |
465 | #define AMDGPU_INFO_FW_GFX_CE 0x06 | |
466 | /* Subquery id: Query GFX RLC firmware version */ | |
467 | #define AMDGPU_INFO_FW_GFX_RLC 0x07 | |
468 | /* Subquery id: Query GFX MEC firmware version */ | |
469 | #define AMDGPU_INFO_FW_GFX_MEC 0x08 | |
470 | /* Subquery id: Query SMC firmware version */ | |
471 | #define AMDGPU_INFO_FW_SMC 0x0a | |
472 | /* Subquery id: Query SDMA firmware version */ | |
473 | #define AMDGPU_INFO_FW_SDMA 0x0b | |
474 | /* number of bytes moved for TTM migration */ | |
475 | #define AMDGPU_INFO_NUM_BYTES_MOVED 0x0f | |
476 | /* the used VRAM size */ | |
477 | #define AMDGPU_INFO_VRAM_USAGE 0x10 | |
478 | /* the used GTT size */ | |
479 | #define AMDGPU_INFO_GTT_USAGE 0x11 | |
480 | /* Information about GDS, etc. resource configuration */ | |
481 | #define AMDGPU_INFO_GDS_CONFIG 0x13 | |
482 | /* Query information about VRAM and GTT domains */ | |
483 | #define AMDGPU_INFO_VRAM_GTT 0x14 | |
484 | /* Query information about register in MMR address space*/ | |
485 | #define AMDGPU_INFO_READ_MMR_REG 0x15 | |
486 | /* Query information about device: rev id, family, etc. */ | |
487 | #define AMDGPU_INFO_DEV_INFO 0x16 | |
488 | /* visible vram usage */ | |
489 | #define AMDGPU_INFO_VIS_VRAM_USAGE 0x17 | |
83a59b63 MO |
490 | /* number of TTM buffer evictions */ |
491 | #define AMDGPU_INFO_NUM_EVICTIONS 0x18 | |
9f6163e7 JZ |
492 | /* Query the total size of VRAM and GTT domains */ |
493 | #define AMDGPU_INFO_VRAM_GTT_TOTAL 0x19 | |
cfa32556 JZ |
494 | /* Query the max allocation size of VRAM and GTT domains */ |
495 | #define AMDGPU_INFO_VRAM_GTT_MAX 0x1a | |
81629cba AD |
496 | |
497 | #define AMDGPU_INFO_MMR_SE_INDEX_SHIFT 0 | |
498 | #define AMDGPU_INFO_MMR_SE_INDEX_MASK 0xff | |
499 | #define AMDGPU_INFO_MMR_SH_INDEX_SHIFT 8 | |
500 | #define AMDGPU_INFO_MMR_SH_INDEX_MASK 0xff | |
501 | ||
000cab9a HR |
502 | struct drm_amdgpu_query_fw { |
503 | /** AMDGPU_INFO_FW_* */ | |
504 | __u32 fw_type; | |
505 | /** | |
506 | * Index of the IP if there are more IPs of | |
507 | * the same type. | |
508 | */ | |
509 | __u32 ip_instance; | |
510 | /** | |
511 | * Index of the engine. Whether this is used depends | |
512 | * on the firmware type. (e.g. MEC, SDMA) | |
513 | */ | |
514 | __u32 index; | |
515 | __u32 _pad; | |
516 | }; | |
517 | ||
81629cba AD |
518 | /* Input structure for the INFO ioctl */ |
519 | struct drm_amdgpu_info { | |
520 | /* Where the return value will be stored */ | |
2ce9dde0 | 521 | __u64 return_pointer; |
81629cba AD |
522 | /* The size of the return value. Just like "size" in "snprintf", |
523 | * it limits how many bytes the kernel can write. */ | |
2ce9dde0 | 524 | __u32 return_size; |
81629cba | 525 | /* The query request id. */ |
2ce9dde0 | 526 | __u32 query; |
81629cba AD |
527 | |
528 | union { | |
529 | struct { | |
2ce9dde0 MR |
530 | __u32 id; |
531 | __u32 _pad; | |
81629cba AD |
532 | } mode_crtc; |
533 | ||
534 | struct { | |
535 | /** AMDGPU_HW_IP_* */ | |
2ce9dde0 | 536 | __u32 type; |
81629cba | 537 | /** |
675da0dd CK |
538 | * Index of the IP if there are more IPs of the same |
539 | * type. Ignored by AMDGPU_INFO_HW_IP_COUNT. | |
81629cba | 540 | */ |
2ce9dde0 | 541 | __u32 ip_instance; |
81629cba AD |
542 | } query_hw_ip; |
543 | ||
544 | struct { | |
2ce9dde0 | 545 | __u32 dword_offset; |
675da0dd | 546 | /** number of registers to read */ |
2ce9dde0 MR |
547 | __u32 count; |
548 | __u32 instance; | |
675da0dd | 549 | /** For future use, no flags defined so far */ |
2ce9dde0 | 550 | __u32 flags; |
81629cba AD |
551 | } read_mmr_reg; |
552 | ||
000cab9a | 553 | struct drm_amdgpu_query_fw query_fw; |
81629cba AD |
554 | }; |
555 | }; | |
556 | ||
557 | struct drm_amdgpu_info_gds { | |
558 | /** GDS GFX partition size */ | |
2ce9dde0 | 559 | __u32 gds_gfx_partition_size; |
81629cba | 560 | /** GDS compute partition size */ |
2ce9dde0 | 561 | __u32 compute_partition_size; |
81629cba | 562 | /** total GDS memory size */ |
2ce9dde0 | 563 | __u32 gds_total_size; |
81629cba | 564 | /** GWS size per GFX partition */ |
2ce9dde0 | 565 | __u32 gws_per_gfx_partition; |
81629cba | 566 | /** GSW size per compute partition */ |
2ce9dde0 | 567 | __u32 gws_per_compute_partition; |
81629cba | 568 | /** OA size per GFX partition */ |
2ce9dde0 | 569 | __u32 oa_per_gfx_partition; |
81629cba | 570 | /** OA size per compute partition */ |
2ce9dde0 MR |
571 | __u32 oa_per_compute_partition; |
572 | __u32 _pad; | |
81629cba AD |
573 | }; |
574 | ||
575 | struct drm_amdgpu_info_vram_gtt { | |
2ce9dde0 MR |
576 | __u64 vram_size; |
577 | __u64 vram_cpu_accessible_size; | |
578 | __u64 gtt_size; | |
81629cba AD |
579 | }; |
580 | ||
9f6163e7 JZ |
581 | struct drm_amdgpu_info_vram_gtt_total { |
582 | __u64 vram_total_size; | |
583 | __u64 vram_cpu_accessible_total_size; | |
584 | __u64 gtt_total_size; | |
585 | }; | |
586 | ||
cfa32556 JZ |
587 | struct drm_amdgpu_info_vram_gtt_max { |
588 | __u64 vram_max_size; | |
589 | __u64 vram_cpu_accessible_max_size; | |
590 | __u64 gtt_max_size; | |
591 | }; | |
592 | ||
81629cba | 593 | struct drm_amdgpu_info_firmware { |
2ce9dde0 MR |
594 | __u32 ver; |
595 | __u32 feature; | |
81629cba AD |
596 | }; |
597 | ||
81c59f54 KW |
598 | #define AMDGPU_VRAM_TYPE_UNKNOWN 0 |
599 | #define AMDGPU_VRAM_TYPE_GDDR1 1 | |
600 | #define AMDGPU_VRAM_TYPE_DDR2 2 | |
601 | #define AMDGPU_VRAM_TYPE_GDDR3 3 | |
602 | #define AMDGPU_VRAM_TYPE_GDDR4 4 | |
603 | #define AMDGPU_VRAM_TYPE_GDDR5 5 | |
604 | #define AMDGPU_VRAM_TYPE_HBM 6 | |
605 | #define AMDGPU_VRAM_TYPE_DDR3 7 | |
606 | ||
81629cba AD |
607 | struct drm_amdgpu_info_device { |
608 | /** PCI Device ID */ | |
2ce9dde0 | 609 | __u32 device_id; |
81629cba | 610 | /** Internal chip revision: A0, A1, etc.) */ |
2ce9dde0 MR |
611 | __u32 chip_rev; |
612 | __u32 external_rev; | |
81629cba | 613 | /** Revision id in PCI Config space */ |
2ce9dde0 MR |
614 | __u32 pci_rev; |
615 | __u32 family; | |
616 | __u32 num_shader_engines; | |
617 | __u32 num_shader_arrays_per_engine; | |
675da0dd | 618 | /* in KHz */ |
2ce9dde0 MR |
619 | __u32 gpu_counter_freq; |
620 | __u64 max_engine_clock; | |
621 | __u64 max_memory_clock; | |
81629cba | 622 | /* cu information */ |
2ce9dde0 MR |
623 | __u32 cu_active_number; |
624 | __u32 cu_ao_mask; | |
625 | __u32 cu_bitmap[4][4]; | |
81629cba | 626 | /** Render backend pipe mask. One render backend is CB+DB. */ |
2ce9dde0 MR |
627 | __u32 enabled_rb_pipes_mask; |
628 | __u32 num_rb_pipes; | |
629 | __u32 num_hw_gfx_contexts; | |
630 | __u32 _pad; | |
631 | __u64 ids_flags; | |
81629cba | 632 | /** Starting virtual address for UMDs. */ |
2ce9dde0 | 633 | __u64 virtual_address_offset; |
02b70c8c | 634 | /** The maximum virtual address */ |
2ce9dde0 | 635 | __u64 virtual_address_max; |
81629cba | 636 | /** Required alignment of virtual addresses. */ |
2ce9dde0 | 637 | __u32 virtual_address_alignment; |
81629cba | 638 | /** Page table entry - fragment size */ |
2ce9dde0 MR |
639 | __u32 pte_fragment_size; |
640 | __u32 gart_page_size; | |
a101a899 | 641 | /** constant engine ram size*/ |
2ce9dde0 | 642 | __u32 ce_ram_size; |
cab6d57c | 643 | /** video memory type info*/ |
2ce9dde0 | 644 | __u32 vram_type; |
81c59f54 | 645 | /** video memory bit width*/ |
2ce9dde0 | 646 | __u32 vram_bit_width; |
fa92754e | 647 | /* vce harvesting instance */ |
2ce9dde0 | 648 | __u32 vce_harvest_config; |
81629cba AD |
649 | }; |
650 | ||
651 | struct drm_amdgpu_info_hw_ip { | |
652 | /** Version of h/w IP */ | |
2ce9dde0 MR |
653 | __u32 hw_ip_version_major; |
654 | __u32 hw_ip_version_minor; | |
81629cba | 655 | /** Capabilities */ |
2ce9dde0 | 656 | __u64 capabilities_flags; |
71062f43 | 657 | /** command buffer address start alignment*/ |
2ce9dde0 | 658 | __u32 ib_start_alignment; |
71062f43 | 659 | /** command buffer size alignment*/ |
2ce9dde0 | 660 | __u32 ib_size_alignment; |
81629cba | 661 | /** Bitmask of available rings. Bit 0 means ring 0, etc. */ |
2ce9dde0 MR |
662 | __u32 available_rings; |
663 | __u32 _pad; | |
81629cba AD |
664 | }; |
665 | ||
666 | /* | |
667 | * Supported GPU families | |
668 | */ | |
669 | #define AMDGPU_FAMILY_UNKNOWN 0 | |
295d0daf | 670 | #define AMDGPU_FAMILY_SI 110 /* Hainan, Oland, Verde, Pitcairn, Tahiti */ |
81629cba AD |
671 | #define AMDGPU_FAMILY_CI 120 /* Bonaire, Hawaii */ |
672 | #define AMDGPU_FAMILY_KV 125 /* Kaveri, Kabini, Mullins */ | |
673 | #define AMDGPU_FAMILY_VI 130 /* Iceland, Tonga */ | |
39bb0c92 | 674 | #define AMDGPU_FAMILY_CZ 135 /* Carrizo, Stoney */ |
81629cba | 675 | |
cfa7152f EV |
676 | #if defined(__cplusplus) |
677 | } | |
678 | #endif | |
679 | ||
81629cba | 680 | #endif |