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81629cba AD |
1 | /* amdgpu_drm.h -- Public header for the amdgpu driver -*- linux-c -*- |
2 | * | |
3 | * Copyright 2000 Precision Insight, Inc., Cedar Park, Texas. | |
4 | * Copyright 2000 VA Linux Systems, Inc., Fremont, California. | |
5 | * Copyright 2002 Tungsten Graphics, Inc., Cedar Park, Texas. | |
6 | * Copyright 2014 Advanced Micro Devices, Inc. | |
7 | * | |
8 | * Permission is hereby granted, free of charge, to any person obtaining a | |
9 | * copy of this software and associated documentation files (the "Software"), | |
10 | * to deal in the Software without restriction, including without limitation | |
11 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
12 | * and/or sell copies of the Software, and to permit persons to whom the | |
13 | * Software is furnished to do so, subject to the following conditions: | |
14 | * | |
15 | * The above copyright notice and this permission notice shall be included in | |
16 | * all copies or substantial portions of the Software. | |
17 | * | |
18 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
19 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
20 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
21 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR | |
22 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, | |
23 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR | |
24 | * OTHER DEALINGS IN THE SOFTWARE. | |
25 | * | |
26 | * Authors: | |
27 | * Kevin E. Martin <martin@valinux.com> | |
28 | * Gareth Hughes <gareth@valinux.com> | |
29 | * Keith Whitwell <keith@tungstengraphics.com> | |
30 | */ | |
31 | ||
32 | #ifndef __AMDGPU_DRM_H__ | |
33 | #define __AMDGPU_DRM_H__ | |
34 | ||
b3fcf36a | 35 | #include "drm.h" |
81629cba | 36 | |
cfa7152f EV |
37 | #if defined(__cplusplus) |
38 | extern "C" { | |
39 | #endif | |
40 | ||
81629cba AD |
41 | #define DRM_AMDGPU_GEM_CREATE 0x00 |
42 | #define DRM_AMDGPU_GEM_MMAP 0x01 | |
43 | #define DRM_AMDGPU_CTX 0x02 | |
44 | #define DRM_AMDGPU_BO_LIST 0x03 | |
45 | #define DRM_AMDGPU_CS 0x04 | |
46 | #define DRM_AMDGPU_INFO 0x05 | |
47 | #define DRM_AMDGPU_GEM_METADATA 0x06 | |
48 | #define DRM_AMDGPU_GEM_WAIT_IDLE 0x07 | |
49 | #define DRM_AMDGPU_GEM_VA 0x08 | |
50 | #define DRM_AMDGPU_WAIT_CS 0x09 | |
51 | #define DRM_AMDGPU_GEM_OP 0x10 | |
52 | #define DRM_AMDGPU_GEM_USERPTR 0x11 | |
53 | ||
54 | #define DRM_IOCTL_AMDGPU_GEM_CREATE DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_CREATE, union drm_amdgpu_gem_create) | |
55 | #define DRM_IOCTL_AMDGPU_GEM_MMAP DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_MMAP, union drm_amdgpu_gem_mmap) | |
56 | #define DRM_IOCTL_AMDGPU_CTX DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_CTX, union drm_amdgpu_ctx) | |
57 | #define DRM_IOCTL_AMDGPU_BO_LIST DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_BO_LIST, union drm_amdgpu_bo_list) | |
58 | #define DRM_IOCTL_AMDGPU_CS DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_CS, union drm_amdgpu_cs) | |
59 | #define DRM_IOCTL_AMDGPU_INFO DRM_IOW(DRM_COMMAND_BASE + DRM_AMDGPU_INFO, struct drm_amdgpu_info) | |
60 | #define DRM_IOCTL_AMDGPU_GEM_METADATA DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_METADATA, struct drm_amdgpu_gem_metadata) | |
61 | #define DRM_IOCTL_AMDGPU_GEM_WAIT_IDLE DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_WAIT_IDLE, union drm_amdgpu_gem_wait_idle) | |
34b5f6a6 | 62 | #define DRM_IOCTL_AMDGPU_GEM_VA DRM_IOW(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_VA, struct drm_amdgpu_gem_va) |
81629cba AD |
63 | #define DRM_IOCTL_AMDGPU_WAIT_CS DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_WAIT_CS, union drm_amdgpu_wait_cs) |
64 | #define DRM_IOCTL_AMDGPU_GEM_OP DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_OP, struct drm_amdgpu_gem_op) | |
65 | #define DRM_IOCTL_AMDGPU_GEM_USERPTR DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_USERPTR, struct drm_amdgpu_gem_userptr) | |
66 | ||
67 | #define AMDGPU_GEM_DOMAIN_CPU 0x1 | |
68 | #define AMDGPU_GEM_DOMAIN_GTT 0x2 | |
69 | #define AMDGPU_GEM_DOMAIN_VRAM 0x4 | |
70 | #define AMDGPU_GEM_DOMAIN_GDS 0x8 | |
71 | #define AMDGPU_GEM_DOMAIN_GWS 0x10 | |
72 | #define AMDGPU_GEM_DOMAIN_OA 0x20 | |
73 | ||
81629cba AD |
74 | /* Flag that CPU access will be required for the case of VRAM domain */ |
75 | #define AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED (1 << 0) | |
76 | /* Flag that CPU access will not work, this VRAM domain is invisible */ | |
77 | #define AMDGPU_GEM_CREATE_NO_CPU_ACCESS (1 << 1) | |
81629cba | 78 | /* Flag that USWC attributes should be used for GTT */ |
88671288 | 79 | #define AMDGPU_GEM_CREATE_CPU_GTT_USWC (1 << 2) |
4fea83ff FC |
80 | /* Flag that the memory should be in VRAM and cleared */ |
81 | #define AMDGPU_GEM_CREATE_VRAM_CLEARED (1 << 3) | |
e7893c4b CZ |
82 | /* Flag that create shadow bo(GTT) while allocating vram bo */ |
83 | #define AMDGPU_GEM_CREATE_SHADOW (1 << 4) | |
81629cba | 84 | |
81629cba AD |
85 | struct drm_amdgpu_gem_create_in { |
86 | /** the requested memory size */ | |
2ce9dde0 | 87 | __u64 bo_size; |
81629cba | 88 | /** physical start_addr alignment in bytes for some HW requirements */ |
2ce9dde0 | 89 | __u64 alignment; |
81629cba | 90 | /** the requested memory domains */ |
2ce9dde0 | 91 | __u64 domains; |
81629cba | 92 | /** allocation flags */ |
2ce9dde0 | 93 | __u64 domain_flags; |
81629cba AD |
94 | }; |
95 | ||
96 | struct drm_amdgpu_gem_create_out { | |
97 | /** returned GEM object handle */ | |
2ce9dde0 MR |
98 | __u32 handle; |
99 | __u32 _pad; | |
81629cba AD |
100 | }; |
101 | ||
102 | union drm_amdgpu_gem_create { | |
103 | struct drm_amdgpu_gem_create_in in; | |
104 | struct drm_amdgpu_gem_create_out out; | |
105 | }; | |
106 | ||
107 | /** Opcode to create new residency list. */ | |
108 | #define AMDGPU_BO_LIST_OP_CREATE 0 | |
109 | /** Opcode to destroy previously created residency list */ | |
110 | #define AMDGPU_BO_LIST_OP_DESTROY 1 | |
111 | /** Opcode to update resource information in the list */ | |
112 | #define AMDGPU_BO_LIST_OP_UPDATE 2 | |
113 | ||
114 | struct drm_amdgpu_bo_list_in { | |
115 | /** Type of operation */ | |
2ce9dde0 | 116 | __u32 operation; |
81629cba | 117 | /** Handle of list or 0 if we want to create one */ |
2ce9dde0 | 118 | __u32 list_handle; |
81629cba | 119 | /** Number of BOs in list */ |
2ce9dde0 | 120 | __u32 bo_number; |
81629cba | 121 | /** Size of each element describing BO */ |
2ce9dde0 | 122 | __u32 bo_info_size; |
81629cba | 123 | /** Pointer to array describing BOs */ |
2ce9dde0 | 124 | __u64 bo_info_ptr; |
81629cba AD |
125 | }; |
126 | ||
127 | struct drm_amdgpu_bo_list_entry { | |
128 | /** Handle of BO */ | |
2ce9dde0 | 129 | __u32 bo_handle; |
81629cba | 130 | /** New (if specified) BO priority to be used during migration */ |
2ce9dde0 | 131 | __u32 bo_priority; |
81629cba AD |
132 | }; |
133 | ||
134 | struct drm_amdgpu_bo_list_out { | |
135 | /** Handle of resource list */ | |
2ce9dde0 MR |
136 | __u32 list_handle; |
137 | __u32 _pad; | |
81629cba AD |
138 | }; |
139 | ||
140 | union drm_amdgpu_bo_list { | |
141 | struct drm_amdgpu_bo_list_in in; | |
142 | struct drm_amdgpu_bo_list_out out; | |
143 | }; | |
144 | ||
145 | /* context related */ | |
146 | #define AMDGPU_CTX_OP_ALLOC_CTX 1 | |
147 | #define AMDGPU_CTX_OP_FREE_CTX 2 | |
148 | #define AMDGPU_CTX_OP_QUERY_STATE 3 | |
149 | ||
d94aed5a MO |
150 | /* GPU reset status */ |
151 | #define AMDGPU_CTX_NO_RESET 0 | |
675da0dd CK |
152 | /* this the context caused it */ |
153 | #define AMDGPU_CTX_GUILTY_RESET 1 | |
154 | /* some other context caused it */ | |
155 | #define AMDGPU_CTX_INNOCENT_RESET 2 | |
156 | /* unknown cause */ | |
157 | #define AMDGPU_CTX_UNKNOWN_RESET 3 | |
d94aed5a | 158 | |
81629cba | 159 | struct drm_amdgpu_ctx_in { |
675da0dd | 160 | /** AMDGPU_CTX_OP_* */ |
2ce9dde0 | 161 | __u32 op; |
675da0dd | 162 | /** For future use, no flags defined so far */ |
2ce9dde0 MR |
163 | __u32 flags; |
164 | __u32 ctx_id; | |
165 | __u32 _pad; | |
81629cba AD |
166 | }; |
167 | ||
168 | union drm_amdgpu_ctx_out { | |
169 | struct { | |
2ce9dde0 MR |
170 | __u32 ctx_id; |
171 | __u32 _pad; | |
81629cba AD |
172 | } alloc; |
173 | ||
174 | struct { | |
675da0dd | 175 | /** For future use, no flags defined so far */ |
2ce9dde0 | 176 | __u64 flags; |
d94aed5a | 177 | /** Number of resets caused by this context so far. */ |
2ce9dde0 | 178 | __u32 hangs; |
d94aed5a | 179 | /** Reset status since the last call of the ioctl. */ |
2ce9dde0 | 180 | __u32 reset_status; |
81629cba AD |
181 | } state; |
182 | }; | |
183 | ||
184 | union drm_amdgpu_ctx { | |
185 | struct drm_amdgpu_ctx_in in; | |
186 | union drm_amdgpu_ctx_out out; | |
187 | }; | |
188 | ||
189 | /* | |
190 | * This is not a reliable API and you should expect it to fail for any | |
191 | * number of reasons and have fallback path that do not use userptr to | |
192 | * perform any operation. | |
193 | */ | |
194 | #define AMDGPU_GEM_USERPTR_READONLY (1 << 0) | |
195 | #define AMDGPU_GEM_USERPTR_ANONONLY (1 << 1) | |
196 | #define AMDGPU_GEM_USERPTR_VALIDATE (1 << 2) | |
197 | #define AMDGPU_GEM_USERPTR_REGISTER (1 << 3) | |
198 | ||
199 | struct drm_amdgpu_gem_userptr { | |
2ce9dde0 MR |
200 | __u64 addr; |
201 | __u64 size; | |
675da0dd | 202 | /* AMDGPU_GEM_USERPTR_* */ |
2ce9dde0 | 203 | __u32 flags; |
675da0dd | 204 | /* Resulting GEM handle */ |
2ce9dde0 | 205 | __u32 handle; |
81629cba AD |
206 | }; |
207 | ||
fbd76d59 MO |
208 | /* same meaning as the GB_TILE_MODE and GL_MACRO_TILE_MODE fields */ |
209 | #define AMDGPU_TILING_ARRAY_MODE_SHIFT 0 | |
210 | #define AMDGPU_TILING_ARRAY_MODE_MASK 0xf | |
211 | #define AMDGPU_TILING_PIPE_CONFIG_SHIFT 4 | |
212 | #define AMDGPU_TILING_PIPE_CONFIG_MASK 0x1f | |
213 | #define AMDGPU_TILING_TILE_SPLIT_SHIFT 9 | |
214 | #define AMDGPU_TILING_TILE_SPLIT_MASK 0x7 | |
215 | #define AMDGPU_TILING_MICRO_TILE_MODE_SHIFT 12 | |
216 | #define AMDGPU_TILING_MICRO_TILE_MODE_MASK 0x7 | |
217 | #define AMDGPU_TILING_BANK_WIDTH_SHIFT 15 | |
218 | #define AMDGPU_TILING_BANK_WIDTH_MASK 0x3 | |
219 | #define AMDGPU_TILING_BANK_HEIGHT_SHIFT 17 | |
220 | #define AMDGPU_TILING_BANK_HEIGHT_MASK 0x3 | |
221 | #define AMDGPU_TILING_MACRO_TILE_ASPECT_SHIFT 19 | |
222 | #define AMDGPU_TILING_MACRO_TILE_ASPECT_MASK 0x3 | |
223 | #define AMDGPU_TILING_NUM_BANKS_SHIFT 21 | |
224 | #define AMDGPU_TILING_NUM_BANKS_MASK 0x3 | |
225 | ||
226 | #define AMDGPU_TILING_SET(field, value) \ | |
227 | (((value) & AMDGPU_TILING_##field##_MASK) << AMDGPU_TILING_##field##_SHIFT) | |
228 | #define AMDGPU_TILING_GET(value, field) \ | |
229 | (((value) >> AMDGPU_TILING_##field##_SHIFT) & AMDGPU_TILING_##field##_MASK) | |
81629cba AD |
230 | |
231 | #define AMDGPU_GEM_METADATA_OP_SET_METADATA 1 | |
232 | #define AMDGPU_GEM_METADATA_OP_GET_METADATA 2 | |
233 | ||
234 | /** The same structure is shared for input/output */ | |
235 | struct drm_amdgpu_gem_metadata { | |
675da0dd | 236 | /** GEM Object handle */ |
2ce9dde0 | 237 | __u32 handle; |
675da0dd | 238 | /** Do we want get or set metadata */ |
2ce9dde0 | 239 | __u32 op; |
81629cba | 240 | struct { |
675da0dd | 241 | /** For future use, no flags defined so far */ |
2ce9dde0 | 242 | __u64 flags; |
675da0dd | 243 | /** family specific tiling info */ |
2ce9dde0 MR |
244 | __u64 tiling_info; |
245 | __u32 data_size_bytes; | |
246 | __u32 data[64]; | |
81629cba AD |
247 | } data; |
248 | }; | |
249 | ||
250 | struct drm_amdgpu_gem_mmap_in { | |
675da0dd | 251 | /** the GEM object handle */ |
2ce9dde0 MR |
252 | __u32 handle; |
253 | __u32 _pad; | |
81629cba AD |
254 | }; |
255 | ||
256 | struct drm_amdgpu_gem_mmap_out { | |
675da0dd | 257 | /** mmap offset from the vma offset manager */ |
2ce9dde0 | 258 | __u64 addr_ptr; |
81629cba AD |
259 | }; |
260 | ||
261 | union drm_amdgpu_gem_mmap { | |
262 | struct drm_amdgpu_gem_mmap_in in; | |
263 | struct drm_amdgpu_gem_mmap_out out; | |
264 | }; | |
265 | ||
266 | struct drm_amdgpu_gem_wait_idle_in { | |
675da0dd | 267 | /** GEM object handle */ |
2ce9dde0 | 268 | __u32 handle; |
675da0dd | 269 | /** For future use, no flags defined so far */ |
2ce9dde0 | 270 | __u32 flags; |
675da0dd | 271 | /** Absolute timeout to wait */ |
2ce9dde0 | 272 | __u64 timeout; |
81629cba AD |
273 | }; |
274 | ||
275 | struct drm_amdgpu_gem_wait_idle_out { | |
675da0dd | 276 | /** BO status: 0 - BO is idle, 1 - BO is busy */ |
2ce9dde0 | 277 | __u32 status; |
675da0dd | 278 | /** Returned current memory domain */ |
2ce9dde0 | 279 | __u32 domain; |
81629cba AD |
280 | }; |
281 | ||
282 | union drm_amdgpu_gem_wait_idle { | |
283 | struct drm_amdgpu_gem_wait_idle_in in; | |
284 | struct drm_amdgpu_gem_wait_idle_out out; | |
285 | }; | |
286 | ||
287 | struct drm_amdgpu_wait_cs_in { | |
675da0dd | 288 | /** Command submission handle */ |
2ce9dde0 | 289 | __u64 handle; |
675da0dd | 290 | /** Absolute timeout to wait */ |
2ce9dde0 MR |
291 | __u64 timeout; |
292 | __u32 ip_type; | |
293 | __u32 ip_instance; | |
294 | __u32 ring; | |
295 | __u32 ctx_id; | |
81629cba AD |
296 | }; |
297 | ||
298 | struct drm_amdgpu_wait_cs_out { | |
675da0dd | 299 | /** CS status: 0 - CS completed, 1 - CS still busy */ |
2ce9dde0 | 300 | __u64 status; |
81629cba AD |
301 | }; |
302 | ||
303 | union drm_amdgpu_wait_cs { | |
304 | struct drm_amdgpu_wait_cs_in in; | |
305 | struct drm_amdgpu_wait_cs_out out; | |
306 | }; | |
307 | ||
675da0dd CK |
308 | #define AMDGPU_GEM_OP_GET_GEM_CREATE_INFO 0 |
309 | #define AMDGPU_GEM_OP_SET_PLACEMENT 1 | |
310 | ||
81629cba AD |
311 | /* Sets or returns a value associated with a buffer. */ |
312 | struct drm_amdgpu_gem_op { | |
675da0dd | 313 | /** GEM object handle */ |
2ce9dde0 | 314 | __u32 handle; |
675da0dd | 315 | /** AMDGPU_GEM_OP_* */ |
2ce9dde0 | 316 | __u32 op; |
675da0dd | 317 | /** Input or return value */ |
2ce9dde0 | 318 | __u64 value; |
81629cba AD |
319 | }; |
320 | ||
81629cba AD |
321 | #define AMDGPU_VA_OP_MAP 1 |
322 | #define AMDGPU_VA_OP_UNMAP 2 | |
323 | ||
fc220f65 CK |
324 | /* Delay the page table update till the next CS */ |
325 | #define AMDGPU_VM_DELAY_UPDATE (1 << 0) | |
326 | ||
81629cba AD |
327 | /* Mapping flags */ |
328 | /* readable mapping */ | |
329 | #define AMDGPU_VM_PAGE_READABLE (1 << 1) | |
330 | /* writable mapping */ | |
331 | #define AMDGPU_VM_PAGE_WRITEABLE (1 << 2) | |
332 | /* executable mapping, new for VI */ | |
333 | #define AMDGPU_VM_PAGE_EXECUTABLE (1 << 3) | |
334 | ||
34b5f6a6 | 335 | struct drm_amdgpu_gem_va { |
675da0dd | 336 | /** GEM object handle */ |
2ce9dde0 MR |
337 | __u32 handle; |
338 | __u32 _pad; | |
675da0dd | 339 | /** AMDGPU_VA_OP_* */ |
2ce9dde0 | 340 | __u32 operation; |
675da0dd | 341 | /** AMDGPU_VM_PAGE_* */ |
2ce9dde0 | 342 | __u32 flags; |
675da0dd | 343 | /** va address to assign . Must be correctly aligned.*/ |
2ce9dde0 | 344 | __u64 va_address; |
675da0dd | 345 | /** Specify offset inside of BO to assign. Must be correctly aligned.*/ |
2ce9dde0 | 346 | __u64 offset_in_bo; |
675da0dd | 347 | /** Specify mapping size. Must be correctly aligned. */ |
2ce9dde0 | 348 | __u64 map_size; |
81629cba AD |
349 | }; |
350 | ||
81629cba AD |
351 | #define AMDGPU_HW_IP_GFX 0 |
352 | #define AMDGPU_HW_IP_COMPUTE 1 | |
353 | #define AMDGPU_HW_IP_DMA 2 | |
354 | #define AMDGPU_HW_IP_UVD 3 | |
355 | #define AMDGPU_HW_IP_VCE 4 | |
356 | #define AMDGPU_HW_IP_NUM 5 | |
357 | ||
358 | #define AMDGPU_HW_IP_INSTANCE_MAX_COUNT 1 | |
359 | ||
360 | #define AMDGPU_CHUNK_ID_IB 0x01 | |
361 | #define AMDGPU_CHUNK_ID_FENCE 0x02 | |
2b48d323 | 362 | #define AMDGPU_CHUNK_ID_DEPENDENCIES 0x03 |
675da0dd | 363 | |
81629cba | 364 | struct drm_amdgpu_cs_chunk { |
2ce9dde0 MR |
365 | __u32 chunk_id; |
366 | __u32 length_dw; | |
367 | __u64 chunk_data; | |
81629cba AD |
368 | }; |
369 | ||
370 | struct drm_amdgpu_cs_in { | |
371 | /** Rendering context id */ | |
2ce9dde0 | 372 | __u32 ctx_id; |
81629cba | 373 | /** Handle of resource list associated with CS */ |
2ce9dde0 MR |
374 | __u32 bo_list_handle; |
375 | __u32 num_chunks; | |
376 | __u32 _pad; | |
377 | /** this points to __u64 * which point to cs chunks */ | |
378 | __u64 chunks; | |
81629cba AD |
379 | }; |
380 | ||
381 | struct drm_amdgpu_cs_out { | |
2ce9dde0 | 382 | __u64 handle; |
81629cba AD |
383 | }; |
384 | ||
385 | union drm_amdgpu_cs { | |
675da0dd CK |
386 | struct drm_amdgpu_cs_in in; |
387 | struct drm_amdgpu_cs_out out; | |
81629cba AD |
388 | }; |
389 | ||
390 | /* Specify flags to be used for IB */ | |
391 | ||
392 | /* This IB should be submitted to CE */ | |
393 | #define AMDGPU_IB_FLAG_CE (1<<0) | |
394 | ||
aa2bdb24 | 395 | /* CE Preamble */ |
cab6d57c | 396 | #define AMDGPU_IB_FLAG_PREAMBLE (1<<1) |
aa2bdb24 | 397 | |
81629cba | 398 | struct drm_amdgpu_cs_chunk_ib { |
2ce9dde0 | 399 | __u32 _pad; |
675da0dd | 400 | /** AMDGPU_IB_FLAG_* */ |
2ce9dde0 | 401 | __u32 flags; |
675da0dd | 402 | /** Virtual address to begin IB execution */ |
2ce9dde0 | 403 | __u64 va_start; |
675da0dd | 404 | /** Size of submission */ |
2ce9dde0 | 405 | __u32 ib_bytes; |
675da0dd | 406 | /** HW IP to submit to */ |
2ce9dde0 | 407 | __u32 ip_type; |
675da0dd | 408 | /** HW IP index of the same type to submit to */ |
2ce9dde0 | 409 | __u32 ip_instance; |
675da0dd | 410 | /** Ring index to submit to */ |
2ce9dde0 | 411 | __u32 ring; |
81629cba AD |
412 | }; |
413 | ||
2b48d323 | 414 | struct drm_amdgpu_cs_chunk_dep { |
2ce9dde0 MR |
415 | __u32 ip_type; |
416 | __u32 ip_instance; | |
417 | __u32 ring; | |
418 | __u32 ctx_id; | |
419 | __u64 handle; | |
2b48d323 CK |
420 | }; |
421 | ||
81629cba | 422 | struct drm_amdgpu_cs_chunk_fence { |
2ce9dde0 MR |
423 | __u32 handle; |
424 | __u32 offset; | |
81629cba AD |
425 | }; |
426 | ||
427 | struct drm_amdgpu_cs_chunk_data { | |
428 | union { | |
429 | struct drm_amdgpu_cs_chunk_ib ib_data; | |
430 | struct drm_amdgpu_cs_chunk_fence fence_data; | |
431 | }; | |
432 | }; | |
433 | ||
434 | /** | |
435 | * Query h/w info: Flag that this is integrated (a.h.a. fusion) GPU | |
436 | * | |
437 | */ | |
438 | #define AMDGPU_IDS_FLAGS_FUSION 0x1 | |
439 | ||
440 | /* indicate if acceleration can be working */ | |
441 | #define AMDGPU_INFO_ACCEL_WORKING 0x00 | |
442 | /* get the crtc_id from the mode object id? */ | |
443 | #define AMDGPU_INFO_CRTC_FROM_ID 0x01 | |
444 | /* query hw IP info */ | |
445 | #define AMDGPU_INFO_HW_IP_INFO 0x02 | |
446 | /* query hw IP instance count for the specified type */ | |
447 | #define AMDGPU_INFO_HW_IP_COUNT 0x03 | |
448 | /* timestamp for GL_ARB_timer_query */ | |
449 | #define AMDGPU_INFO_TIMESTAMP 0x05 | |
450 | /* Query the firmware version */ | |
451 | #define AMDGPU_INFO_FW_VERSION 0x0e | |
452 | /* Subquery id: Query VCE firmware version */ | |
453 | #define AMDGPU_INFO_FW_VCE 0x1 | |
454 | /* Subquery id: Query UVD firmware version */ | |
455 | #define AMDGPU_INFO_FW_UVD 0x2 | |
456 | /* Subquery id: Query GMC firmware version */ | |
457 | #define AMDGPU_INFO_FW_GMC 0x03 | |
458 | /* Subquery id: Query GFX ME firmware version */ | |
459 | #define AMDGPU_INFO_FW_GFX_ME 0x04 | |
460 | /* Subquery id: Query GFX PFP firmware version */ | |
461 | #define AMDGPU_INFO_FW_GFX_PFP 0x05 | |
462 | /* Subquery id: Query GFX CE firmware version */ | |
463 | #define AMDGPU_INFO_FW_GFX_CE 0x06 | |
464 | /* Subquery id: Query GFX RLC firmware version */ | |
465 | #define AMDGPU_INFO_FW_GFX_RLC 0x07 | |
466 | /* Subquery id: Query GFX MEC firmware version */ | |
467 | #define AMDGPU_INFO_FW_GFX_MEC 0x08 | |
468 | /* Subquery id: Query SMC firmware version */ | |
469 | #define AMDGPU_INFO_FW_SMC 0x0a | |
470 | /* Subquery id: Query SDMA firmware version */ | |
471 | #define AMDGPU_INFO_FW_SDMA 0x0b | |
472 | /* number of bytes moved for TTM migration */ | |
473 | #define AMDGPU_INFO_NUM_BYTES_MOVED 0x0f | |
474 | /* the used VRAM size */ | |
475 | #define AMDGPU_INFO_VRAM_USAGE 0x10 | |
476 | /* the used GTT size */ | |
477 | #define AMDGPU_INFO_GTT_USAGE 0x11 | |
478 | /* Information about GDS, etc. resource configuration */ | |
479 | #define AMDGPU_INFO_GDS_CONFIG 0x13 | |
480 | /* Query information about VRAM and GTT domains */ | |
481 | #define AMDGPU_INFO_VRAM_GTT 0x14 | |
482 | /* Query information about register in MMR address space*/ | |
483 | #define AMDGPU_INFO_READ_MMR_REG 0x15 | |
484 | /* Query information about device: rev id, family, etc. */ | |
485 | #define AMDGPU_INFO_DEV_INFO 0x16 | |
486 | /* visible vram usage */ | |
487 | #define AMDGPU_INFO_VIS_VRAM_USAGE 0x17 | |
83a59b63 MO |
488 | /* number of TTM buffer evictions */ |
489 | #define AMDGPU_INFO_NUM_EVICTIONS 0x18 | |
9f6163e7 JZ |
490 | /* Query the total size of VRAM and GTT domains */ |
491 | #define AMDGPU_INFO_VRAM_GTT_TOTAL 0x19 | |
81629cba AD |
492 | |
493 | #define AMDGPU_INFO_MMR_SE_INDEX_SHIFT 0 | |
494 | #define AMDGPU_INFO_MMR_SE_INDEX_MASK 0xff | |
495 | #define AMDGPU_INFO_MMR_SH_INDEX_SHIFT 8 | |
496 | #define AMDGPU_INFO_MMR_SH_INDEX_MASK 0xff | |
497 | ||
000cab9a HR |
498 | struct drm_amdgpu_query_fw { |
499 | /** AMDGPU_INFO_FW_* */ | |
500 | __u32 fw_type; | |
501 | /** | |
502 | * Index of the IP if there are more IPs of | |
503 | * the same type. | |
504 | */ | |
505 | __u32 ip_instance; | |
506 | /** | |
507 | * Index of the engine. Whether this is used depends | |
508 | * on the firmware type. (e.g. MEC, SDMA) | |
509 | */ | |
510 | __u32 index; | |
511 | __u32 _pad; | |
512 | }; | |
513 | ||
81629cba AD |
514 | /* Input structure for the INFO ioctl */ |
515 | struct drm_amdgpu_info { | |
516 | /* Where the return value will be stored */ | |
2ce9dde0 | 517 | __u64 return_pointer; |
81629cba AD |
518 | /* The size of the return value. Just like "size" in "snprintf", |
519 | * it limits how many bytes the kernel can write. */ | |
2ce9dde0 | 520 | __u32 return_size; |
81629cba | 521 | /* The query request id. */ |
2ce9dde0 | 522 | __u32 query; |
81629cba AD |
523 | |
524 | union { | |
525 | struct { | |
2ce9dde0 MR |
526 | __u32 id; |
527 | __u32 _pad; | |
81629cba AD |
528 | } mode_crtc; |
529 | ||
530 | struct { | |
531 | /** AMDGPU_HW_IP_* */ | |
2ce9dde0 | 532 | __u32 type; |
81629cba | 533 | /** |
675da0dd CK |
534 | * Index of the IP if there are more IPs of the same |
535 | * type. Ignored by AMDGPU_INFO_HW_IP_COUNT. | |
81629cba | 536 | */ |
2ce9dde0 | 537 | __u32 ip_instance; |
81629cba AD |
538 | } query_hw_ip; |
539 | ||
540 | struct { | |
2ce9dde0 | 541 | __u32 dword_offset; |
675da0dd | 542 | /** number of registers to read */ |
2ce9dde0 MR |
543 | __u32 count; |
544 | __u32 instance; | |
675da0dd | 545 | /** For future use, no flags defined so far */ |
2ce9dde0 | 546 | __u32 flags; |
81629cba AD |
547 | } read_mmr_reg; |
548 | ||
000cab9a | 549 | struct drm_amdgpu_query_fw query_fw; |
81629cba AD |
550 | }; |
551 | }; | |
552 | ||
553 | struct drm_amdgpu_info_gds { | |
554 | /** GDS GFX partition size */ | |
2ce9dde0 | 555 | __u32 gds_gfx_partition_size; |
81629cba | 556 | /** GDS compute partition size */ |
2ce9dde0 | 557 | __u32 compute_partition_size; |
81629cba | 558 | /** total GDS memory size */ |
2ce9dde0 | 559 | __u32 gds_total_size; |
81629cba | 560 | /** GWS size per GFX partition */ |
2ce9dde0 | 561 | __u32 gws_per_gfx_partition; |
81629cba | 562 | /** GSW size per compute partition */ |
2ce9dde0 | 563 | __u32 gws_per_compute_partition; |
81629cba | 564 | /** OA size per GFX partition */ |
2ce9dde0 | 565 | __u32 oa_per_gfx_partition; |
81629cba | 566 | /** OA size per compute partition */ |
2ce9dde0 MR |
567 | __u32 oa_per_compute_partition; |
568 | __u32 _pad; | |
81629cba AD |
569 | }; |
570 | ||
571 | struct drm_amdgpu_info_vram_gtt { | |
2ce9dde0 MR |
572 | __u64 vram_size; |
573 | __u64 vram_cpu_accessible_size; | |
574 | __u64 gtt_size; | |
81629cba AD |
575 | }; |
576 | ||
9f6163e7 JZ |
577 | struct drm_amdgpu_info_vram_gtt_total { |
578 | __u64 vram_total_size; | |
579 | __u64 vram_cpu_accessible_total_size; | |
580 | __u64 gtt_total_size; | |
581 | }; | |
582 | ||
81629cba | 583 | struct drm_amdgpu_info_firmware { |
2ce9dde0 MR |
584 | __u32 ver; |
585 | __u32 feature; | |
81629cba AD |
586 | }; |
587 | ||
81c59f54 KW |
588 | #define AMDGPU_VRAM_TYPE_UNKNOWN 0 |
589 | #define AMDGPU_VRAM_TYPE_GDDR1 1 | |
590 | #define AMDGPU_VRAM_TYPE_DDR2 2 | |
591 | #define AMDGPU_VRAM_TYPE_GDDR3 3 | |
592 | #define AMDGPU_VRAM_TYPE_GDDR4 4 | |
593 | #define AMDGPU_VRAM_TYPE_GDDR5 5 | |
594 | #define AMDGPU_VRAM_TYPE_HBM 6 | |
595 | #define AMDGPU_VRAM_TYPE_DDR3 7 | |
596 | ||
81629cba AD |
597 | struct drm_amdgpu_info_device { |
598 | /** PCI Device ID */ | |
2ce9dde0 | 599 | __u32 device_id; |
81629cba | 600 | /** Internal chip revision: A0, A1, etc.) */ |
2ce9dde0 MR |
601 | __u32 chip_rev; |
602 | __u32 external_rev; | |
81629cba | 603 | /** Revision id in PCI Config space */ |
2ce9dde0 MR |
604 | __u32 pci_rev; |
605 | __u32 family; | |
606 | __u32 num_shader_engines; | |
607 | __u32 num_shader_arrays_per_engine; | |
675da0dd | 608 | /* in KHz */ |
2ce9dde0 MR |
609 | __u32 gpu_counter_freq; |
610 | __u64 max_engine_clock; | |
611 | __u64 max_memory_clock; | |
81629cba | 612 | /* cu information */ |
2ce9dde0 MR |
613 | __u32 cu_active_number; |
614 | __u32 cu_ao_mask; | |
615 | __u32 cu_bitmap[4][4]; | |
81629cba | 616 | /** Render backend pipe mask. One render backend is CB+DB. */ |
2ce9dde0 MR |
617 | __u32 enabled_rb_pipes_mask; |
618 | __u32 num_rb_pipes; | |
619 | __u32 num_hw_gfx_contexts; | |
620 | __u32 _pad; | |
621 | __u64 ids_flags; | |
81629cba | 622 | /** Starting virtual address for UMDs. */ |
2ce9dde0 | 623 | __u64 virtual_address_offset; |
02b70c8c | 624 | /** The maximum virtual address */ |
2ce9dde0 | 625 | __u64 virtual_address_max; |
81629cba | 626 | /** Required alignment of virtual addresses. */ |
2ce9dde0 | 627 | __u32 virtual_address_alignment; |
81629cba | 628 | /** Page table entry - fragment size */ |
2ce9dde0 MR |
629 | __u32 pte_fragment_size; |
630 | __u32 gart_page_size; | |
a101a899 | 631 | /** constant engine ram size*/ |
2ce9dde0 | 632 | __u32 ce_ram_size; |
cab6d57c | 633 | /** video memory type info*/ |
2ce9dde0 | 634 | __u32 vram_type; |
81c59f54 | 635 | /** video memory bit width*/ |
2ce9dde0 | 636 | __u32 vram_bit_width; |
fa92754e | 637 | /* vce harvesting instance */ |
2ce9dde0 | 638 | __u32 vce_harvest_config; |
81629cba AD |
639 | }; |
640 | ||
641 | struct drm_amdgpu_info_hw_ip { | |
642 | /** Version of h/w IP */ | |
2ce9dde0 MR |
643 | __u32 hw_ip_version_major; |
644 | __u32 hw_ip_version_minor; | |
81629cba | 645 | /** Capabilities */ |
2ce9dde0 | 646 | __u64 capabilities_flags; |
71062f43 | 647 | /** command buffer address start alignment*/ |
2ce9dde0 | 648 | __u32 ib_start_alignment; |
71062f43 | 649 | /** command buffer size alignment*/ |
2ce9dde0 | 650 | __u32 ib_size_alignment; |
81629cba | 651 | /** Bitmask of available rings. Bit 0 means ring 0, etc. */ |
2ce9dde0 MR |
652 | __u32 available_rings; |
653 | __u32 _pad; | |
81629cba AD |
654 | }; |
655 | ||
656 | /* | |
657 | * Supported GPU families | |
658 | */ | |
659 | #define AMDGPU_FAMILY_UNKNOWN 0 | |
295d0daf | 660 | #define AMDGPU_FAMILY_SI 110 /* Hainan, Oland, Verde, Pitcairn, Tahiti */ |
81629cba AD |
661 | #define AMDGPU_FAMILY_CI 120 /* Bonaire, Hawaii */ |
662 | #define AMDGPU_FAMILY_KV 125 /* Kaveri, Kabini, Mullins */ | |
663 | #define AMDGPU_FAMILY_VI 130 /* Iceland, Tonga */ | |
39bb0c92 | 664 | #define AMDGPU_FAMILY_CZ 135 /* Carrizo, Stoney */ |
81629cba | 665 | |
cfa7152f EV |
666 | #if defined(__cplusplus) |
667 | } | |
668 | #endif | |
669 | ||
81629cba | 670 | #endif |