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1da177e4 | 1 | /** |
b5e89ed5 | 2 | * \file drm.h |
1da177e4 | 3 | * Header for the Direct Rendering Manager |
b5e89ed5 | 4 | * |
1da177e4 LT |
5 | * \author Rickard E. (Rik) Faith <faith@valinux.com> |
6 | * | |
7 | * \par Acknowledgments: | |
8 | * Dec 1999, Richard Henderson <rth@twiddle.net>, move to generic \c cmpxchg. | |
9 | */ | |
10 | ||
11 | /* | |
12 | * Copyright 1999 Precision Insight, Inc., Cedar Park, Texas. | |
13 | * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California. | |
14 | * All rights reserved. | |
15 | * | |
16 | * Permission is hereby granted, free of charge, to any person obtaining a | |
17 | * copy of this software and associated documentation files (the "Software"), | |
18 | * to deal in the Software without restriction, including without limitation | |
19 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
20 | * and/or sell copies of the Software, and to permit persons to whom the | |
21 | * Software is furnished to do so, subject to the following conditions: | |
22 | * | |
23 | * The above copyright notice and this permission notice (including the next | |
24 | * paragraph) shall be included in all copies or substantial portions of the | |
25 | * Software. | |
26 | * | |
27 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
28 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
29 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
30 | * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR | |
31 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, | |
32 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR | |
33 | * OTHER DEALINGS IN THE SOFTWARE. | |
34 | */ | |
35 | ||
1da177e4 LT |
36 | #ifndef _DRM_H_ |
37 | #define _DRM_H_ | |
38 | ||
00c96726 DV |
39 | #if defined(__KERNEL__) |
40 | ||
41 | #include <linux/types.h> | |
42 | #include <asm/ioctl.h> | |
43 | typedef unsigned int drm_handle_t; | |
44 | ||
45 | #elif defined(__linux__) | |
1a95916f | 46 | |
1d7f83d5 | 47 | #include <linux/types.h> |
1a95916f KH |
48 | #include <asm/ioctl.h> |
49 | typedef unsigned int drm_handle_t; | |
50 | ||
51 | #else /* One of the BSDs */ | |
1da177e4 | 52 | |
1a95916f KH |
53 | #include <sys/ioccom.h> |
54 | #include <sys/types.h> | |
55 | typedef int8_t __s8; | |
56 | typedef uint8_t __u8; | |
57 | typedef int16_t __s16; | |
58 | typedef uint16_t __u16; | |
59 | typedef int32_t __s32; | |
60 | typedef uint32_t __u32; | |
61 | typedef int64_t __s64; | |
62 | typedef uint64_t __u64; | |
1a2a42c8 | 63 | typedef size_t __kernel_size_t; |
1a95916f KH |
64 | typedef unsigned long drm_handle_t; |
65 | ||
66 | #endif | |
b589ee59 | 67 | |
ebbb0e5c EV |
68 | #if defined(__cplusplus) |
69 | extern "C" { | |
70 | #endif | |
71 | ||
1da177e4 LT |
72 | #define DRM_NAME "drm" /**< Name in kernel, /dev, and /proc */ |
73 | #define DRM_MIN_ORDER 5 /**< At least 2^5 bytes = 32 bytes */ | |
74 | #define DRM_MAX_ORDER 22 /**< Up to 2^22 bytes = 4MB */ | |
75 | #define DRM_RAM_PERCENT 10 /**< How much system ram can we lock? */ | |
76 | ||
b3a80a22 DA |
77 | #define _DRM_LOCK_HELD 0x80000000U /**< Hardware lock is held */ |
78 | #define _DRM_LOCK_CONT 0x40000000U /**< Hardware lock is contended */ | |
1da177e4 LT |
79 | #define _DRM_LOCK_IS_HELD(lock) ((lock) & _DRM_LOCK_HELD) |
80 | #define _DRM_LOCK_IS_CONT(lock) ((lock) & _DRM_LOCK_CONT) | |
81 | #define _DRM_LOCKING_CONTEXT(lock) ((lock) & ~(_DRM_LOCK_HELD|_DRM_LOCK_CONT)) | |
82 | ||
b5e89ed5 DA |
83 | typedef unsigned int drm_context_t; |
84 | typedef unsigned int drm_drawable_t; | |
85 | typedef unsigned int drm_magic_t; | |
1da177e4 LT |
86 | |
87 | /** | |
88 | * Cliprect. | |
b5e89ed5 | 89 | * |
1da177e4 LT |
90 | * \warning: If you change this structure, make sure you change |
91 | * XF86DRIClipRectRec in the server as well | |
92 | * | |
93 | * \note KW: Actually it's illegal to change either for | |
94 | * backwards-compatibility reasons. | |
95 | */ | |
c60ce623 | 96 | struct drm_clip_rect { |
b5e89ed5 DA |
97 | unsigned short x1; |
98 | unsigned short y1; | |
99 | unsigned short x2; | |
100 | unsigned short y2; | |
c60ce623 | 101 | }; |
1da177e4 | 102 | |
bea5679f MD |
103 | /** |
104 | * Drawable information. | |
105 | */ | |
c60ce623 | 106 | struct drm_drawable_info { |
bea5679f | 107 | unsigned int num_rects; |
c60ce623 DA |
108 | struct drm_clip_rect *rects; |
109 | }; | |
bea5679f | 110 | |
1da177e4 LT |
111 | /** |
112 | * Texture region, | |
113 | */ | |
c60ce623 | 114 | struct drm_tex_region { |
b5e89ed5 DA |
115 | unsigned char next; |
116 | unsigned char prev; | |
117 | unsigned char in_use; | |
118 | unsigned char padding; | |
119 | unsigned int age; | |
c60ce623 | 120 | }; |
1da177e4 LT |
121 | |
122 | /** | |
123 | * Hardware lock. | |
124 | * | |
125 | * The lock structure is a simple cache-line aligned integer. To avoid | |
126 | * processor bus contention on a multiprocessor system, there should not be any | |
127 | * other data stored in the same cache line. | |
128 | */ | |
c60ce623 | 129 | struct drm_hw_lock { |
1da177e4 | 130 | __volatile__ unsigned int lock; /**< lock variable */ |
b5e89ed5 | 131 | char padding[60]; /**< Pad to cache line */ |
c60ce623 | 132 | }; |
1da177e4 | 133 | |
1da177e4 LT |
134 | /** |
135 | * DRM_IOCTL_VERSION ioctl argument type. | |
b5e89ed5 | 136 | * |
1da177e4 LT |
137 | * \sa drmGetVersion(). |
138 | */ | |
c60ce623 | 139 | struct drm_version { |
b5e89ed5 DA |
140 | int version_major; /**< Major version */ |
141 | int version_minor; /**< Minor version */ | |
142 | int version_patchlevel; /**< Patch level */ | |
1a2a42c8 | 143 | __kernel_size_t name_len; /**< Length of name buffer */ |
b5e89ed5 | 144 | char __user *name; /**< Name of driver */ |
1a2a42c8 | 145 | __kernel_size_t date_len; /**< Length of date buffer */ |
b5e89ed5 | 146 | char __user *date; /**< User-space buffer to hold date */ |
1a2a42c8 | 147 | __kernel_size_t desc_len; /**< Length of desc buffer */ |
b5e89ed5 | 148 | char __user *desc; /**< User-space buffer to hold desc */ |
c60ce623 | 149 | }; |
1da177e4 | 150 | |
1da177e4 LT |
151 | /** |
152 | * DRM_IOCTL_GET_UNIQUE ioctl argument type. | |
153 | * | |
154 | * \sa drmGetBusid() and drmSetBusId(). | |
155 | */ | |
c60ce623 | 156 | struct drm_unique { |
1a2a42c8 | 157 | __kernel_size_t unique_len; /**< Length of unique */ |
b5e89ed5 | 158 | char __user *unique; /**< Unique name for driver instantiation */ |
c60ce623 | 159 | }; |
1da177e4 | 160 | |
c60ce623 | 161 | struct drm_list { |
b5e89ed5 | 162 | int count; /**< Length of user-space structures */ |
c60ce623 DA |
163 | struct drm_version __user *version; |
164 | }; | |
1da177e4 | 165 | |
c60ce623 | 166 | struct drm_block { |
b5e89ed5 | 167 | int unused; |
c60ce623 | 168 | }; |
1da177e4 | 169 | |
1da177e4 LT |
170 | /** |
171 | * DRM_IOCTL_CONTROL ioctl argument type. | |
172 | * | |
173 | * \sa drmCtlInstHandler() and drmCtlUninstHandler(). | |
174 | */ | |
c60ce623 | 175 | struct drm_control { |
1da177e4 LT |
176 | enum { |
177 | DRM_ADD_COMMAND, | |
178 | DRM_RM_COMMAND, | |
179 | DRM_INST_HANDLER, | |
180 | DRM_UNINST_HANDLER | |
b5e89ed5 DA |
181 | } func; |
182 | int irq; | |
c60ce623 | 183 | }; |
1da177e4 | 184 | |
1da177e4 LT |
185 | /** |
186 | * Type of memory to map. | |
187 | */ | |
c60ce623 | 188 | enum drm_map_type { |
b5e89ed5 DA |
189 | _DRM_FRAME_BUFFER = 0, /**< WC (no caching), no core dump */ |
190 | _DRM_REGISTERS = 1, /**< no caching, no core dump */ | |
191 | _DRM_SHM = 2, /**< shared, cached */ | |
192 | _DRM_AGP = 3, /**< AGP/GART */ | |
2d0f9eaf | 193 | _DRM_SCATTER_GATHER = 4, /**< Scatter/gather memory for PCI DMA */ |
00fdf360 | 194 | _DRM_CONSISTENT = 5 /**< Consistent memory for PCI DMA */ |
c60ce623 | 195 | }; |
1da177e4 | 196 | |
1da177e4 LT |
197 | /** |
198 | * Memory mapping flags. | |
199 | */ | |
c60ce623 | 200 | enum drm_map_flags { |
b5e89ed5 DA |
201 | _DRM_RESTRICTED = 0x01, /**< Cannot be mapped to user-virtual */ |
202 | _DRM_READ_ONLY = 0x02, | |
203 | _DRM_LOCKED = 0x04, /**< shared, cached, locked */ | |
204 | _DRM_KERNEL = 0x08, /**< kernel requires access */ | |
1da177e4 | 205 | _DRM_WRITE_COMBINING = 0x10, /**< use write-combining if available */ |
b5e89ed5 | 206 | _DRM_CONTAINS_LOCK = 0x20, /**< SHM page that contains lock */ |
e3236a11 DA |
207 | _DRM_REMOVABLE = 0x40, /**< Removable mapping */ |
208 | _DRM_DRIVER = 0x80 /**< Managed by driver */ | |
c60ce623 | 209 | }; |
1da177e4 | 210 | |
c60ce623 | 211 | struct drm_ctx_priv_map { |
b5e89ed5 DA |
212 | unsigned int ctx_id; /**< Context requesting private mapping */ |
213 | void *handle; /**< Handle of map */ | |
c60ce623 | 214 | }; |
1da177e4 | 215 | |
1da177e4 LT |
216 | /** |
217 | * DRM_IOCTL_GET_MAP, DRM_IOCTL_ADD_MAP and DRM_IOCTL_RM_MAP ioctls | |
218 | * argument type. | |
219 | * | |
220 | * \sa drmAddMap(). | |
221 | */ | |
c60ce623 | 222 | struct drm_map { |
b5e89ed5 DA |
223 | unsigned long offset; /**< Requested physical address (0 for SAREA)*/ |
224 | unsigned long size; /**< Requested physical size (bytes) */ | |
c60ce623 DA |
225 | enum drm_map_type type; /**< Type of memory to map */ |
226 | enum drm_map_flags flags; /**< Flags */ | |
b5e89ed5 | 227 | void *handle; /**< User-space: "Handle" to pass to mmap() */ |
1da177e4 | 228 | /**< Kernel-space: kernel-virtual address */ |
b5e89ed5 DA |
229 | int mtrr; /**< MTRR slot used */ |
230 | /* Private data */ | |
c60ce623 | 231 | }; |
1da177e4 | 232 | |
1da177e4 LT |
233 | /** |
234 | * DRM_IOCTL_GET_CLIENT ioctl argument type. | |
235 | */ | |
c60ce623 | 236 | struct drm_client { |
b5e89ed5 DA |
237 | int idx; /**< Which client desired? */ |
238 | int auth; /**< Is client authenticated? */ | |
239 | unsigned long pid; /**< Process ID */ | |
240 | unsigned long uid; /**< User ID */ | |
241 | unsigned long magic; /**< Magic */ | |
242 | unsigned long iocs; /**< Ioctl count */ | |
c60ce623 | 243 | }; |
1da177e4 | 244 | |
c60ce623 | 245 | enum drm_stat_type { |
1da177e4 LT |
246 | _DRM_STAT_LOCK, |
247 | _DRM_STAT_OPENS, | |
248 | _DRM_STAT_CLOSES, | |
249 | _DRM_STAT_IOCTLS, | |
250 | _DRM_STAT_LOCKS, | |
251 | _DRM_STAT_UNLOCKS, | |
252 | _DRM_STAT_VALUE, /**< Generic value */ | |
253 | _DRM_STAT_BYTE, /**< Generic byte counter (1024bytes/K) */ | |
254 | _DRM_STAT_COUNT, /**< Generic non-byte counter (1000/k) */ | |
255 | ||
256 | _DRM_STAT_IRQ, /**< IRQ */ | |
257 | _DRM_STAT_PRIMARY, /**< Primary DMA bytes */ | |
258 | _DRM_STAT_SECONDARY, /**< Secondary DMA bytes */ | |
259 | _DRM_STAT_DMA, /**< DMA */ | |
260 | _DRM_STAT_SPECIAL, /**< Special DMA (e.g., priority or polled) */ | |
261 | _DRM_STAT_MISSED /**< Missed DMA opportunity */ | |
b5e89ed5 | 262 | /* Add to the *END* of the list */ |
c60ce623 | 263 | }; |
1da177e4 | 264 | |
1da177e4 LT |
265 | /** |
266 | * DRM_IOCTL_GET_STATS ioctl argument type. | |
267 | */ | |
c60ce623 | 268 | struct drm_stats { |
1da177e4 LT |
269 | unsigned long count; |
270 | struct { | |
b5e89ed5 | 271 | unsigned long value; |
c60ce623 | 272 | enum drm_stat_type type; |
1da177e4 | 273 | } data[15]; |
c60ce623 | 274 | }; |
1da177e4 | 275 | |
1da177e4 LT |
276 | /** |
277 | * Hardware locking flags. | |
278 | */ | |
c60ce623 | 279 | enum drm_lock_flags { |
b5e89ed5 DA |
280 | _DRM_LOCK_READY = 0x01, /**< Wait until hardware is ready for DMA */ |
281 | _DRM_LOCK_QUIESCENT = 0x02, /**< Wait until hardware quiescent */ | |
282 | _DRM_LOCK_FLUSH = 0x04, /**< Flush this context's DMA queue first */ | |
283 | _DRM_LOCK_FLUSH_ALL = 0x08, /**< Flush all DMA queues first */ | |
284 | /* These *HALT* flags aren't supported yet | |
285 | -- they will be used to support the | |
286 | full-screen DGA-like mode. */ | |
1da177e4 LT |
287 | _DRM_HALT_ALL_QUEUES = 0x10, /**< Halt all current and future queues */ |
288 | _DRM_HALT_CUR_QUEUES = 0x20 /**< Halt all current queues */ | |
c60ce623 | 289 | }; |
1da177e4 | 290 | |
1da177e4 LT |
291 | /** |
292 | * DRM_IOCTL_LOCK, DRM_IOCTL_UNLOCK and DRM_IOCTL_FINISH ioctl argument type. | |
b5e89ed5 | 293 | * |
1da177e4 LT |
294 | * \sa drmGetLock() and drmUnlock(). |
295 | */ | |
c60ce623 | 296 | struct drm_lock { |
b5e89ed5 | 297 | int context; |
c60ce623 DA |
298 | enum drm_lock_flags flags; |
299 | }; | |
1da177e4 | 300 | |
1da177e4 LT |
301 | /** |
302 | * DMA flags | |
303 | * | |
b5e89ed5 | 304 | * \warning |
1da177e4 LT |
305 | * These values \e must match xf86drm.h. |
306 | * | |
307 | * \sa drm_dma. | |
308 | */ | |
c60ce623 | 309 | enum drm_dma_flags { |
b5e89ed5 DA |
310 | /* Flags for DMA buffer dispatch */ |
311 | _DRM_DMA_BLOCK = 0x01, /**< | |
1da177e4 | 312 | * Block until buffer dispatched. |
b5e89ed5 | 313 | * |
1da177e4 LT |
314 | * \note The buffer may not yet have |
315 | * been processed by the hardware -- | |
316 | * getting a hardware lock with the | |
317 | * hardware quiescent will ensure | |
318 | * that the buffer has been | |
319 | * processed. | |
320 | */ | |
321 | _DRM_DMA_WHILE_LOCKED = 0x02, /**< Dispatch while lock held */ | |
b5e89ed5 | 322 | _DRM_DMA_PRIORITY = 0x04, /**< High priority dispatch */ |
1da177e4 | 323 | |
b5e89ed5 DA |
324 | /* Flags for DMA buffer request */ |
325 | _DRM_DMA_WAIT = 0x10, /**< Wait for free buffers */ | |
326 | _DRM_DMA_SMALLER_OK = 0x20, /**< Smaller-than-requested buffers OK */ | |
327 | _DRM_DMA_LARGER_OK = 0x40 /**< Larger-than-requested buffers OK */ | |
c60ce623 | 328 | }; |
1da177e4 | 329 | |
1da177e4 LT |
330 | /** |
331 | * DRM_IOCTL_ADD_BUFS and DRM_IOCTL_MARK_BUFS ioctl argument type. | |
332 | * | |
333 | * \sa drmAddBufs(). | |
334 | */ | |
c60ce623 | 335 | struct drm_buf_desc { |
b5e89ed5 DA |
336 | int count; /**< Number of buffers of this size */ |
337 | int size; /**< Size in bytes */ | |
338 | int low_mark; /**< Low water mark */ | |
339 | int high_mark; /**< High water mark */ | |
1da177e4 | 340 | enum { |
b5e89ed5 DA |
341 | _DRM_PAGE_ALIGN = 0x01, /**< Align on page boundaries for DMA */ |
342 | _DRM_AGP_BUFFER = 0x02, /**< Buffer is in AGP space */ | |
343 | _DRM_SG_BUFFER = 0x04, /**< Scatter/gather memory buffer */ | |
3417f33e GS |
344 | _DRM_FB_BUFFER = 0x08, /**< Buffer is in frame buffer */ |
345 | _DRM_PCI_BUFFER_RO = 0x10 /**< Map PCI DMA buffer read-only */ | |
b5e89ed5 DA |
346 | } flags; |
347 | unsigned long agp_start; /**< | |
1da177e4 LT |
348 | * Start address of where the AGP buffers are |
349 | * in the AGP aperture | |
350 | */ | |
c60ce623 | 351 | }; |
1da177e4 | 352 | |
1da177e4 LT |
353 | /** |
354 | * DRM_IOCTL_INFO_BUFS ioctl argument type. | |
355 | */ | |
c60ce623 | 356 | struct drm_buf_info { |
b5e89ed5 | 357 | int count; /**< Entries in list */ |
c60ce623 DA |
358 | struct drm_buf_desc __user *list; |
359 | }; | |
1da177e4 | 360 | |
1da177e4 LT |
361 | /** |
362 | * DRM_IOCTL_FREE_BUFS ioctl argument type. | |
363 | */ | |
c60ce623 | 364 | struct drm_buf_free { |
b5e89ed5 DA |
365 | int count; |
366 | int __user *list; | |
c60ce623 | 367 | }; |
1da177e4 | 368 | |
1da177e4 LT |
369 | /** |
370 | * Buffer information | |
371 | * | |
372 | * \sa drm_buf_map. | |
373 | */ | |
c60ce623 | 374 | struct drm_buf_pub { |
b5e89ed5 DA |
375 | int idx; /**< Index into the master buffer list */ |
376 | int total; /**< Buffer size */ | |
377 | int used; /**< Amount of buffer in use (for DMA) */ | |
378 | void __user *address; /**< Address of buffer */ | |
c60ce623 | 379 | }; |
1da177e4 | 380 | |
1da177e4 LT |
381 | /** |
382 | * DRM_IOCTL_MAP_BUFS ioctl argument type. | |
383 | */ | |
c60ce623 | 384 | struct drm_buf_map { |
b5e89ed5 | 385 | int count; /**< Length of the buffer list */ |
4c4925fa DV |
386 | #ifdef __cplusplus |
387 | void __user *virt; | |
388 | #else | |
b5e89ed5 | 389 | void __user *virtual; /**< Mmap'd area in user-virtual */ |
4c4925fa | 390 | #endif |
c60ce623 DA |
391 | struct drm_buf_pub __user *list; /**< Buffer information */ |
392 | }; | |
1da177e4 | 393 | |
1da177e4 LT |
394 | /** |
395 | * DRM_IOCTL_DMA ioctl argument type. | |
396 | * | |
397 | * Indices here refer to the offset into the buffer list in drm_buf_get. | |
398 | * | |
399 | * \sa drmDMA(). | |
400 | */ | |
c60ce623 | 401 | struct drm_dma { |
b5e89ed5 DA |
402 | int context; /**< Context handle */ |
403 | int send_count; /**< Number of buffers to send */ | |
404 | int __user *send_indices; /**< List of handles to buffers */ | |
405 | int __user *send_sizes; /**< Lengths of data to send */ | |
c60ce623 | 406 | enum drm_dma_flags flags; /**< Flags */ |
b5e89ed5 DA |
407 | int request_count; /**< Number of buffers requested */ |
408 | int request_size; /**< Desired size for buffers */ | |
409 | int __user *request_indices; /**< Buffer information */ | |
410 | int __user *request_sizes; | |
411 | int granted_count; /**< Number of buffers granted */ | |
c60ce623 | 412 | }; |
1da177e4 | 413 | |
c60ce623 | 414 | enum drm_ctx_flags { |
1da177e4 | 415 | _DRM_CONTEXT_PRESERVED = 0x01, |
b5e89ed5 | 416 | _DRM_CONTEXT_2DONLY = 0x02 |
c60ce623 | 417 | }; |
1da177e4 | 418 | |
1da177e4 LT |
419 | /** |
420 | * DRM_IOCTL_ADD_CTX ioctl argument type. | |
421 | * | |
422 | * \sa drmCreateContext() and drmDestroyContext(). | |
423 | */ | |
c60ce623 | 424 | struct drm_ctx { |
b5e89ed5 | 425 | drm_context_t handle; |
c60ce623 DA |
426 | enum drm_ctx_flags flags; |
427 | }; | |
1da177e4 | 428 | |
1da177e4 LT |
429 | /** |
430 | * DRM_IOCTL_RES_CTX ioctl argument type. | |
431 | */ | |
c60ce623 | 432 | struct drm_ctx_res { |
b5e89ed5 | 433 | int count; |
c60ce623 DA |
434 | struct drm_ctx __user *contexts; |
435 | }; | |
1da177e4 | 436 | |
1da177e4 LT |
437 | /** |
438 | * DRM_IOCTL_ADD_DRAW and DRM_IOCTL_RM_DRAW ioctl argument type. | |
439 | */ | |
c60ce623 | 440 | struct drm_draw { |
b5e89ed5 | 441 | drm_drawable_t handle; |
c60ce623 | 442 | }; |
1da177e4 | 443 | |
bea5679f MD |
444 | /** |
445 | * DRM_IOCTL_UPDATE_DRAW ioctl argument type. | |
446 | */ | |
447 | typedef enum { | |
00fdf360 | 448 | DRM_DRAWABLE_CLIPRECTS |
bea5679f MD |
449 | } drm_drawable_info_type_t; |
450 | ||
c60ce623 | 451 | struct drm_update_draw { |
bea5679f MD |
452 | drm_drawable_t handle; |
453 | unsigned int type; | |
454 | unsigned int num; | |
455 | unsigned long long data; | |
c60ce623 | 456 | }; |
bea5679f | 457 | |
1da177e4 LT |
458 | /** |
459 | * DRM_IOCTL_GET_MAGIC and DRM_IOCTL_AUTH_MAGIC ioctl argument type. | |
460 | */ | |
c60ce623 | 461 | struct drm_auth { |
b5e89ed5 | 462 | drm_magic_t magic; |
c60ce623 | 463 | }; |
1da177e4 | 464 | |
1da177e4 LT |
465 | /** |
466 | * DRM_IOCTL_IRQ_BUSID ioctl argument type. | |
467 | * | |
468 | * \sa drmGetInterruptFromBusID(). | |
469 | */ | |
c60ce623 | 470 | struct drm_irq_busid { |
1da177e4 LT |
471 | int irq; /**< IRQ number */ |
472 | int busnum; /**< bus number */ | |
473 | int devnum; /**< device number */ | |
474 | int funcnum; /**< function number */ | |
c60ce623 | 475 | }; |
1da177e4 | 476 | |
c60ce623 | 477 | enum drm_vblank_seq_type { |
b5e89ed5 DA |
478 | _DRM_VBLANK_ABSOLUTE = 0x0, /**< Wait for specific vblank sequence number */ |
479 | _DRM_VBLANK_RELATIVE = 0x1, /**< Wait for given number of vblanks */ | |
51eab416 DA |
480 | /* bits 1-6 are reserved for high crtcs */ |
481 | _DRM_VBLANK_HIGH_CRTC_MASK = 0x0000003e, | |
c9a9c5e0 | 482 | _DRM_VBLANK_EVENT = 0x4000000, /**< Send event instead of blocking */ |
0a3e67a4 | 483 | _DRM_VBLANK_FLIP = 0x8000000, /**< Scheduled buffer swap should flip */ |
ab285d74 | 484 | _DRM_VBLANK_NEXTONMISS = 0x10000000, /**< If missed, wait for next vblank */ |
776c9443 | 485 | _DRM_VBLANK_SECONDARY = 0x20000000, /**< Secondary display controller */ |
30b23634 | 486 | _DRM_VBLANK_SIGNAL = 0x40000000 /**< Send signal instead of blocking, unsupported */ |
c60ce623 | 487 | }; |
51eab416 | 488 | #define _DRM_VBLANK_HIGH_CRTC_SHIFT 1 |
1da177e4 | 489 | |
776c9443 | 490 | #define _DRM_VBLANK_TYPES_MASK (_DRM_VBLANK_ABSOLUTE | _DRM_VBLANK_RELATIVE) |
c9a9c5e0 KH |
491 | #define _DRM_VBLANK_FLAGS_MASK (_DRM_VBLANK_EVENT | _DRM_VBLANK_SIGNAL | \ |
492 | _DRM_VBLANK_SECONDARY | _DRM_VBLANK_NEXTONMISS) | |
1da177e4 | 493 | |
1da177e4 | 494 | struct drm_wait_vblank_request { |
c60ce623 | 495 | enum drm_vblank_seq_type type; |
1da177e4 LT |
496 | unsigned int sequence; |
497 | unsigned long signal; | |
498 | }; | |
499 | ||
1da177e4 | 500 | struct drm_wait_vblank_reply { |
c60ce623 | 501 | enum drm_vblank_seq_type type; |
1da177e4 LT |
502 | unsigned int sequence; |
503 | long tval_sec; | |
504 | long tval_usec; | |
505 | }; | |
506 | ||
1da177e4 LT |
507 | /** |
508 | * DRM_IOCTL_WAIT_VBLANK ioctl argument type. | |
509 | * | |
510 | * \sa drmWaitVBlank(). | |
511 | */ | |
c60ce623 | 512 | union drm_wait_vblank { |
1da177e4 LT |
513 | struct drm_wait_vblank_request request; |
514 | struct drm_wait_vblank_reply reply; | |
c60ce623 | 515 | }; |
1da177e4 | 516 | |
0a3e67a4 JB |
517 | #define _DRM_PRE_MODESET 1 |
518 | #define _DRM_POST_MODESET 2 | |
519 | ||
520 | /** | |
521 | * DRM_IOCTL_MODESET_CTL ioctl argument type | |
522 | * | |
523 | * \sa drmModesetCtl(). | |
524 | */ | |
525 | struct drm_modeset_ctl { | |
1d7f83d5 AB |
526 | __u32 crtc; |
527 | __u32 cmd; | |
0a3e67a4 JB |
528 | }; |
529 | ||
1da177e4 LT |
530 | /** |
531 | * DRM_IOCTL_AGP_ENABLE ioctl argument type. | |
532 | * | |
533 | * \sa drmAgpEnable(). | |
534 | */ | |
c60ce623 | 535 | struct drm_agp_mode { |
1da177e4 | 536 | unsigned long mode; /**< AGP mode */ |
c60ce623 | 537 | }; |
1da177e4 | 538 | |
1da177e4 LT |
539 | /** |
540 | * DRM_IOCTL_AGP_ALLOC and DRM_IOCTL_AGP_FREE ioctls argument type. | |
541 | * | |
542 | * \sa drmAgpAlloc() and drmAgpFree(). | |
543 | */ | |
c60ce623 | 544 | struct drm_agp_buffer { |
1da177e4 LT |
545 | unsigned long size; /**< In bytes -- will round to page boundary */ |
546 | unsigned long handle; /**< Used for binding / unbinding */ | |
b5e89ed5 DA |
547 | unsigned long type; /**< Type of memory to allocate */ |
548 | unsigned long physical; /**< Physical used by i810 */ | |
c60ce623 | 549 | }; |
1da177e4 | 550 | |
1da177e4 LT |
551 | /** |
552 | * DRM_IOCTL_AGP_BIND and DRM_IOCTL_AGP_UNBIND ioctls argument type. | |
553 | * | |
554 | * \sa drmAgpBind() and drmAgpUnbind(). | |
555 | */ | |
c60ce623 | 556 | struct drm_agp_binding { |
b5e89ed5 | 557 | unsigned long handle; /**< From drm_agp_buffer */ |
1da177e4 | 558 | unsigned long offset; /**< In bytes -- will round to page boundary */ |
c60ce623 | 559 | }; |
1da177e4 | 560 | |
1da177e4 LT |
561 | /** |
562 | * DRM_IOCTL_AGP_INFO ioctl argument type. | |
563 | * | |
564 | * \sa drmAgpVersionMajor(), drmAgpVersionMinor(), drmAgpGetMode(), | |
565 | * drmAgpBase(), drmAgpSize(), drmAgpMemoryUsed(), drmAgpMemoryAvail(), | |
566 | * drmAgpVendorId() and drmAgpDeviceId(). | |
567 | */ | |
c60ce623 | 568 | struct drm_agp_info { |
b5e89ed5 DA |
569 | int agp_version_major; |
570 | int agp_version_minor; | |
571 | unsigned long mode; | |
572 | unsigned long aperture_base; /* physical address */ | |
573 | unsigned long aperture_size; /* bytes */ | |
574 | unsigned long memory_allowed; /* bytes */ | |
575 | unsigned long memory_used; | |
576 | ||
577 | /* PCI information */ | |
1da177e4 LT |
578 | unsigned short id_vendor; |
579 | unsigned short id_device; | |
c60ce623 | 580 | }; |
1da177e4 | 581 | |
1da177e4 LT |
582 | /** |
583 | * DRM_IOCTL_SG_ALLOC ioctl argument type. | |
584 | */ | |
c60ce623 | 585 | struct drm_scatter_gather { |
1da177e4 LT |
586 | unsigned long size; /**< In bytes -- will round to page boundary */ |
587 | unsigned long handle; /**< Used for mapping / unmapping */ | |
c60ce623 | 588 | }; |
1da177e4 LT |
589 | |
590 | /** | |
591 | * DRM_IOCTL_SET_VERSION ioctl argument type. | |
592 | */ | |
c60ce623 | 593 | struct drm_set_version { |
1da177e4 LT |
594 | int drm_di_major; |
595 | int drm_di_minor; | |
596 | int drm_dd_major; | |
597 | int drm_dd_minor; | |
c60ce623 | 598 | }; |
1da177e4 | 599 | |
673a394b EA |
600 | /** DRM_IOCTL_GEM_CLOSE ioctl argument type */ |
601 | struct drm_gem_close { | |
602 | /** Handle of the object to be closed. */ | |
1d7f83d5 AB |
603 | __u32 handle; |
604 | __u32 pad; | |
673a394b EA |
605 | }; |
606 | ||
607 | /** DRM_IOCTL_GEM_FLINK ioctl argument type */ | |
608 | struct drm_gem_flink { | |
609 | /** Handle for the object being named */ | |
1d7f83d5 | 610 | __u32 handle; |
673a394b EA |
611 | |
612 | /** Returned global name */ | |
1d7f83d5 | 613 | __u32 name; |
673a394b EA |
614 | }; |
615 | ||
616 | /** DRM_IOCTL_GEM_OPEN ioctl argument type */ | |
617 | struct drm_gem_open { | |
618 | /** Name of object being opened */ | |
1d7f83d5 | 619 | __u32 name; |
673a394b EA |
620 | |
621 | /** Returned handle for the object */ | |
1d7f83d5 | 622 | __u32 handle; |
673a394b EA |
623 | |
624 | /** Returned size of the object */ | |
1d7f83d5 | 625 | __u64 size; |
673a394b EA |
626 | }; |
627 | ||
a99b57db DL |
628 | #define DRM_CAP_DUMB_BUFFER 0x1 |
629 | #define DRM_CAP_VBLANK_HIGH_CRTC 0x2 | |
630 | #define DRM_CAP_DUMB_PREFERRED_DEPTH 0x3 | |
631 | #define DRM_CAP_DUMB_PREFER_SHADOW 0x4 | |
632 | #define DRM_CAP_PRIME 0x5 | |
633 | #define DRM_PRIME_CAP_IMPORT 0x1 | |
634 | #define DRM_PRIME_CAP_EXPORT 0x2 | |
635 | #define DRM_CAP_TIMESTAMP_MONOTONIC 0x6 | |
636 | #define DRM_CAP_ASYNC_PAGE_FLIP 0x7 | |
bfe8b573 LD |
637 | /* |
638 | * The CURSOR_WIDTH and CURSOR_HEIGHT capabilities return a valid widthxheight | |
639 | * combination for the hardware cursor. The intention is that a hardware | |
640 | * agnostic userspace can query a cursor plane size to use. | |
641 | * | |
642 | * Note that the cross-driver contract is to merely return a valid size; | |
643 | * drivers are free to attach another meaning on top, eg. i915 returns the | |
644 | * maximum plane size. | |
645 | */ | |
8716ed4e AD |
646 | #define DRM_CAP_CURSOR_WIDTH 0x8 |
647 | #define DRM_CAP_CURSOR_HEIGHT 0x9 | |
e3eb3250 | 648 | #define DRM_CAP_ADDFB2_MODIFIERS 0x10 |
f837297a | 649 | #define DRM_CAP_PAGE_FLIP_TARGET 0x11 |
a99b57db | 650 | |
9f35421e BS |
651 | /** DRM_IOCTL_GET_CAP ioctl argument type */ |
652 | struct drm_get_cap { | |
653 | __u64 capability; | |
654 | __u64 value; | |
655 | }; | |
656 | ||
61d8e328 DL |
657 | /** |
658 | * DRM_CLIENT_CAP_STEREO_3D | |
659 | * | |
660 | * if set to 1, the DRM core will expose the stereo 3D capabilities of the | |
661 | * monitor by advertising the supported 3D layouts in the flags of struct | |
662 | * drm_mode_modeinfo. | |
663 | */ | |
664 | #define DRM_CLIENT_CAP_STEREO_3D 1 | |
665 | ||
681e7ec7 MR |
666 | /** |
667 | * DRM_CLIENT_CAP_UNIVERSAL_PLANES | |
668 | * | |
669 | * If set to 1, the DRM core will expose all planes (overlay, primary, and | |
670 | * cursor) to userspace. | |
671 | */ | |
672 | #define DRM_CLIENT_CAP_UNIVERSAL_PLANES 2 | |
673 | ||
88a48e29 RC |
674 | /** |
675 | * DRM_CLIENT_CAP_ATOMIC | |
676 | * | |
677 | * If set to 1, the DRM core will expose atomic properties to userspace | |
678 | */ | |
679 | #define DRM_CLIENT_CAP_ATOMIC 3 | |
680 | ||
1c0814fe DL |
681 | /** DRM_IOCTL_SET_CLIENT_CAP ioctl argument type */ |
682 | struct drm_set_client_cap { | |
683 | __u64 capability; | |
684 | __u64 value; | |
685 | }; | |
686 | ||
bfe981a0 | 687 | #define DRM_RDWR O_RDWR |
3248877e DA |
688 | #define DRM_CLOEXEC O_CLOEXEC |
689 | struct drm_prime_handle { | |
690 | __u32 handle; | |
691 | ||
692 | /** Flags.. only applicable for handle->fd */ | |
693 | __u32 flags; | |
694 | ||
695 | /** Returned dmabuf file descriptor */ | |
696 | __s32 fd; | |
697 | }; | |
698 | ||
ebbb0e5c EV |
699 | #if defined(__cplusplus) |
700 | } | |
701 | #endif | |
702 | ||
0b1ccd49 | 703 | #include "drm_mode.h" |
f453ba04 | 704 | |
ebbb0e5c EV |
705 | #if defined(__cplusplus) |
706 | extern "C" { | |
707 | #endif | |
708 | ||
1da177e4 LT |
709 | #define DRM_IOCTL_BASE 'd' |
710 | #define DRM_IO(nr) _IO(DRM_IOCTL_BASE,nr) | |
711 | #define DRM_IOR(nr,type) _IOR(DRM_IOCTL_BASE,nr,type) | |
712 | #define DRM_IOW(nr,type) _IOW(DRM_IOCTL_BASE,nr,type) | |
713 | #define DRM_IOWR(nr,type) _IOWR(DRM_IOCTL_BASE,nr,type) | |
714 | ||
c60ce623 DA |
715 | #define DRM_IOCTL_VERSION DRM_IOWR(0x00, struct drm_version) |
716 | #define DRM_IOCTL_GET_UNIQUE DRM_IOWR(0x01, struct drm_unique) | |
717 | #define DRM_IOCTL_GET_MAGIC DRM_IOR( 0x02, struct drm_auth) | |
718 | #define DRM_IOCTL_IRQ_BUSID DRM_IOWR(0x03, struct drm_irq_busid) | |
719 | #define DRM_IOCTL_GET_MAP DRM_IOWR(0x04, struct drm_map) | |
720 | #define DRM_IOCTL_GET_CLIENT DRM_IOWR(0x05, struct drm_client) | |
721 | #define DRM_IOCTL_GET_STATS DRM_IOR( 0x06, struct drm_stats) | |
722 | #define DRM_IOCTL_SET_VERSION DRM_IOWR(0x07, struct drm_set_version) | |
0a3e67a4 | 723 | #define DRM_IOCTL_MODESET_CTL DRM_IOW(0x08, struct drm_modeset_ctl) |
673a394b EA |
724 | #define DRM_IOCTL_GEM_CLOSE DRM_IOW (0x09, struct drm_gem_close) |
725 | #define DRM_IOCTL_GEM_FLINK DRM_IOWR(0x0a, struct drm_gem_flink) | |
726 | #define DRM_IOCTL_GEM_OPEN DRM_IOWR(0x0b, struct drm_gem_open) | |
9f35421e | 727 | #define DRM_IOCTL_GET_CAP DRM_IOWR(0x0c, struct drm_get_cap) |
1c0814fe | 728 | #define DRM_IOCTL_SET_CLIENT_CAP DRM_IOW( 0x0d, struct drm_set_client_cap) |
c60ce623 DA |
729 | |
730 | #define DRM_IOCTL_SET_UNIQUE DRM_IOW( 0x10, struct drm_unique) | |
731 | #define DRM_IOCTL_AUTH_MAGIC DRM_IOW( 0x11, struct drm_auth) | |
732 | #define DRM_IOCTL_BLOCK DRM_IOWR(0x12, struct drm_block) | |
733 | #define DRM_IOCTL_UNBLOCK DRM_IOWR(0x13, struct drm_block) | |
734 | #define DRM_IOCTL_CONTROL DRM_IOW( 0x14, struct drm_control) | |
735 | #define DRM_IOCTL_ADD_MAP DRM_IOWR(0x15, struct drm_map) | |
736 | #define DRM_IOCTL_ADD_BUFS DRM_IOWR(0x16, struct drm_buf_desc) | |
737 | #define DRM_IOCTL_MARK_BUFS DRM_IOW( 0x17, struct drm_buf_desc) | |
738 | #define DRM_IOCTL_INFO_BUFS DRM_IOWR(0x18, struct drm_buf_info) | |
739 | #define DRM_IOCTL_MAP_BUFS DRM_IOWR(0x19, struct drm_buf_map) | |
740 | #define DRM_IOCTL_FREE_BUFS DRM_IOW( 0x1a, struct drm_buf_free) | |
741 | ||
742 | #define DRM_IOCTL_RM_MAP DRM_IOW( 0x1b, struct drm_map) | |
743 | ||
744 | #define DRM_IOCTL_SET_SAREA_CTX DRM_IOW( 0x1c, struct drm_ctx_priv_map) | |
745 | #define DRM_IOCTL_GET_SAREA_CTX DRM_IOWR(0x1d, struct drm_ctx_priv_map) | |
746 | ||
7c1c2871 DA |
747 | #define DRM_IOCTL_SET_MASTER DRM_IO(0x1e) |
748 | #define DRM_IOCTL_DROP_MASTER DRM_IO(0x1f) | |
749 | ||
c60ce623 DA |
750 | #define DRM_IOCTL_ADD_CTX DRM_IOWR(0x20, struct drm_ctx) |
751 | #define DRM_IOCTL_RM_CTX DRM_IOWR(0x21, struct drm_ctx) | |
752 | #define DRM_IOCTL_MOD_CTX DRM_IOW( 0x22, struct drm_ctx) | |
753 | #define DRM_IOCTL_GET_CTX DRM_IOWR(0x23, struct drm_ctx) | |
754 | #define DRM_IOCTL_SWITCH_CTX DRM_IOW( 0x24, struct drm_ctx) | |
755 | #define DRM_IOCTL_NEW_CTX DRM_IOW( 0x25, struct drm_ctx) | |
756 | #define DRM_IOCTL_RES_CTX DRM_IOWR(0x26, struct drm_ctx_res) | |
757 | #define DRM_IOCTL_ADD_DRAW DRM_IOWR(0x27, struct drm_draw) | |
758 | #define DRM_IOCTL_RM_DRAW DRM_IOWR(0x28, struct drm_draw) | |
759 | #define DRM_IOCTL_DMA DRM_IOWR(0x29, struct drm_dma) | |
760 | #define DRM_IOCTL_LOCK DRM_IOW( 0x2a, struct drm_lock) | |
761 | #define DRM_IOCTL_UNLOCK DRM_IOW( 0x2b, struct drm_lock) | |
762 | #define DRM_IOCTL_FINISH DRM_IOW( 0x2c, struct drm_lock) | |
1da177e4 | 763 | |
3248877e DA |
764 | #define DRM_IOCTL_PRIME_HANDLE_TO_FD DRM_IOWR(0x2d, struct drm_prime_handle) |
765 | #define DRM_IOCTL_PRIME_FD_TO_HANDLE DRM_IOWR(0x2e, struct drm_prime_handle) | |
ba4420c2 | 766 | |
1da177e4 LT |
767 | #define DRM_IOCTL_AGP_ACQUIRE DRM_IO( 0x30) |
768 | #define DRM_IOCTL_AGP_RELEASE DRM_IO( 0x31) | |
c60ce623 DA |
769 | #define DRM_IOCTL_AGP_ENABLE DRM_IOW( 0x32, struct drm_agp_mode) |
770 | #define DRM_IOCTL_AGP_INFO DRM_IOR( 0x33, struct drm_agp_info) | |
771 | #define DRM_IOCTL_AGP_ALLOC DRM_IOWR(0x34, struct drm_agp_buffer) | |
772 | #define DRM_IOCTL_AGP_FREE DRM_IOW( 0x35, struct drm_agp_buffer) | |
773 | #define DRM_IOCTL_AGP_BIND DRM_IOW( 0x36, struct drm_agp_binding) | |
774 | #define DRM_IOCTL_AGP_UNBIND DRM_IOW( 0x37, struct drm_agp_binding) | |
1da177e4 | 775 | |
b5543059 | 776 | #define DRM_IOCTL_SG_ALLOC DRM_IOWR(0x38, struct drm_scatter_gather) |
c60ce623 | 777 | #define DRM_IOCTL_SG_FREE DRM_IOW( 0x39, struct drm_scatter_gather) |
1da177e4 | 778 | |
c60ce623 | 779 | #define DRM_IOCTL_WAIT_VBLANK DRM_IOWR(0x3a, union drm_wait_vblank) |
1da177e4 | 780 | |
c60ce623 | 781 | #define DRM_IOCTL_UPDATE_DRAW DRM_IOW(0x3f, struct drm_update_draw) |
bea5679f | 782 | |
f453ba04 DA |
783 | #define DRM_IOCTL_MODE_GETRESOURCES DRM_IOWR(0xA0, struct drm_mode_card_res) |
784 | #define DRM_IOCTL_MODE_GETCRTC DRM_IOWR(0xA1, struct drm_mode_crtc) | |
785 | #define DRM_IOCTL_MODE_SETCRTC DRM_IOWR(0xA2, struct drm_mode_crtc) | |
786 | #define DRM_IOCTL_MODE_CURSOR DRM_IOWR(0xA3, struct drm_mode_cursor) | |
787 | #define DRM_IOCTL_MODE_GETGAMMA DRM_IOWR(0xA4, struct drm_mode_crtc_lut) | |
788 | #define DRM_IOCTL_MODE_SETGAMMA DRM_IOWR(0xA5, struct drm_mode_crtc_lut) | |
789 | #define DRM_IOCTL_MODE_GETENCODER DRM_IOWR(0xA6, struct drm_mode_get_encoder) | |
790 | #define DRM_IOCTL_MODE_GETCONNECTOR DRM_IOWR(0xA7, struct drm_mode_get_connector) | |
c55b6b3d VS |
791 | #define DRM_IOCTL_MODE_ATTACHMODE DRM_IOWR(0xA8, struct drm_mode_mode_cmd) /* deprecated (never worked) */ |
792 | #define DRM_IOCTL_MODE_DETACHMODE DRM_IOWR(0xA9, struct drm_mode_mode_cmd) /* deprecated (never worked) */ | |
f453ba04 DA |
793 | |
794 | #define DRM_IOCTL_MODE_GETPROPERTY DRM_IOWR(0xAA, struct drm_mode_get_property) | |
795 | #define DRM_IOCTL_MODE_SETPROPERTY DRM_IOWR(0xAB, struct drm_mode_connector_set_property) | |
796 | #define DRM_IOCTL_MODE_GETPROPBLOB DRM_IOWR(0xAC, struct drm_mode_get_blob) | |
797 | #define DRM_IOCTL_MODE_GETFB DRM_IOWR(0xAD, struct drm_mode_fb_cmd) | |
798 | #define DRM_IOCTL_MODE_ADDFB DRM_IOWR(0xAE, struct drm_mode_fb_cmd) | |
799 | #define DRM_IOCTL_MODE_RMFB DRM_IOWR(0xAF, unsigned int) | |
d91d8a3f | 800 | #define DRM_IOCTL_MODE_PAGE_FLIP DRM_IOWR(0xB0, struct drm_mode_crtc_page_flip) |
884840aa | 801 | #define DRM_IOCTL_MODE_DIRTYFB DRM_IOWR(0xB1, struct drm_mode_fb_dirty_cmd) |
f453ba04 | 802 | |
ff72145b DA |
803 | #define DRM_IOCTL_MODE_CREATE_DUMB DRM_IOWR(0xB2, struct drm_mode_create_dumb) |
804 | #define DRM_IOCTL_MODE_MAP_DUMB DRM_IOWR(0xB3, struct drm_mode_map_dumb) | |
805 | #define DRM_IOCTL_MODE_DESTROY_DUMB DRM_IOWR(0xB4, struct drm_mode_destroy_dumb) | |
8cf5c917 JB |
806 | #define DRM_IOCTL_MODE_GETPLANERESOURCES DRM_IOWR(0xB5, struct drm_mode_get_plane_res) |
807 | #define DRM_IOCTL_MODE_GETPLANE DRM_IOWR(0xB6, struct drm_mode_get_plane) | |
808 | #define DRM_IOCTL_MODE_SETPLANE DRM_IOWR(0xB7, struct drm_mode_set_plane) | |
308e5bcb | 809 | #define DRM_IOCTL_MODE_ADDFB2 DRM_IOWR(0xB8, struct drm_mode_fb_cmd2) |
c543188a PZ |
810 | #define DRM_IOCTL_MODE_OBJ_GETPROPERTIES DRM_IOWR(0xB9, struct drm_mode_obj_get_properties) |
811 | #define DRM_IOCTL_MODE_OBJ_SETPROPERTY DRM_IOWR(0xBA, struct drm_mode_obj_set_property) | |
4c813d4d | 812 | #define DRM_IOCTL_MODE_CURSOR2 DRM_IOWR(0xBB, struct drm_mode_cursor2) |
d34f20d6 | 813 | #define DRM_IOCTL_MODE_ATOMIC DRM_IOWR(0xBC, struct drm_mode_atomic) |
e2f5d2ea DS |
814 | #define DRM_IOCTL_MODE_CREATEPROPBLOB DRM_IOWR(0xBD, struct drm_mode_create_blob) |
815 | #define DRM_IOCTL_MODE_DESTROYPROPBLOB DRM_IOWR(0xBE, struct drm_mode_destroy_blob) | |
ff72145b | 816 | |
1da177e4 LT |
817 | /** |
818 | * Device specific ioctls should only be in their respective headers | |
735b9ffa | 819 | * The device specific ioctl range is from 0x40 to 0x9f. |
99da6d86 | 820 | * Generic IOCTLS restart at 0xA0. |
1da177e4 LT |
821 | * |
822 | * \sa drmCommandNone(), drmCommandRead(), drmCommandWrite(), and | |
823 | * drmCommandReadWrite(). | |
824 | */ | |
825 | #define DRM_COMMAND_BASE 0x40 | |
99da6d86 | 826 | #define DRM_COMMAND_END 0xA0 |
1da177e4 | 827 | |
c9a9c5e0 KH |
828 | /** |
829 | * Header for events written back to userspace on the drm fd. The | |
830 | * type defines the type of event, the length specifies the total | |
831 | * length of the event (including the header), and user_data is | |
832 | * typically a 64 bit value passed with the ioctl that triggered the | |
833 | * event. A read on the drm fd will always only return complete | |
834 | * events, that is, if for example the read buffer is 100 bytes, and | |
835 | * there are two 64 byte events pending, only one will be returned. | |
836 | * | |
837 | * Event types 0 - 0x7fffffff are generic drm events, 0x80000000 and | |
838 | * up are chipset specific. | |
839 | */ | |
840 | struct drm_event { | |
841 | __u32 type; | |
842 | __u32 length; | |
843 | }; | |
844 | ||
845 | #define DRM_EVENT_VBLANK 0x01 | |
7bd4d7be | 846 | #define DRM_EVENT_FLIP_COMPLETE 0x02 |
c9a9c5e0 KH |
847 | |
848 | struct drm_event_vblank { | |
849 | struct drm_event base; | |
850 | __u64 user_data; | |
851 | __u32 tv_sec; | |
852 | __u32 tv_usec; | |
853 | __u32 sequence; | |
854 | __u32 reserved; | |
855 | }; | |
856 | ||
c60ce623 DA |
857 | /* typedef area */ |
858 | #ifndef __KERNEL__ | |
859 | typedef struct drm_clip_rect drm_clip_rect_t; | |
860 | typedef struct drm_drawable_info drm_drawable_info_t; | |
861 | typedef struct drm_tex_region drm_tex_region_t; | |
862 | typedef struct drm_hw_lock drm_hw_lock_t; | |
863 | typedef struct drm_version drm_version_t; | |
864 | typedef struct drm_unique drm_unique_t; | |
865 | typedef struct drm_list drm_list_t; | |
866 | typedef struct drm_block drm_block_t; | |
867 | typedef struct drm_control drm_control_t; | |
868 | typedef enum drm_map_type drm_map_type_t; | |
869 | typedef enum drm_map_flags drm_map_flags_t; | |
870 | typedef struct drm_ctx_priv_map drm_ctx_priv_map_t; | |
871 | typedef struct drm_map drm_map_t; | |
872 | typedef struct drm_client drm_client_t; | |
873 | typedef enum drm_stat_type drm_stat_type_t; | |
874 | typedef struct drm_stats drm_stats_t; | |
875 | typedef enum drm_lock_flags drm_lock_flags_t; | |
876 | typedef struct drm_lock drm_lock_t; | |
877 | typedef enum drm_dma_flags drm_dma_flags_t; | |
878 | typedef struct drm_buf_desc drm_buf_desc_t; | |
879 | typedef struct drm_buf_info drm_buf_info_t; | |
880 | typedef struct drm_buf_free drm_buf_free_t; | |
881 | typedef struct drm_buf_pub drm_buf_pub_t; | |
882 | typedef struct drm_buf_map drm_buf_map_t; | |
883 | typedef struct drm_dma drm_dma_t; | |
884 | typedef union drm_wait_vblank drm_wait_vblank_t; | |
885 | typedef struct drm_agp_mode drm_agp_mode_t; | |
886 | typedef enum drm_ctx_flags drm_ctx_flags_t; | |
887 | typedef struct drm_ctx drm_ctx_t; | |
888 | typedef struct drm_ctx_res drm_ctx_res_t; | |
889 | typedef struct drm_draw drm_draw_t; | |
890 | typedef struct drm_update_draw drm_update_draw_t; | |
891 | typedef struct drm_auth drm_auth_t; | |
892 | typedef struct drm_irq_busid drm_irq_busid_t; | |
893 | typedef enum drm_vblank_seq_type drm_vblank_seq_type_t; | |
894 | ||
895 | typedef struct drm_agp_buffer drm_agp_buffer_t; | |
896 | typedef struct drm_agp_binding drm_agp_binding_t; | |
897 | typedef struct drm_agp_info drm_agp_info_t; | |
898 | typedef struct drm_scatter_gather drm_scatter_gather_t; | |
899 | typedef struct drm_set_version drm_set_version_t; | |
900 | #endif | |
901 | ||
ebbb0e5c EV |
902 | #if defined(__cplusplus) |
903 | } | |
904 | #endif | |
905 | ||
1da177e4 | 906 | #endif |