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f453ba04
DA
1/*
2 * Copyright (c) 2007 Dave Airlie <airlied@linux.ie>
3 * Copyright (c) 2007 Jakob Bornecrantz <wallbraker@gmail.com>
4 * Copyright (c) 2008 Red Hat Inc.
5 * Copyright (c) 2007-2008 Tungsten Graphics, Inc., Cedar Park, TX., USA
6 * Copyright (c) 2007-2008 Intel Corporation
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice shall be included in
16 * all copies or substantial portions of the Software.
17 *
18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
20 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
21 * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
22 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
23 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * IN THE SOFTWARE.
25 */
26
27#ifndef _DRM_MODE_H
28#define _DRM_MODE_H
29
abd5422d 30#include "drm.h"
10db4e1e 31
ebbb0e5c
EV
32#if defined(__cplusplus)
33extern "C" {
34#endif
35
e0c8463a
JB
36#define DRM_DISPLAY_INFO_LEN 32
37#define DRM_CONNECTOR_NAME_LEN 32
38#define DRM_DISPLAY_MODE_LEN 32
39#define DRM_PROP_NAME_LEN 32
f453ba04
DA
40
41#define DRM_MODE_TYPE_BUILTIN (1<<0)
42#define DRM_MODE_TYPE_CLOCK_C ((1<<1) | DRM_MODE_TYPE_BUILTIN)
43#define DRM_MODE_TYPE_CRTC_C ((1<<2) | DRM_MODE_TYPE_BUILTIN)
44#define DRM_MODE_TYPE_PREFERRED (1<<3)
45#define DRM_MODE_TYPE_DEFAULT (1<<4)
46#define DRM_MODE_TYPE_USERDEF (1<<5)
47#define DRM_MODE_TYPE_DRIVER (1<<6)
48
49/* Video mode flags */
91d5ee04
VS
50/* bit compatible with the xrandr RR_ definitions (bits 0-13)
51 *
52 * ABI warning: Existing userspace really expects
53 * the mode flags to match the xrandr definitions. Any
54 * changes that don't match the xrandr definitions will
55 * likely need a new client cap or some other mechanism
56 * to avoid breaking existing userspace. This includes
57 * allocating new flags in the previously unused bits!
58 */
4aa17cf0
DL
59#define DRM_MODE_FLAG_PHSYNC (1<<0)
60#define DRM_MODE_FLAG_NHSYNC (1<<1)
61#define DRM_MODE_FLAG_PVSYNC (1<<2)
62#define DRM_MODE_FLAG_NVSYNC (1<<3)
63#define DRM_MODE_FLAG_INTERLACE (1<<4)
64#define DRM_MODE_FLAG_DBLSCAN (1<<5)
65#define DRM_MODE_FLAG_CSYNC (1<<6)
66#define DRM_MODE_FLAG_PCSYNC (1<<7)
67#define DRM_MODE_FLAG_NCSYNC (1<<8)
68#define DRM_MODE_FLAG_HSKEW (1<<9) /* hskew provided */
69#define DRM_MODE_FLAG_BCAST (1<<10)
70#define DRM_MODE_FLAG_PIXMUX (1<<11)
71#define DRM_MODE_FLAG_DBLCLK (1<<12)
72#define DRM_MODE_FLAG_CLKDIV2 (1<<13)
5848ad40
DL
73 /*
74 * When adding a new stereo mode don't forget to adjust DRM_MODE_FLAGS_3D_MAX
75 * (define not exposed to user space).
76 */
f7e121b7
DL
77#define DRM_MODE_FLAG_3D_MASK (0x1f<<14)
78#define DRM_MODE_FLAG_3D_NONE (0<<14)
79#define DRM_MODE_FLAG_3D_FRAME_PACKING (1<<14)
80#define DRM_MODE_FLAG_3D_FIELD_ALTERNATIVE (2<<14)
81#define DRM_MODE_FLAG_3D_LINE_ALTERNATIVE (3<<14)
82#define DRM_MODE_FLAG_3D_SIDE_BY_SIDE_FULL (4<<14)
83#define DRM_MODE_FLAG_3D_L_DEPTH (5<<14)
84#define DRM_MODE_FLAG_3D_L_DEPTH_GFX_GFX_DEPTH (6<<14)
85#define DRM_MODE_FLAG_3D_TOP_AND_BOTTOM (7<<14)
86#define DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF (8<<14)
87
876f43c0
SS
88/* Picture aspect ratio options */
89#define DRM_MODE_PICTURE_ASPECT_NONE 0
90#define DRM_MODE_PICTURE_ASPECT_4_3 1
91#define DRM_MODE_PICTURE_ASPECT_16_9 2
92
93/* Aspect ratio flag bitmask (4 bits 22:19) */
94#define DRM_MODE_FLAG_PIC_AR_MASK (0x0F<<19)
95#define DRM_MODE_FLAG_PIC_AR_NONE \
96 (DRM_MODE_PICTURE_ASPECT_NONE<<19)
97#define DRM_MODE_FLAG_PIC_AR_4_3 \
98 (DRM_MODE_PICTURE_ASPECT_4_3<<19)
99#define DRM_MODE_FLAG_PIC_AR_16_9 \
100 (DRM_MODE_PICTURE_ASPECT_16_9<<19)
f453ba04
DA
101
102/* DPMS flags */
103/* bit compatible with the xorg definitions. */
e0c8463a
JB
104#define DRM_MODE_DPMS_ON 0
105#define DRM_MODE_DPMS_STANDBY 1
106#define DRM_MODE_DPMS_SUSPEND 2
107#define DRM_MODE_DPMS_OFF 3
f453ba04
DA
108
109/* Scaling mode options */
53bd8389
JB
110#define DRM_MODE_SCALE_NONE 0 /* Unmodified timing (display or
111 software can still scale) */
112#define DRM_MODE_SCALE_FULLSCREEN 1 /* Full screen, ignore aspect */
113#define DRM_MODE_SCALE_CENTER 2 /* Centered, no scaling */
114#define DRM_MODE_SCALE_ASPECT 3 /* Full screen, preserve aspect */
f453ba04
DA
115
116/* Dithering mode options */
e0c8463a
JB
117#define DRM_MODE_DITHERING_OFF 0
118#define DRM_MODE_DITHERING_ON 1
92897b5c 119#define DRM_MODE_DITHERING_AUTO 2
f453ba04 120
884840aa
JB
121/* Dirty info options */
122#define DRM_MODE_DIRTY_OFF 0
123#define DRM_MODE_DIRTY_ON 1
124#define DRM_MODE_DIRTY_ANNOTATE 2
125
f453ba04 126struct drm_mode_modeinfo {
1d7f83d5 127 __u32 clock;
bbda9c1f
RC
128 __u16 hdisplay;
129 __u16 hsync_start;
130 __u16 hsync_end;
131 __u16 htotal;
132 __u16 hskew;
133 __u16 vdisplay;
134 __u16 vsync_start;
135 __u16 vsync_end;
136 __u16 vtotal;
137 __u16 vscan;
f453ba04 138
fa5829b3 139 __u32 vrefresh;
f453ba04 140
1d7f83d5
AB
141 __u32 flags;
142 __u32 type;
f453ba04
DA
143 char name[DRM_DISPLAY_MODE_LEN];
144};
145
146struct drm_mode_card_res {
1d7f83d5
AB
147 __u64 fb_id_ptr;
148 __u64 crtc_id_ptr;
149 __u64 connector_id_ptr;
150 __u64 encoder_id_ptr;
151 __u32 count_fbs;
152 __u32 count_crtcs;
153 __u32 count_connectors;
154 __u32 count_encoders;
bbda9c1f
RC
155 __u32 min_width;
156 __u32 max_width;
157 __u32 min_height;
158 __u32 max_height;
f453ba04
DA
159};
160
161struct drm_mode_crtc {
1d7f83d5
AB
162 __u64 set_connectors_ptr;
163 __u32 count_connectors;
f453ba04 164
1d7f83d5
AB
165 __u32 crtc_id; /**< Id */
166 __u32 fb_id; /**< Id of framebuffer */
f453ba04 167
bbda9c1f
RC
168 __u32 x; /**< x Position on the framebuffer */
169 __u32 y; /**< y Position on the framebuffer */
f453ba04 170
1d7f83d5
AB
171 __u32 gamma_size;
172 __u32 mode_valid;
f453ba04
DA
173 struct drm_mode_modeinfo mode;
174};
175
8cf5c917
JB
176#define DRM_MODE_PRESENT_TOP_FIELD (1<<0)
177#define DRM_MODE_PRESENT_BOTTOM_FIELD (1<<1)
178
179/* Planes blend with or override other bits on the CRTC */
180struct drm_mode_set_plane {
181 __u32 plane_id;
182 __u32 crtc_id;
183 __u32 fb_id; /* fb object contains surface format type */
184 __u32 flags; /* see above flags */
185
186 /* Signed dest location allows it to be partially off screen */
bbda9c1f
RC
187 __s32 crtc_x;
188 __s32 crtc_y;
189 __u32 crtc_w;
190 __u32 crtc_h;
8cf5c917
JB
191
192 /* Source values are 16.16 fixed point */
bbda9c1f
RC
193 __u32 src_x;
194 __u32 src_y;
195 __u32 src_h;
196 __u32 src_w;
8cf5c917
JB
197};
198
199struct drm_mode_get_plane {
200 __u32 plane_id;
201
202 __u32 crtc_id;
203 __u32 fb_id;
204
205 __u32 possible_crtcs;
206 __u32 gamma_size;
207
208 __u32 count_format_types;
209 __u64 format_type_ptr;
210};
211
212struct drm_mode_get_plane_res {
213 __u64 plane_id_ptr;
214 __u32 count_planes;
215};
216
217#define DRM_MODE_ENCODER_NONE 0
218#define DRM_MODE_ENCODER_DAC 1
219#define DRM_MODE_ENCODER_TMDS 2
220#define DRM_MODE_ENCODER_LVDS 3
221#define DRM_MODE_ENCODER_TVDAC 4
a7331e5c 222#define DRM_MODE_ENCODER_VIRTUAL 5
b8923273 223#define DRM_MODE_ENCODER_DSI 6
182407a6 224#define DRM_MODE_ENCODER_DPMST 7
0b27c02a 225#define DRM_MODE_ENCODER_DPI 8
f453ba04
DA
226
227struct drm_mode_get_encoder {
1d7f83d5
AB
228 __u32 encoder_id;
229 __u32 encoder_type;
f453ba04 230
1d7f83d5 231 __u32 crtc_id; /**< Id of crtc */
f453ba04 232
1d7f83d5
AB
233 __u32 possible_crtcs;
234 __u32 possible_clones;
f453ba04
DA
235};
236
237/* This is for connectors with multiple signal types. */
238/* Try to match DRM_MODE_CONNECTOR_X as closely as possible. */
e0c8463a
JB
239#define DRM_MODE_SUBCONNECTOR_Automatic 0
240#define DRM_MODE_SUBCONNECTOR_Unknown 0
241#define DRM_MODE_SUBCONNECTOR_DVID 3
242#define DRM_MODE_SUBCONNECTOR_DVIA 4
243#define DRM_MODE_SUBCONNECTOR_Composite 5
244#define DRM_MODE_SUBCONNECTOR_SVIDEO 6
245#define DRM_MODE_SUBCONNECTOR_Component 8
aeaa1ad3 246#define DRM_MODE_SUBCONNECTOR_SCART 9
e0c8463a
JB
247
248#define DRM_MODE_CONNECTOR_Unknown 0
249#define DRM_MODE_CONNECTOR_VGA 1
250#define DRM_MODE_CONNECTOR_DVII 2
251#define DRM_MODE_CONNECTOR_DVID 3
252#define DRM_MODE_CONNECTOR_DVIA 4
253#define DRM_MODE_CONNECTOR_Composite 5
254#define DRM_MODE_CONNECTOR_SVIDEO 6
255#define DRM_MODE_CONNECTOR_LVDS 7
256#define DRM_MODE_CONNECTOR_Component 8
257#define DRM_MODE_CONNECTOR_9PinDIN 9
258#define DRM_MODE_CONNECTOR_DisplayPort 10
259#define DRM_MODE_CONNECTOR_HDMIA 11
260#define DRM_MODE_CONNECTOR_HDMIB 12
74bd3c26 261#define DRM_MODE_CONNECTOR_TV 13
7970e677 262#define DRM_MODE_CONNECTOR_eDP 14
a7331e5c 263#define DRM_MODE_CONNECTOR_VIRTUAL 15
b8923273 264#define DRM_MODE_CONNECTOR_DSI 16
0b27c02a 265#define DRM_MODE_CONNECTOR_DPI 17
f453ba04
DA
266
267struct drm_mode_get_connector {
268
1d7f83d5
AB
269 __u64 encoders_ptr;
270 __u64 modes_ptr;
271 __u64 props_ptr;
272 __u64 prop_values_ptr;
f453ba04 273
1d7f83d5
AB
274 __u32 count_modes;
275 __u32 count_props;
276 __u32 count_encoders;
f453ba04 277
1d7f83d5
AB
278 __u32 encoder_id; /**< Current Encoder */
279 __u32 connector_id; /**< Id */
280 __u32 connector_type;
281 __u32 connector_type_id;
f453ba04 282
1d7f83d5 283 __u32 connection;
bbda9c1f
RC
284 __u32 mm_width; /**< width in millimeters */
285 __u32 mm_height; /**< height in millimeters */
1d7f83d5 286 __u32 subpixel;
bc5bd37c
CW
287
288 __u32 pad;
f453ba04
DA
289};
290
e0c8463a
JB
291#define DRM_MODE_PROP_PENDING (1<<0)
292#define DRM_MODE_PROP_RANGE (1<<1)
293#define DRM_MODE_PROP_IMMUTABLE (1<<2)
294#define DRM_MODE_PROP_ENUM (1<<3) /* enumerated type with text strings */
295#define DRM_MODE_PROP_BLOB (1<<4)
49e27545 296#define DRM_MODE_PROP_BITMASK (1<<5) /* bitmask of enumerated types */
f453ba04 297
5ea22f24
RC
298/* non-extended types: legacy bitmask, one bit per type: */
299#define DRM_MODE_PROP_LEGACY_TYPE ( \
300 DRM_MODE_PROP_RANGE | \
301 DRM_MODE_PROP_ENUM | \
302 DRM_MODE_PROP_BLOB | \
303 DRM_MODE_PROP_BITMASK)
304
305/* extended-types: rather than continue to consume a bit per type,
306 * grab a chunk of the bits to use as integer type id.
307 */
308#define DRM_MODE_PROP_EXTENDED_TYPE 0x0000ffc0
309#define DRM_MODE_PROP_TYPE(n) ((n) << 6)
98f75de4 310#define DRM_MODE_PROP_OBJECT DRM_MODE_PROP_TYPE(1)
ebc44cf3 311#define DRM_MODE_PROP_SIGNED_RANGE DRM_MODE_PROP_TYPE(2)
5ea22f24 312
88a48e29
RC
313/* the PROP_ATOMIC flag is used to hide properties from userspace that
314 * is not aware of atomic properties. This is mostly to work around
315 * older userspace (DDX drivers) that read/write each prop they find,
316 * witout being aware that this could be triggering a lengthy modeset.
317 */
318#define DRM_MODE_PROP_ATOMIC 0x80000000
319
f453ba04 320struct drm_mode_property_enum {
1d7f83d5 321 __u64 value;
e0c8463a 322 char name[DRM_PROP_NAME_LEN];
f453ba04
DA
323};
324
325struct drm_mode_get_property {
1d7f83d5
AB
326 __u64 values_ptr; /* values and blob lengths */
327 __u64 enum_blob_ptr; /* enum and blob id ptrs */
f453ba04 328
1d7f83d5
AB
329 __u32 prop_id;
330 __u32 flags;
e0c8463a 331 char name[DRM_PROP_NAME_LEN];
f453ba04 332
1d7f83d5 333 __u32 count_values;
3758b341
DV
334 /* This is only used to count enum values, not blobs. The _blobs is
335 * simply because of a historical reason, i.e. backwards compat. */
1d7f83d5 336 __u32 count_enum_blobs;
f453ba04
DA
337};
338
339struct drm_mode_connector_set_property {
1d7f83d5
AB
340 __u64 value;
341 __u32 prop_id;
342 __u32 connector_id;
f453ba04
DA
343};
344
8812f381
DV
345#define DRM_MODE_OBJECT_CRTC 0xcccccccc
346#define DRM_MODE_OBJECT_CONNECTOR 0xc0c0c0c0
347#define DRM_MODE_OBJECT_ENCODER 0xe0e0e0e0
348#define DRM_MODE_OBJECT_MODE 0xdededede
349#define DRM_MODE_OBJECT_PROPERTY 0xb0b0b0b0
350#define DRM_MODE_OBJECT_FB 0xfbfbfbfb
351#define DRM_MODE_OBJECT_BLOB 0xbbbbbbbb
352#define DRM_MODE_OBJECT_PLANE 0xeeeeeeee
353#define DRM_MODE_OBJECT_ANY 0
354
c543188a
PZ
355struct drm_mode_obj_get_properties {
356 __u64 props_ptr;
357 __u64 prop_values_ptr;
358 __u32 count_props;
359 __u32 obj_id;
360 __u32 obj_type;
361};
362
363struct drm_mode_obj_set_property {
364 __u64 value;
365 __u32 prop_id;
366 __u32 obj_id;
367 __u32 obj_type;
368};
369
f453ba04 370struct drm_mode_get_blob {
1d7f83d5
AB
371 __u32 blob_id;
372 __u32 length;
373 __u64 data;
f453ba04
DA
374};
375
376struct drm_mode_fb_cmd {
1d7f83d5 377 __u32 fb_id;
bbda9c1f
RC
378 __u32 width;
379 __u32 height;
1d7f83d5
AB
380 __u32 pitch;
381 __u32 bpp;
382 __u32 depth;
e0c8463a 383 /* driver specific handle */
1d7f83d5 384 __u32 handle;
f453ba04
DA
385};
386
cc5b6f00 387#define DRM_MODE_FB_INTERLACED (1<<0) /* for interlaced framebuffers */
e3eb3250 388#define DRM_MODE_FB_MODIFIERS (1<<1) /* enables ->modifer[] */
308e5bcb
JB
389
390struct drm_mode_fb_cmd2 {
391 __u32 fb_id;
bbda9c1f
RC
392 __u32 width;
393 __u32 height;
308e5bcb
JB
394 __u32 pixel_format; /* fourcc code from drm_fourcc.h */
395 __u32 flags; /* see above flags */
396
397 /*
398 * In case of planar formats, this ioctl allows up to 4
ae28290b 399 * buffer objects with offsets and pitches per plane.
308e5bcb
JB
400 * The pitch and offset order is dictated by the fourcc,
401 * e.g. NV12 (http://fourcc.org/yuv.php#NV12) is described as:
402 *
403 * YUV 4:2:0 image with a plane of 8 bit Y samples
404 * followed by an interleaved U/V plane containing
405 * 8 bit 2x2 subsampled colour difference samples.
406 *
ae28290b
RC
407 * So it would consist of Y as offsets[0] and UV as
408 * offsets[1]. Note that offsets[0] will generally
409 * be 0 (but this is not required).
e3eb3250
RC
410 *
411 * To accommodate tiled, compressed, etc formats, a per-plane
412 * modifier can be specified. The default value of zero
413 * indicates "native" format as specified by the fourcc.
414 * Vendor specific modifier token. This allows, for example,
415 * different tiling/swizzling pattern on different planes.
416 * See discussion above of DRM_FORMAT_MOD_xxx.
308e5bcb
JB
417 */
418 __u32 handles[4];
419 __u32 pitches[4]; /* pitch for each plane */
420 __u32 offsets[4]; /* offset of each plane */
e3eb3250 421 __u64 modifier[4]; /* ie, tiling, compressed (per plane) */
308e5bcb
JB
422};
423
884840aa
JB
424#define DRM_MODE_FB_DIRTY_ANNOTATE_COPY 0x01
425#define DRM_MODE_FB_DIRTY_ANNOTATE_FILL 0x02
426#define DRM_MODE_FB_DIRTY_FLAGS 0x03
427
a5cd3351
XW
428#define DRM_MODE_FB_DIRTY_MAX_CLIPS 256
429
884840aa
JB
430/*
431 * Mark a region of a framebuffer as dirty.
432 *
433 * Some hardware does not automatically update display contents
434 * as a hardware or software draw to a framebuffer. This ioctl
435 * allows userspace to tell the kernel and the hardware what
436 * regions of the framebuffer have changed.
437 *
438 * The kernel or hardware is free to update more then just the
439 * region specified by the clip rects. The kernel or hardware
440 * may also delay and/or coalesce several calls to dirty into a
441 * single update.
442 *
443 * Userspace may annotate the updates, the annotates are a
444 * promise made by the caller that the change is either a copy
445 * of pixels or a fill of a single color in the region specified.
446 *
447 * If the DRM_MODE_FB_DIRTY_ANNOTATE_COPY flag is given then
448 * the number of updated regions are half of num_clips given,
449 * where the clip rects are paired in src and dst. The width and
450 * height of each one of the pairs must match.
451 *
452 * If the DRM_MODE_FB_DIRTY_ANNOTATE_FILL flag is given the caller
453 * promises that the region specified of the clip rects is filled
454 * completely with a single color as given in the color argument.
455 */
456
457struct drm_mode_fb_dirty_cmd {
458 __u32 fb_id;
459 __u32 flags;
460 __u32 color;
461 __u32 num_clips;
462 __u64 clips_ptr;
463};
464
f453ba04 465struct drm_mode_mode_cmd {
1d7f83d5 466 __u32 connector_id;
f453ba04
DA
467 struct drm_mode_modeinfo mode;
468};
469
7c4eaca4
JB
470#define DRM_MODE_CURSOR_BO 0x01
471#define DRM_MODE_CURSOR_MOVE 0x02
472#define DRM_MODE_CURSOR_FLAGS 0x03
f453ba04
DA
473
474/*
25985edc 475 * depending on the value in flags different members are used.
f453ba04
DA
476 *
477 * CURSOR_BO uses
715f59cc 478 * crtc_id
f453ba04
DA
479 * width
480 * height
715f59cc 481 * handle - if 0 turns the cursor off
f453ba04
DA
482 *
483 * CURSOR_MOVE uses
715f59cc 484 * crtc_id
f453ba04
DA
485 * x
486 * y
487 */
488struct drm_mode_cursor {
1d7f83d5
AB
489 __u32 flags;
490 __u32 crtc_id;
491 __s32 x;
492 __s32 y;
493 __u32 width;
494 __u32 height;
e0c8463a 495 /* driver specific handle */
1d7f83d5 496 __u32 handle;
f453ba04
DA
497};
498
4c813d4d
DA
499struct drm_mode_cursor2 {
500 __u32 flags;
501 __u32 crtc_id;
502 __s32 x;
503 __s32 y;
504 __u32 width;
505 __u32 height;
506 /* driver specific handle */
507 __u32 handle;
508 __s32 hot_x;
509 __s32 hot_y;
510};
511
f453ba04 512struct drm_mode_crtc_lut {
1d7f83d5
AB
513 __u32 crtc_id;
514 __u32 gamma_size;
f453ba04
DA
515
516 /* pointers to arrays */
1d7f83d5
AB
517 __u64 red;
518 __u64 green;
519 __u64 blue;
f453ba04
DA
520};
521
5488dc16
LL
522struct drm_color_ctm {
523 /* Conversion matrix in S31.32 format. */
524 __s64 matrix[9];
525};
526
527struct drm_color_lut {
528 /*
529 * Data is U0.16 fixed point format.
530 */
531 __u16 red;
532 __u16 green;
533 __u16 blue;
534 __u16 reserved;
535};
536
d91d8a3f 537#define DRM_MODE_PAGE_FLIP_EVENT 0x01
9bba0c42 538#define DRM_MODE_PAGE_FLIP_ASYNC 0x02
f837297a
MD
539#define DRM_MODE_PAGE_FLIP_TARGET_ABSOLUTE 0x4
540#define DRM_MODE_PAGE_FLIP_TARGET_RELATIVE 0x8
541#define DRM_MODE_PAGE_FLIP_TARGET (DRM_MODE_PAGE_FLIP_TARGET_ABSOLUTE | \
542 DRM_MODE_PAGE_FLIP_TARGET_RELATIVE)
543#define DRM_MODE_PAGE_FLIP_FLAGS (DRM_MODE_PAGE_FLIP_EVENT | \
544 DRM_MODE_PAGE_FLIP_ASYNC | \
545 DRM_MODE_PAGE_FLIP_TARGET)
d91d8a3f
KH
546
547/*
548 * Request a page flip on the specified crtc.
549 *
550 * This ioctl will ask KMS to schedule a page flip for the specified
551 * crtc. Once any pending rendering targeting the specified fb (as of
552 * ioctl time) has completed, the crtc will be reprogrammed to display
553 * that fb after the next vertical refresh. The ioctl returns
554 * immediately, but subsequent rendering to the current fb will block
555 * in the execbuffer ioctl until the page flip happens. If a page
556 * flip is already pending as the ioctl is called, EBUSY will be
557 * returned.
558 *
9bba0c42
KP
559 * Flag DRM_MODE_PAGE_FLIP_EVENT requests that drm sends back a vblank
560 * event (see drm.h: struct drm_event_vblank) when the page flip is
561 * done. The user_data field passed in with this ioctl will be
562 * returned as the user_data field in the vblank event struct.
563 *
564 * Flag DRM_MODE_PAGE_FLIP_ASYNC requests that the flip happen
565 * 'as soon as possible', meaning that it not delay waiting for vblank.
566 * This may cause tearing on the screen.
d91d8a3f 567 *
f837297a 568 * The reserved field must be zero.
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569 */
570
571struct drm_mode_crtc_page_flip {
572 __u32 crtc_id;
573 __u32 fb_id;
574 __u32 flags;
575 __u32 reserved;
576 __u64 user_data;
577};
578
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579/*
580 * Request a page flip on the specified crtc.
581 *
582 * Same as struct drm_mode_crtc_page_flip, but supports new flags and
583 * re-purposes the reserved field:
584 *
585 * The sequence field must be zero unless either of the
586 * DRM_MODE_PAGE_FLIP_TARGET_ABSOLUTE/RELATIVE flags is specified. When
587 * the ABSOLUTE flag is specified, the sequence field denotes the absolute
588 * vblank sequence when the flip should take effect. When the RELATIVE
589 * flag is specified, the sequence field denotes the relative (to the
590 * current one when the ioctl is called) vblank sequence when the flip
591 * should take effect. NOTE: DRM_IOCTL_WAIT_VBLANK must still be used to
592 * make sure the vblank sequence before the target one has passed before
593 * calling this ioctl. The purpose of the
594 * DRM_MODE_PAGE_FLIP_TARGET_ABSOLUTE/RELATIVE flags is merely to clarify
595 * the target for when code dealing with a page flip runs during a
596 * vertical blank period.
597 */
598
599struct drm_mode_crtc_page_flip_target {
600 __u32 crtc_id;
601 __u32 fb_id;
602 __u32 flags;
603 __u32 sequence;
604 __u64 user_data;
605};
606
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607/* create a dumb scanout buffer */
608struct drm_mode_create_dumb {
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609 __u32 height;
610 __u32 width;
611 __u32 bpp;
612 __u32 flags;
ff72145b 613 /* handle, pitch, size will be returned */
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614 __u32 handle;
615 __u32 pitch;
616 __u64 size;
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617};
618
619/* set up for mmap of a dumb scanout buffer */
620struct drm_mode_map_dumb {
621 /** Handle for the object being mapped. */
622 __u32 handle;
623 __u32 pad;
624 /**
625 * Fake offset to use for subsequent mmap call
626 *
627 * This is a fixed-size type for 32/64 compatibility.
628 */
629 __u64 offset;
630};
631
632struct drm_mode_destroy_dumb {
05623b7f 633 __u32 handle;
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634};
635
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636/* page-flip flags are valid, plus: */
637#define DRM_MODE_ATOMIC_TEST_ONLY 0x0100
638#define DRM_MODE_ATOMIC_NONBLOCK 0x0200
639#define DRM_MODE_ATOMIC_ALLOW_MODESET 0x0400
640
641#define DRM_MODE_ATOMIC_FLAGS (\
642 DRM_MODE_PAGE_FLIP_EVENT |\
643 DRM_MODE_PAGE_FLIP_ASYNC |\
644 DRM_MODE_ATOMIC_TEST_ONLY |\
645 DRM_MODE_ATOMIC_NONBLOCK |\
646 DRM_MODE_ATOMIC_ALLOW_MODESET)
647
648struct drm_mode_atomic {
649 __u32 flags;
650 __u32 count_objs;
651 __u64 objs_ptr;
652 __u64 count_props_ptr;
653 __u64 props_ptr;
654 __u64 prop_values_ptr;
655 __u64 reserved;
656 __u64 user_data;
657};
658
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659/**
660 * Create a new 'blob' data property, copying length bytes from data pointer,
661 * and returning new blob ID.
662 */
663struct drm_mode_create_blob {
664 /** Pointer to data to copy. */
665 __u64 data;
666 /** Length of data to copy. */
667 __u32 length;
668 /** Return: new property ID. */
669 __u32 blob_id;
670};
671
672/**
673 * Destroy a user-created blob property.
674 */
675struct drm_mode_destroy_blob {
676 __u32 blob_id;
677};
678
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679#if defined(__cplusplus)
680}
681#endif
682
f453ba04 683#endif