[mirror_ubuntu-artful-kernel.git] / include / uapi / drm / drm_mode.h

/*
 * Copyright (c) 2007 Dave Airlie <airlied@linux.ie>
 * Copyright (c) 2007 Jakob Bornecrantz <wallbraker@gmail.com>
 * Copyright (c) 2008 Red Hat Inc.
 * Copyright (c) 2007-2008 Tungsten Graphics, Inc., Cedar Park, TX., USA
 * Copyright (c) 2007-2008 Intel Corporation
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal in the Software without restriction, including without limitation
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 * and/or sell copies of the Software, and to permit persons to whom the
 * Software is furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in
 * all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
 * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
 * IN THE SOFTWARE.
 */

#ifndef _DRM_MODE_H
#define _DRM_MODE_H

#include <linux/types.h>

#define DRM_DISPLAY_INFO_LEN	32
#define DRM_CONNECTOR_NAME_LEN	32
#define DRM_DISPLAY_MODE_LEN	32
#define DRM_PROP_NAME_LEN	32

#define DRM_MODE_TYPE_BUILTIN	(1<<0)
#define DRM_MODE_TYPE_CLOCK_C	((1<<1) | DRM_MODE_TYPE_BUILTIN)
#define DRM_MODE_TYPE_CRTC_C	((1<<2) | DRM_MODE_TYPE_BUILTIN)
#define DRM_MODE_TYPE_PREFERRED	(1<<3)
#define DRM_MODE_TYPE_DEFAULT	(1<<4)
#define DRM_MODE_TYPE_USERDEF	(1<<5)
#define DRM_MODE_TYPE_DRIVER	(1<<6)

/* Video mode flags */
/* bit compatible with the xorg definitions. */
#define DRM_MODE_FLAG_PHSYNC			(1<<0)
#define DRM_MODE_FLAG_NHSYNC			(1<<1)
#define DRM_MODE_FLAG_PVSYNC			(1<<2)
#define DRM_MODE_FLAG_NVSYNC			(1<<3)
#define DRM_MODE_FLAG_INTERLACE			(1<<4)
#define DRM_MODE_FLAG_DBLSCAN			(1<<5)
#define DRM_MODE_FLAG_CSYNC			(1<<6)
#define DRM_MODE_FLAG_PCSYNC			(1<<7)
#define DRM_MODE_FLAG_NCSYNC			(1<<8)
#define DRM_MODE_FLAG_HSKEW			(1<<9) /* hskew provided */
#define DRM_MODE_FLAG_BCAST			(1<<10)
#define DRM_MODE_FLAG_PIXMUX			(1<<11)
#define DRM_MODE_FLAG_DBLCLK			(1<<12)
#define DRM_MODE_FLAG_CLKDIV2			(1<<13)
 /*
  * When adding a new stereo mode don't forget to adjust DRM_MODE_FLAGS_3D_MAX
  * (define not exposed to user space).
  */
#define DRM_MODE_FLAG_3D_MASK			(0x1f<<14)
#define  DRM_MODE_FLAG_3D_NONE			(0<<14)
#define  DRM_MODE_FLAG_3D_FRAME_PACKING		(1<<14)
#define  DRM_MODE_FLAG_3D_FIELD_ALTERNATIVE	(2<<14)
#define  DRM_MODE_FLAG_3D_LINE_ALTERNATIVE	(3<<14)
#define  DRM_MODE_FLAG_3D_SIDE_BY_SIDE_FULL	(4<<14)
#define  DRM_MODE_FLAG_3D_L_DEPTH		(5<<14)
#define  DRM_MODE_FLAG_3D_L_DEPTH_GFX_GFX_DEPTH	(6<<14)
#define  DRM_MODE_FLAG_3D_TOP_AND_BOTTOM	(7<<14)
#define  DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF	(8<<14)


/* DPMS flags */
/* bit compatible with the xorg definitions. */
#define DRM_MODE_DPMS_ON	0
#define DRM_MODE_DPMS_STANDBY	1
#define DRM_MODE_DPMS_SUSPEND	2
#define DRM_MODE_DPMS_OFF	3

/* Scaling mode options */
#define DRM_MODE_SCALE_NONE		0 /* Unmodified timing (display or
					     software can still scale) */
#define DRM_MODE_SCALE_FULLSCREEN	1 /* Full screen, ignore aspect */
#define DRM_MODE_SCALE_CENTER		2 /* Centered, no scaling */
#define DRM_MODE_SCALE_ASPECT		3 /* Full screen, preserve aspect */

/* Dithering mode options */
#define DRM_MODE_DITHERING_OFF	0
#define DRM_MODE_DITHERING_ON	1
#define DRM_MODE_DITHERING_AUTO 2

/* Dirty info options */
#define DRM_MODE_DIRTY_OFF      0
#define DRM_MODE_DIRTY_ON       1
#define DRM_MODE_DIRTY_ANNOTATE 2

struct drm_mode_modeinfo {
	__u32 clock;
	__u16 hdisplay, hsync_start, hsync_end, htotal, hskew;
	__u16 vdisplay, vsync_start, vsync_end, vtotal, vscan;

	__u32 vrefresh;

	__u32 flags;
	__u32 type;
	char name[DRM_DISPLAY_MODE_LEN];
};

struct drm_mode_card_res {
	__u64 fb_id_ptr;
	__u64 crtc_id_ptr;
	__u64 connector_id_ptr;
	__u64 encoder_id_ptr;
	__u32 count_fbs;
	__u32 count_crtcs;
	__u32 count_connectors;
	__u32 count_encoders;
	__u32 min_width, max_width;
	__u32 min_height, max_height;
};

struct drm_mode_crtc {
	__u64 set_connectors_ptr;
	__u32 count_connectors;

	__u32 crtc_id; /**< Id */
	__u32 fb_id; /**< Id of framebuffer */

	__u32 x, y; /**< Position on the frameuffer */

	__u32 gamma_size;
	__u32 mode_valid;
	struct drm_mode_modeinfo mode;
};

#define DRM_MODE_PRESENT_TOP_FIELD	(1<<0)
#define DRM_MODE_PRESENT_BOTTOM_FIELD	(1<<1)

/* Planes blend with or override other bits on the CRTC */
struct drm_mode_set_plane {
	__u32 plane_id;
	__u32 crtc_id;
	__u32 fb_id; /* fb object contains surface format type */
	__u32 flags; /* see above flags */

	/* Signed dest location allows it to be partially off screen */
	__s32 crtc_x, crtc_y;
	__u32 crtc_w, crtc_h;

	/* Source values are 16.16 fixed point */
	__u32 src_x, src_y;
	__u32 src_h, src_w;
};

struct drm_mode_get_plane {
	__u32 plane_id;

	__u32 crtc_id;
	__u32 fb_id;

	__u32 possible_crtcs;
	__u32 gamma_size;

	__u32 count_format_types;
	__u64 format_type_ptr;
};

struct drm_mode_get_plane_res {
	__u64 plane_id_ptr;
	__u32 count_planes;
};

#define DRM_MODE_ENCODER_NONE	0
#define DRM_MODE_ENCODER_DAC	1
#define DRM_MODE_ENCODER_TMDS	2
#define DRM_MODE_ENCODER_LVDS	3
#define DRM_MODE_ENCODER_TVDAC	4
#define DRM_MODE_ENCODER_VIRTUAL 5
#define DRM_MODE_ENCODER_DSI	6
#define DRM_MODE_ENCODER_DPMST	7

struct drm_mode_get_encoder {
	__u32 encoder_id;
	__u32 encoder_type;

	__u32 crtc_id; /**< Id of crtc */

	__u32 possible_crtcs;
	__u32 possible_clones;
};

/* This is for connectors with multiple signal types. */
/* Try to match DRM_MODE_CONNECTOR_X as closely as possible. */
#define DRM_MODE_SUBCONNECTOR_Automatic	0
#define DRM_MODE_SUBCONNECTOR_Unknown	0
#define DRM_MODE_SUBCONNECTOR_DVID	3
#define DRM_MODE_SUBCONNECTOR_DVIA	4
#define DRM_MODE_SUBCONNECTOR_Composite	5
#define DRM_MODE_SUBCONNECTOR_SVIDEO	6
#define DRM_MODE_SUBCONNECTOR_Component	8
#define DRM_MODE_SUBCONNECTOR_SCART	9

#define DRM_MODE_CONNECTOR_Unknown	0
#define DRM_MODE_CONNECTOR_VGA		1
#define DRM_MODE_CONNECTOR_DVII		2
#define DRM_MODE_CONNECTOR_DVID		3
#define DRM_MODE_CONNECTOR_DVIA		4
#define DRM_MODE_CONNECTOR_Composite	5
#define DRM_MODE_CONNECTOR_SVIDEO	6
#define DRM_MODE_CONNECTOR_LVDS		7
#define DRM_MODE_CONNECTOR_Component	8
#define DRM_MODE_CONNECTOR_9PinDIN	9
#define DRM_MODE_CONNECTOR_DisplayPort	10
#define DRM_MODE_CONNECTOR_HDMIA	11
#define DRM_MODE_CONNECTOR_HDMIB	12
#define DRM_MODE_CONNECTOR_TV		13
#define DRM_MODE_CONNECTOR_eDP		14
#define DRM_MODE_CONNECTOR_VIRTUAL      15
#define DRM_MODE_CONNECTOR_DSI		16

struct drm_mode_get_connector {

	__u64 encoders_ptr;
	__u64 modes_ptr;
	__u64 props_ptr;
	__u64 prop_values_ptr;

	__u32 count_modes;
	__u32 count_props;
	__u32 count_encoders;

	__u32 encoder_id; /**< Current Encoder */
	__u32 connector_id; /**< Id */
	__u32 connector_type;
	__u32 connector_type_id;

	__u32 connection;
	__u32 mm_width, mm_height; /**< HxW in millimeters */
	__u32 subpixel;

	__u32 pad;
};

#define DRM_MODE_PROP_PENDING	(1<<0)
#define DRM_MODE_PROP_RANGE	(1<<1)
#define DRM_MODE_PROP_IMMUTABLE	(1<<2)
#define DRM_MODE_PROP_ENUM	(1<<3) /* enumerated type with text strings */
#define DRM_MODE_PROP_BLOB	(1<<4)
#define DRM_MODE_PROP_BITMASK	(1<<5) /* bitmask of enumerated types */

/* non-extended types: legacy bitmask, one bit per type: */
#define DRM_MODE_PROP_LEGACY_TYPE  ( \
		DRM_MODE_PROP_RANGE | \
		DRM_MODE_PROP_ENUM | \
		DRM_MODE_PROP_BLOB | \
		DRM_MODE_PROP_BITMASK)

/* extended-types: rather than continue to consume a bit per type,
 * grab a chunk of the bits to use as integer type id.
 */
#define DRM_MODE_PROP_EXTENDED_TYPE	0x0000ffc0
#define DRM_MODE_PROP_TYPE(n)		((n) << 6)
#define DRM_MODE_PROP_OBJECT		DRM_MODE_PROP_TYPE(1)

struct drm_mode_property_enum {
	__u64 value;
	char name[DRM_PROP_NAME_LEN];
};

struct drm_mode_get_property {
	__u64 values_ptr; /* values and blob lengths */
	__u64 enum_blob_ptr; /* enum and blob id ptrs */

	__u32 prop_id;
	__u32 flags;
	char name[DRM_PROP_NAME_LEN];

	__u32 count_values;
	__u32 count_enum_blobs;
};

struct drm_mode_connector_set_property {
	__u64 value;
	__u32 prop_id;
	__u32 connector_id;
};

struct drm_mode_obj_get_properties {
	__u64 props_ptr;
	__u64 prop_values_ptr;
	__u32 count_props;
	__u32 obj_id;
	__u32 obj_type;
};

struct drm_mode_obj_set_property {
	__u64 value;
	__u32 prop_id;
	__u32 obj_id;
	__u32 obj_type;
};

struct drm_mode_get_blob {
	__u32 blob_id;
	__u32 length;
	__u64 data;
};

struct drm_mode_fb_cmd {
	__u32 fb_id;
	__u32 width, height;
	__u32 pitch;
	__u32 bpp;
	__u32 depth;
	/* driver specific handle */
	__u32 handle;
};

#define DRM_MODE_FB_INTERLACED	(1<<0) /* for interlaced framebuffers */

struct drm_mode_fb_cmd2 {
	__u32 fb_id;
	__u32 width, height;
	__u32 pixel_format; /* fourcc code from drm_fourcc.h */
	__u32 flags; /* see above flags */

	/*
	 * In case of planar formats, this ioctl allows up to 4
	 * buffer objects with offets and pitches per plane.
	 * The pitch and offset order is dictated by the fourcc,
	 * e.g. NV12 (http://fourcc.org/yuv.php#NV12) is described as:
	 *
	 *   YUV 4:2:0 image with a plane of 8 bit Y samples
	 *   followed by an interleaved U/V plane containing
	 *   8 bit 2x2 subsampled colour difference samples.
	 *
	 * So it would consist of Y as offset[0] and UV as
	 * offeset[1].  Note that offset[0] will generally
	 * be 0.
	 */
	__u32 handles[4];
	__u32 pitches[4]; /* pitch for each plane */
	__u32 offsets[4]; /* offset of each plane */
};

#define DRM_MODE_FB_DIRTY_ANNOTATE_COPY 0x01
#define DRM_MODE_FB_DIRTY_ANNOTATE_FILL 0x02
#define DRM_MODE_FB_DIRTY_FLAGS         0x03

#define DRM_MODE_FB_DIRTY_MAX_CLIPS     256

/*
 * Mark a region of a framebuffer as dirty.
 *
 * Some hardware does not automatically update display contents
 * as a hardware or software draw to a framebuffer. This ioctl
 * allows userspace to tell the kernel and the hardware what
 * regions of the framebuffer have changed.
 *
 * The kernel or hardware is free to update more then just the
 * region specified by the clip rects. The kernel or hardware
 * may also delay and/or coalesce several calls to dirty into a
 * single update.
 *
 * Userspace may annotate the updates, the annotates are a
 * promise made by the caller that the change is either a copy
 * of pixels or a fill of a single color in the region specified.
 *
 * If the DRM_MODE_FB_DIRTY_ANNOTATE_COPY flag is given then
 * the number of updated regions are half of num_clips given,
 * where the clip rects are paired in src and dst. The width and
 * height of each one of the pairs must match.
 *
 * If the DRM_MODE_FB_DIRTY_ANNOTATE_FILL flag is given the caller
 * promises that the region specified of the clip rects is filled
 * completely with a single color as given in the color argument.
 */

struct drm_mode_fb_dirty_cmd {
	__u32 fb_id;
	__u32 flags;
	__u32 color;
	__u32 num_clips;
	__u64 clips_ptr;
};

struct drm_mode_mode_cmd {
	__u32 connector_id;
	struct drm_mode_modeinfo mode;
};

#define DRM_MODE_CURSOR_BO	0x01
#define DRM_MODE_CURSOR_MOVE	0x02
#define DRM_MODE_CURSOR_FLAGS	0x03

/*
 * depending on the value in flags different members are used.
 *
 * CURSOR_BO uses
 *    crtc_id
 *    width
 *    height
 *    handle - if 0 turns the cursor off
 *
 * CURSOR_MOVE uses
 *    crtc_id
 *    x
 *    y
 */
struct drm_mode_cursor {
	__u32 flags;
	__u32 crtc_id;
	__s32 x;
	__s32 y;
	__u32 width;
	__u32 height;
	/* driver specific handle */
	__u32 handle;
};

struct drm_mode_cursor2 {
	__u32 flags;
	__u32 crtc_id;
	__s32 x;
	__s32 y;
	__u32 width;
	__u32 height;
	/* driver specific handle */
	__u32 handle;
	__s32 hot_x;
	__s32 hot_y;
};

struct drm_mode_crtc_lut {
	__u32 crtc_id;
	__u32 gamma_size;

	/* pointers to arrays */
	__u64 red;
	__u64 green;
	__u64 blue;
};

#define DRM_MODE_PAGE_FLIP_EVENT 0x01
#define DRM_MODE_PAGE_FLIP_ASYNC 0x02
#define DRM_MODE_PAGE_FLIP_FLAGS (DRM_MODE_PAGE_FLIP_EVENT|DRM_MODE_PAGE_FLIP_ASYNC)

/*
 * Request a page flip on the specified crtc.
 *
 * This ioctl will ask KMS to schedule a page flip for the specified
 * crtc.  Once any pending rendering targeting the specified fb (as of
 * ioctl time) has completed, the crtc will be reprogrammed to display
 * that fb after the next vertical refresh.  The ioctl returns
 * immediately, but subsequent rendering to the current fb will block
 * in the execbuffer ioctl until the page flip happens.  If a page
 * flip is already pending as the ioctl is called, EBUSY will be
 * returned.
 *
 * Flag DRM_MODE_PAGE_FLIP_EVENT requests that drm sends back a vblank
 * event (see drm.h: struct drm_event_vblank) when the page flip is
 * done.  The user_data field passed in with this ioctl will be
 * returned as the user_data field in the vblank event struct.
 *
 * Flag DRM_MODE_PAGE_FLIP_ASYNC requests that the flip happen
 * 'as soon as possible', meaning that it not delay waiting for vblank.
 * This may cause tearing on the screen.
 *
 * The reserved field must be zero until we figure out something
 * clever to use it for.
 */

struct drm_mode_crtc_page_flip {
	__u32 crtc_id;
	__u32 fb_id;
	__u32 flags;
	__u32 reserved;
	__u64 user_data;
};

/* create a dumb scanout buffer */
struct drm_mode_create_dumb {
	uint32_t height;
	uint32_t width;
	uint32_t bpp;
	uint32_t flags;
	/* handle, pitch, size will be returned */
	uint32_t handle;
	uint32_t pitch;
	uint64_t size;
};

/* set up for mmap of a dumb scanout buffer */
struct drm_mode_map_dumb {
	/** Handle for the object being mapped. */
	__u32 handle;
	__u32 pad;
	/**
	 * Fake offset to use for subsequent mmap call
	 *
	 * This is a fixed-size type for 32/64 compatibility.
	 */
	__u64 offset;
};

struct drm_mode_destroy_dumb {
	uint32_t handle;
};

#endif
Commit	Line	Data
f453ba04 DA	1	/*
	2	* Copyright (c) 2007 Dave Airlie <airlied@linux.ie>
	3	* Copyright (c) 2007 Jakob Bornecrantz <wallbraker@gmail.com>
	4	* Copyright (c) 2008 Red Hat Inc.
	5	* Copyright (c) 2007-2008 Tungsten Graphics, Inc., Cedar Park, TX., USA
	6	* Copyright (c) 2007-2008 Intel Corporation
	7	*
	8	* Permission is hereby granted, free of charge, to any person obtaining a
	9	* copy of this software and associated documentation files (the "Software"),
	10	* to deal in the Software without restriction, including without limitation
	11	* the rights to use, copy, modify, merge, publish, distribute, sublicense,
	12	* and/or sell copies of the Software, and to permit persons to whom the
	13	* Software is furnished to do so, subject to the following conditions:
	14	*
	15	* The above copyright notice and this permission notice shall be included in
	16	* all copies or substantial portions of the Software.
	17	*
	18	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
	19	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	20	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
	21	* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
	22	* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
	23	* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
	24	* IN THE SOFTWARE.
	25	*/
	26
	27	#ifndef _DRM_MODE_H
	28	#define _DRM_MODE_H
	29
10db4e1e BP	30	#include <linux/types.h>
10db4e1e BP	31
e0c8463a JB	32	#define DRM_DISPLAY_INFO_LEN 32
	33	#define DRM_CONNECTOR_NAME_LEN 32
	34	#define DRM_DISPLAY_MODE_LEN 32
	35	#define DRM_PROP_NAME_LEN 32
f453ba04 DA	36
	37	#define DRM_MODE_TYPE_BUILTIN (1<<0)
	38	#define DRM_MODE_TYPE_CLOCK_C ((1<<1) \| DRM_MODE_TYPE_BUILTIN)
	39	#define DRM_MODE_TYPE_CRTC_C ((1<<2) \| DRM_MODE_TYPE_BUILTIN)
	40	#define DRM_MODE_TYPE_PREFERRED (1<<3)
	41	#define DRM_MODE_TYPE_DEFAULT (1<<4)
	42	#define DRM_MODE_TYPE_USERDEF (1<<5)
	43	#define DRM_MODE_TYPE_DRIVER (1<<6)
	44
	45	/* Video mode flags */
	46	/* bit compatible with the xorg definitions. */
4aa17cf0 DL	47	#define DRM_MODE_FLAG_PHSYNC (1<<0)
	48	#define DRM_MODE_FLAG_NHSYNC (1<<1)
	49	#define DRM_MODE_FLAG_PVSYNC (1<<2)
	50	#define DRM_MODE_FLAG_NVSYNC (1<<3)
	51	#define DRM_MODE_FLAG_INTERLACE (1<<4)
	52	#define DRM_MODE_FLAG_DBLSCAN (1<<5)
	53	#define DRM_MODE_FLAG_CSYNC (1<<6)
	54	#define DRM_MODE_FLAG_PCSYNC (1<<7)
	55	#define DRM_MODE_FLAG_NCSYNC (1<<8)
	56	#define DRM_MODE_FLAG_HSKEW (1<<9) /* hskew provided */
	57	#define DRM_MODE_FLAG_BCAST (1<<10)
	58	#define DRM_MODE_FLAG_PIXMUX (1<<11)
	59	#define DRM_MODE_FLAG_DBLCLK (1<<12)
	60	#define DRM_MODE_FLAG_CLKDIV2 (1<<13)
5848ad40 DL	61	/*
	62	* When adding a new stereo mode don't forget to adjust DRM_MODE_FLAGS_3D_MAX
	63	* (define not exposed to user space).
	64	*/
f7e121b7 DL	65	#define DRM_MODE_FLAG_3D_MASK (0x1f<<14)
	66	#define DRM_MODE_FLAG_3D_NONE (0<<14)
	67	#define DRM_MODE_FLAG_3D_FRAME_PACKING (1<<14)
	68	#define DRM_MODE_FLAG_3D_FIELD_ALTERNATIVE (2<<14)
	69	#define DRM_MODE_FLAG_3D_LINE_ALTERNATIVE (3<<14)
	70	#define DRM_MODE_FLAG_3D_SIDE_BY_SIDE_FULL (4<<14)
	71	#define DRM_MODE_FLAG_3D_L_DEPTH (5<<14)
	72	#define DRM_MODE_FLAG_3D_L_DEPTH_GFX_GFX_DEPTH (6<<14)
	73	#define DRM_MODE_FLAG_3D_TOP_AND_BOTTOM (7<<14)
	74	#define DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF (8<<14)
	75
f453ba04 DA	76
	77	/* DPMS flags */
	78	/* bit compatible with the xorg definitions. */
e0c8463a JB	79	#define DRM_MODE_DPMS_ON 0
	80	#define DRM_MODE_DPMS_STANDBY 1
	81	#define DRM_MODE_DPMS_SUSPEND 2
	82	#define DRM_MODE_DPMS_OFF 3
f453ba04 DA	83
f453ba04 DA	84	/* Scaling mode options */
53bd8389 JB	85	#define DRM_MODE_SCALE_NONE 0 /* Unmodified timing (display or
	86	software can still scale) */
	87	#define DRM_MODE_SCALE_FULLSCREEN 1 /* Full screen, ignore aspect */
	88	#define DRM_MODE_SCALE_CENTER 2 /* Centered, no scaling */
	89	#define DRM_MODE_SCALE_ASPECT 3 /* Full screen, preserve aspect */
f453ba04 DA	90
f453ba04 DA	91	/* Dithering mode options */
e0c8463a JB	92	#define DRM_MODE_DITHERING_OFF 0
e0c8463a JB	93	#define DRM_MODE_DITHERING_ON 1
92897b5c	94	#define DRM_MODE_DITHERING_AUTO 2
f453ba04	95
884840aa JB	96	/* Dirty info options */
	97	#define DRM_MODE_DIRTY_OFF 0
	98	#define DRM_MODE_DIRTY_ON 1
	99	#define DRM_MODE_DIRTY_ANNOTATE 2
	100
f453ba04	101	struct drm_mode_modeinfo {
1d7f83d5 AB	102	__u32 clock;
	103	__u16 hdisplay, hsync_start, hsync_end, htotal, hskew;
	104	__u16 vdisplay, vsync_start, vsync_end, vtotal, vscan;
f453ba04	105
fa5829b3	106	__u32 vrefresh;
f453ba04	107
1d7f83d5 AB	108	__u32 flags;
1d7f83d5 AB	109	__u32 type;
f453ba04 DA	110	char name[DRM_DISPLAY_MODE_LEN];
	111	};
	112
	113	struct drm_mode_card_res {
1d7f83d5 AB	114	__u64 fb_id_ptr;
	115	__u64 crtc_id_ptr;
	116	__u64 connector_id_ptr;
	117	__u64 encoder_id_ptr;
	118	__u32 count_fbs;
	119	__u32 count_crtcs;
	120	__u32 count_connectors;
	121	__u32 count_encoders;
	122	__u32 min_width, max_width;
	123	__u32 min_height, max_height;
f453ba04 DA	124	};
	125
	126	struct drm_mode_crtc {
1d7f83d5 AB	127	__u64 set_connectors_ptr;
1d7f83d5 AB	128	__u32 count_connectors;
f453ba04	129
1d7f83d5 AB	130	__u32 crtc_id; /*< Id /
1d7f83d5 AB	131	__u32 fb_id; /*< Id of framebuffer /
f453ba04	132
1d7f83d5	133	__u32 x, y; /*< Position on the frameuffer /
f453ba04	134
1d7f83d5 AB	135	__u32 gamma_size;
1d7f83d5 AB	136	__u32 mode_valid;
f453ba04 DA	137	struct drm_mode_modeinfo mode;
	138	};
	139
8cf5c917 JB	140	#define DRM_MODE_PRESENT_TOP_FIELD (1<<0)
	141	#define DRM_MODE_PRESENT_BOTTOM_FIELD (1<<1)
	142
	143	/* Planes blend with or override other bits on the CRTC */
	144	struct drm_mode_set_plane {
	145	__u32 plane_id;
	146	__u32 crtc_id;
	147	__u32 fb_id; /* fb object contains surface format type */
	148	__u32 flags; /* see above flags */
	149
	150	/* Signed dest location allows it to be partially off screen */
	151	__s32 crtc_x, crtc_y;
	152	__u32 crtc_w, crtc_h;
	153
	154	/* Source values are 16.16 fixed point */
	155	__u32 src_x, src_y;
	156	__u32 src_h, src_w;
	157	};
	158
	159	struct drm_mode_get_plane {
	160	__u32 plane_id;
	161
	162	__u32 crtc_id;
	163	__u32 fb_id;
	164
	165	__u32 possible_crtcs;
	166	__u32 gamma_size;
	167
	168	__u32 count_format_types;
	169	__u64 format_type_ptr;
	170	};
	171
	172	struct drm_mode_get_plane_res {
	173	__u64 plane_id_ptr;
	174	__u32 count_planes;
	175	};
	176
	177	#define DRM_MODE_ENCODER_NONE 0
	178	#define DRM_MODE_ENCODER_DAC 1
	179	#define DRM_MODE_ENCODER_TMDS 2
	180	#define DRM_MODE_ENCODER_LVDS 3
	181	#define DRM_MODE_ENCODER_TVDAC 4
a7331e5c	182	#define DRM_MODE_ENCODER_VIRTUAL 5
b8923273	183	#define DRM_MODE_ENCODER_DSI 6
182407a6	184	#define DRM_MODE_ENCODER_DPMST 7
f453ba04 DA	185
f453ba04 DA	186	struct drm_mode_get_encoder {
1d7f83d5 AB	187	__u32 encoder_id;
1d7f83d5 AB	188	__u32 encoder_type;
f453ba04	189
1d7f83d5	190	__u32 crtc_id; /*< Id of crtc /
f453ba04	191
1d7f83d5 AB	192	__u32 possible_crtcs;
1d7f83d5 AB	193	__u32 possible_clones;
f453ba04 DA	194	};
	195
	196	/* This is for connectors with multiple signal types. */
	197	/* Try to match DRM_MODE_CONNECTOR_X as closely as possible. */
e0c8463a JB	198	#define DRM_MODE_SUBCONNECTOR_Automatic 0
	199	#define DRM_MODE_SUBCONNECTOR_Unknown 0
	200	#define DRM_MODE_SUBCONNECTOR_DVID 3
	201	#define DRM_MODE_SUBCONNECTOR_DVIA 4
	202	#define DRM_MODE_SUBCONNECTOR_Composite 5
	203	#define DRM_MODE_SUBCONNECTOR_SVIDEO 6
	204	#define DRM_MODE_SUBCONNECTOR_Component 8
aeaa1ad3	205	#define DRM_MODE_SUBCONNECTOR_SCART 9
e0c8463a JB	206
	207	#define DRM_MODE_CONNECTOR_Unknown 0
	208	#define DRM_MODE_CONNECTOR_VGA 1
	209	#define DRM_MODE_CONNECTOR_DVII 2
	210	#define DRM_MODE_CONNECTOR_DVID 3
	211	#define DRM_MODE_CONNECTOR_DVIA 4
	212	#define DRM_MODE_CONNECTOR_Composite 5
	213	#define DRM_MODE_CONNECTOR_SVIDEO 6
	214	#define DRM_MODE_CONNECTOR_LVDS 7
	215	#define DRM_MODE_CONNECTOR_Component 8
	216	#define DRM_MODE_CONNECTOR_9PinDIN 9
	217	#define DRM_MODE_CONNECTOR_DisplayPort 10
	218	#define DRM_MODE_CONNECTOR_HDMIA 11
	219	#define DRM_MODE_CONNECTOR_HDMIB 12
74bd3c26	220	#define DRM_MODE_CONNECTOR_TV 13
7970e677	221	#define DRM_MODE_CONNECTOR_eDP 14
a7331e5c	222	#define DRM_MODE_CONNECTOR_VIRTUAL 15
b8923273	223	#define DRM_MODE_CONNECTOR_DSI 16
f453ba04 DA	224
	225	struct drm_mode_get_connector {
	226
1d7f83d5 AB	227	__u64 encoders_ptr;
	228	__u64 modes_ptr;
	229	__u64 props_ptr;
	230	__u64 prop_values_ptr;
f453ba04	231
1d7f83d5 AB	232	__u32 count_modes;
	233	__u32 count_props;
	234	__u32 count_encoders;
f453ba04	235
1d7f83d5 AB	236	__u32 encoder_id; /*< Current Encoder /
	237	__u32 connector_id; /*< Id /
	238	__u32 connector_type;
	239	__u32 connector_type_id;
f453ba04	240
1d7f83d5 AB	241	__u32 connection;
	242	__u32 mm_width, mm_height; /*< HxW in millimeters /
	243	__u32 subpixel;
bc5bd37c CW	244
bc5bd37c CW	245	__u32 pad;
f453ba04 DA	246	};
f453ba04 DA	247
e0c8463a JB	248	#define DRM_MODE_PROP_PENDING (1<<0)
	249	#define DRM_MODE_PROP_RANGE (1<<1)
	250	#define DRM_MODE_PROP_IMMUTABLE (1<<2)
	251	#define DRM_MODE_PROP_ENUM (1<<3) /* enumerated type with text strings */
	252	#define DRM_MODE_PROP_BLOB (1<<4)
49e27545	253	#define DRM_MODE_PROP_BITMASK (1<<5) /* bitmask of enumerated types */
f453ba04	254
5ea22f24 RC	255	/* non-extended types: legacy bitmask, one bit per type: */
	256	#define DRM_MODE_PROP_LEGACY_TYPE ( \
	257	DRM_MODE_PROP_RANGE \| \
	258	DRM_MODE_PROP_ENUM \| \
	259	DRM_MODE_PROP_BLOB \| \
	260	DRM_MODE_PROP_BITMASK)
	261
	262	/* extended-types: rather than continue to consume a bit per type,
	263	* grab a chunk of the bits to use as integer type id.
	264	*/
	265	#define DRM_MODE_PROP_EXTENDED_TYPE 0x0000ffc0
	266	#define DRM_MODE_PROP_TYPE(n) ((n) << 6)
98f75de4	267	#define DRM_MODE_PROP_OBJECT DRM_MODE_PROP_TYPE(1)
5ea22f24	268
f453ba04	269	struct drm_mode_property_enum {
1d7f83d5	270	__u64 value;
e0c8463a	271	char name[DRM_PROP_NAME_LEN];
f453ba04 DA	272	};
	273
	274	struct drm_mode_get_property {
1d7f83d5 AB	275	__u64 values_ptr; /* values and blob lengths */
1d7f83d5 AB	276	__u64 enum_blob_ptr; /* enum and blob id ptrs */
f453ba04	277
1d7f83d5 AB	278	__u32 prop_id;
1d7f83d5 AB	279	__u32 flags;
e0c8463a	280	char name[DRM_PROP_NAME_LEN];
f453ba04	281
1d7f83d5 AB	282	__u32 count_values;
1d7f83d5 AB	283	__u32 count_enum_blobs;
f453ba04 DA	284	};
	285
	286	struct drm_mode_connector_set_property {
1d7f83d5 AB	287	__u64 value;
	288	__u32 prop_id;
	289	__u32 connector_id;
f453ba04 DA	290	};
f453ba04 DA	291
c543188a PZ	292	struct drm_mode_obj_get_properties {
	293	__u64 props_ptr;
	294	__u64 prop_values_ptr;
	295	__u32 count_props;
	296	__u32 obj_id;
	297	__u32 obj_type;
	298	};
	299
	300	struct drm_mode_obj_set_property {
	301	__u64 value;
	302	__u32 prop_id;
	303	__u32 obj_id;
	304	__u32 obj_type;
	305	};
	306
f453ba04	307	struct drm_mode_get_blob {
1d7f83d5 AB	308	__u32 blob_id;
	309	__u32 length;
	310	__u64 data;
f453ba04 DA	311	};
	312
	313	struct drm_mode_fb_cmd {
1d7f83d5 AB	314	__u32 fb_id;
	315	__u32 width, height;
	316	__u32 pitch;
	317	__u32 bpp;
	318	__u32 depth;
e0c8463a	319	/* driver specific handle */
1d7f83d5	320	__u32 handle;
f453ba04 DA	321	};
f453ba04 DA	322
cc5b6f00	323	#define DRM_MODE_FB_INTERLACED (1<<0) /* for interlaced framebuffers */
308e5bcb JB	324
	325	struct drm_mode_fb_cmd2 {
	326	__u32 fb_id;
	327	__u32 width, height;
	328	__u32 pixel_format; /* fourcc code from drm_fourcc.h */
	329	__u32 flags; /* see above flags */
	330
	331	/*
	332	* In case of planar formats, this ioctl allows up to 4
	333	* buffer objects with offets and pitches per plane.
	334	* The pitch and offset order is dictated by the fourcc,
	335	* e.g. NV12 (http://fourcc.org/yuv.php#NV12) is described as:
	336	*
	337	* YUV 4:2:0 image with a plane of 8 bit Y samples
	338	* followed by an interleaved U/V plane containing
	339	* 8 bit 2x2 subsampled colour difference samples.
	340	*
	341	* So it would consist of Y as offset[0] and UV as
	342	* offeset[1]. Note that offset[0] will generally
	343	* be 0.
	344	*/
	345	__u32 handles[4];
	346	__u32 pitches[4]; /* pitch for each plane */
	347	__u32 offsets[4]; /* offset of each plane */
	348	};
	349
884840aa JB	350	#define DRM_MODE_FB_DIRTY_ANNOTATE_COPY 0x01
	351	#define DRM_MODE_FB_DIRTY_ANNOTATE_FILL 0x02
	352	#define DRM_MODE_FB_DIRTY_FLAGS 0x03
	353
a5cd3351 XW	354	#define DRM_MODE_FB_DIRTY_MAX_CLIPS 256
a5cd3351 XW	355
884840aa JB	356	/*
	357	* Mark a region of a framebuffer as dirty.
	358	*
	359	* Some hardware does not automatically update display contents
	360	* as a hardware or software draw to a framebuffer. This ioctl
	361	* allows userspace to tell the kernel and the hardware what
	362	* regions of the framebuffer have changed.
	363	*
	364	* The kernel or hardware is free to update more then just the
	365	* region specified by the clip rects. The kernel or hardware
	366	* may also delay and/or coalesce several calls to dirty into a
	367	* single update.
	368	*
	369	* Userspace may annotate the updates, the annotates are a
	370	* promise made by the caller that the change is either a copy
	371	* of pixels or a fill of a single color in the region specified.
	372	*
	373	* If the DRM_MODE_FB_DIRTY_ANNOTATE_COPY flag is given then
	374	* the number of updated regions are half of num_clips given,
	375	* where the clip rects are paired in src and dst. The width and
	376	* height of each one of the pairs must match.
	377	*
	378	* If the DRM_MODE_FB_DIRTY_ANNOTATE_FILL flag is given the caller
	379	* promises that the region specified of the clip rects is filled
	380	* completely with a single color as given in the color argument.
	381	*/
	382
	383	struct drm_mode_fb_dirty_cmd {
	384	__u32 fb_id;
	385	__u32 flags;
	386	__u32 color;
	387	__u32 num_clips;
	388	__u64 clips_ptr;
	389	};
	390
f453ba04	391	struct drm_mode_mode_cmd {
1d7f83d5	392	__u32 connector_id;
f453ba04 DA	393	struct drm_mode_modeinfo mode;
	394	};
	395
7c4eaca4 JB	396	#define DRM_MODE_CURSOR_BO 0x01
	397	#define DRM_MODE_CURSOR_MOVE 0x02
	398	#define DRM_MODE_CURSOR_FLAGS 0x03
f453ba04 DA	399
f453ba04 DA	400	/*
25985edc	401	* depending on the value in flags different members are used.
f453ba04 DA	402	*
f453ba04 DA	403	* CURSOR_BO uses
715f59cc	404	* crtc_id
f453ba04 DA	405	* width
f453ba04 DA	406	* height
715f59cc	407	* handle - if 0 turns the cursor off
f453ba04 DA	408	*
f453ba04 DA	409	* CURSOR_MOVE uses
715f59cc	410	* crtc_id
f453ba04 DA	411	* x
	412	* y
	413	*/
	414	struct drm_mode_cursor {
1d7f83d5 AB	415	__u32 flags;
	416	__u32 crtc_id;
	417	__s32 x;
	418	__s32 y;
	419	__u32 width;
	420	__u32 height;
e0c8463a	421	/* driver specific handle */
1d7f83d5	422	__u32 handle;
f453ba04 DA	423	};
f453ba04 DA	424
4c813d4d DA	425	struct drm_mode_cursor2 {
	426	__u32 flags;
	427	__u32 crtc_id;
	428	__s32 x;
	429	__s32 y;
	430	__u32 width;
	431	__u32 height;
	432	/* driver specific handle */
	433	__u32 handle;
	434	__s32 hot_x;
	435	__s32 hot_y;
	436	};
	437
f453ba04	438	struct drm_mode_crtc_lut {
1d7f83d5 AB	439	__u32 crtc_id;
1d7f83d5 AB	440	__u32 gamma_size;
f453ba04 DA	441
f453ba04 DA	442	/* pointers to arrays */
1d7f83d5 AB	443	__u64 red;
	444	__u64 green;
	445	__u64 blue;
f453ba04 DA	446	};
f453ba04 DA	447
d91d8a3f	448	#define DRM_MODE_PAGE_FLIP_EVENT 0x01
9bba0c42 KP	449	#define DRM_MODE_PAGE_FLIP_ASYNC 0x02
9bba0c42 KP	450	#define DRM_MODE_PAGE_FLIP_FLAGS (DRM_MODE_PAGE_FLIP_EVENT\|DRM_MODE_PAGE_FLIP_ASYNC)
d91d8a3f KH	451
	452	/*
	453	* Request a page flip on the specified crtc.
	454	*
	455	* This ioctl will ask KMS to schedule a page flip for the specified
	456	* crtc. Once any pending rendering targeting the specified fb (as of
	457	* ioctl time) has completed, the crtc will be reprogrammed to display
	458	* that fb after the next vertical refresh. The ioctl returns
	459	* immediately, but subsequent rendering to the current fb will block
	460	* in the execbuffer ioctl until the page flip happens. If a page
	461	* flip is already pending as the ioctl is called, EBUSY will be
	462	* returned.
	463	*
9bba0c42 KP	464	* Flag DRM_MODE_PAGE_FLIP_EVENT requests that drm sends back a vblank
	465	* event (see drm.h: struct drm_event_vblank) when the page flip is
	466	* done. The user_data field passed in with this ioctl will be
	467	* returned as the user_data field in the vblank event struct.
	468	*
	469	* Flag DRM_MODE_PAGE_FLIP_ASYNC requests that the flip happen
	470	* 'as soon as possible', meaning that it not delay waiting for vblank.
	471	* This may cause tearing on the screen.
d91d8a3f KH	472	*
	473	* The reserved field must be zero until we figure out something
	474	* clever to use it for.
	475	*/
	476
	477	struct drm_mode_crtc_page_flip {
	478	__u32 crtc_id;
	479	__u32 fb_id;
	480	__u32 flags;
	481	__u32 reserved;
	482	__u64 user_data;
	483	};
	484
ff72145b DA	485	/* create a dumb scanout buffer */
	486	struct drm_mode_create_dumb {
	487	uint32_t height;
	488	uint32_t width;
	489	uint32_t bpp;
	490	uint32_t flags;
	491	/* handle, pitch, size will be returned */
	492	uint32_t handle;
	493	uint32_t pitch;
	494	uint64_t size;
	495	};
	496
	497	/* set up for mmap of a dumb scanout buffer */
	498	struct drm_mode_map_dumb {
	499	/** Handle for the object being mapped. */
	500	__u32 handle;
	501	__u32 pad;
	502	/**
	503	* Fake offset to use for subsequent mmap call
	504	*
	505	* This is a fixed-size type for 32/64 compatibility.
	506	*/
	507	__u64 offset;
	508	};
	509
	510	struct drm_mode_destroy_dumb {
	511	uint32_t handle;
	512	};
	513
f453ba04	514	#endif