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f453ba04 DA |
1 | /* |
2 | * Copyright (c) 2007 Dave Airlie <airlied@linux.ie> | |
3 | * Copyright (c) 2007 Jakob Bornecrantz <wallbraker@gmail.com> | |
4 | * Copyright (c) 2008 Red Hat Inc. | |
5 | * Copyright (c) 2007-2008 Tungsten Graphics, Inc., Cedar Park, TX., USA | |
6 | * Copyright (c) 2007-2008 Intel Corporation | |
7 | * | |
8 | * Permission is hereby granted, free of charge, to any person obtaining a | |
9 | * copy of this software and associated documentation files (the "Software"), | |
10 | * to deal in the Software without restriction, including without limitation | |
11 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
12 | * and/or sell copies of the Software, and to permit persons to whom the | |
13 | * Software is furnished to do so, subject to the following conditions: | |
14 | * | |
15 | * The above copyright notice and this permission notice shall be included in | |
16 | * all copies or substantial portions of the Software. | |
17 | * | |
18 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
19 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
20 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE | |
21 | * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
22 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
23 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS | |
24 | * IN THE SOFTWARE. | |
25 | */ | |
26 | ||
27 | #ifndef _DRM_MODE_H | |
28 | #define _DRM_MODE_H | |
29 | ||
10db4e1e BP |
30 | #include <linux/types.h> |
31 | ||
e0c8463a JB |
32 | #define DRM_DISPLAY_INFO_LEN 32 |
33 | #define DRM_CONNECTOR_NAME_LEN 32 | |
34 | #define DRM_DISPLAY_MODE_LEN 32 | |
35 | #define DRM_PROP_NAME_LEN 32 | |
f453ba04 DA |
36 | |
37 | #define DRM_MODE_TYPE_BUILTIN (1<<0) | |
38 | #define DRM_MODE_TYPE_CLOCK_C ((1<<1) | DRM_MODE_TYPE_BUILTIN) | |
39 | #define DRM_MODE_TYPE_CRTC_C ((1<<2) | DRM_MODE_TYPE_BUILTIN) | |
40 | #define DRM_MODE_TYPE_PREFERRED (1<<3) | |
41 | #define DRM_MODE_TYPE_DEFAULT (1<<4) | |
42 | #define DRM_MODE_TYPE_USERDEF (1<<5) | |
43 | #define DRM_MODE_TYPE_DRIVER (1<<6) | |
44 | ||
45 | /* Video mode flags */ | |
46 | /* bit compatible with the xorg definitions. */ | |
47 | #define DRM_MODE_FLAG_PHSYNC (1<<0) | |
48 | #define DRM_MODE_FLAG_NHSYNC (1<<1) | |
49 | #define DRM_MODE_FLAG_PVSYNC (1<<2) | |
50 | #define DRM_MODE_FLAG_NVSYNC (1<<3) | |
51 | #define DRM_MODE_FLAG_INTERLACE (1<<4) | |
52 | #define DRM_MODE_FLAG_DBLSCAN (1<<5) | |
53 | #define DRM_MODE_FLAG_CSYNC (1<<6) | |
54 | #define DRM_MODE_FLAG_PCSYNC (1<<7) | |
55 | #define DRM_MODE_FLAG_NCSYNC (1<<8) | |
56 | #define DRM_MODE_FLAG_HSKEW (1<<9) /* hskew provided */ | |
57 | #define DRM_MODE_FLAG_BCAST (1<<10) | |
58 | #define DRM_MODE_FLAG_PIXMUX (1<<11) | |
59 | #define DRM_MODE_FLAG_DBLCLK (1<<12) | |
60 | #define DRM_MODE_FLAG_CLKDIV2 (1<<13) | |
61 | ||
62 | /* DPMS flags */ | |
63 | /* bit compatible with the xorg definitions. */ | |
e0c8463a JB |
64 | #define DRM_MODE_DPMS_ON 0 |
65 | #define DRM_MODE_DPMS_STANDBY 1 | |
66 | #define DRM_MODE_DPMS_SUSPEND 2 | |
67 | #define DRM_MODE_DPMS_OFF 3 | |
f453ba04 DA |
68 | |
69 | /* Scaling mode options */ | |
53bd8389 JB |
70 | #define DRM_MODE_SCALE_NONE 0 /* Unmodified timing (display or |
71 | software can still scale) */ | |
72 | #define DRM_MODE_SCALE_FULLSCREEN 1 /* Full screen, ignore aspect */ | |
73 | #define DRM_MODE_SCALE_CENTER 2 /* Centered, no scaling */ | |
74 | #define DRM_MODE_SCALE_ASPECT 3 /* Full screen, preserve aspect */ | |
f453ba04 DA |
75 | |
76 | /* Dithering mode options */ | |
e0c8463a JB |
77 | #define DRM_MODE_DITHERING_OFF 0 |
78 | #define DRM_MODE_DITHERING_ON 1 | |
92897b5c | 79 | #define DRM_MODE_DITHERING_AUTO 2 |
f453ba04 | 80 | |
884840aa JB |
81 | /* Dirty info options */ |
82 | #define DRM_MODE_DIRTY_OFF 0 | |
83 | #define DRM_MODE_DIRTY_ON 1 | |
84 | #define DRM_MODE_DIRTY_ANNOTATE 2 | |
85 | ||
f453ba04 | 86 | struct drm_mode_modeinfo { |
1d7f83d5 AB |
87 | __u32 clock; |
88 | __u16 hdisplay, hsync_start, hsync_end, htotal, hskew; | |
89 | __u16 vdisplay, vsync_start, vsync_end, vtotal, vscan; | |
f453ba04 | 90 | |
fa5829b3 | 91 | __u32 vrefresh; |
f453ba04 | 92 | |
1d7f83d5 AB |
93 | __u32 flags; |
94 | __u32 type; | |
f453ba04 DA |
95 | char name[DRM_DISPLAY_MODE_LEN]; |
96 | }; | |
97 | ||
98 | struct drm_mode_card_res { | |
1d7f83d5 AB |
99 | __u64 fb_id_ptr; |
100 | __u64 crtc_id_ptr; | |
101 | __u64 connector_id_ptr; | |
102 | __u64 encoder_id_ptr; | |
103 | __u32 count_fbs; | |
104 | __u32 count_crtcs; | |
105 | __u32 count_connectors; | |
106 | __u32 count_encoders; | |
107 | __u32 min_width, max_width; | |
108 | __u32 min_height, max_height; | |
f453ba04 DA |
109 | }; |
110 | ||
111 | struct drm_mode_crtc { | |
1d7f83d5 AB |
112 | __u64 set_connectors_ptr; |
113 | __u32 count_connectors; | |
f453ba04 | 114 | |
1d7f83d5 AB |
115 | __u32 crtc_id; /**< Id */ |
116 | __u32 fb_id; /**< Id of framebuffer */ | |
f453ba04 | 117 | |
1d7f83d5 | 118 | __u32 x, y; /**< Position on the frameuffer */ |
f453ba04 | 119 | |
1d7f83d5 AB |
120 | __u32 gamma_size; |
121 | __u32 mode_valid; | |
f453ba04 DA |
122 | struct drm_mode_modeinfo mode; |
123 | }; | |
124 | ||
8cf5c917 JB |
125 | #define DRM_MODE_PRESENT_TOP_FIELD (1<<0) |
126 | #define DRM_MODE_PRESENT_BOTTOM_FIELD (1<<1) | |
127 | ||
128 | /* Planes blend with or override other bits on the CRTC */ | |
129 | struct drm_mode_set_plane { | |
130 | __u32 plane_id; | |
131 | __u32 crtc_id; | |
132 | __u32 fb_id; /* fb object contains surface format type */ | |
133 | __u32 flags; /* see above flags */ | |
134 | ||
135 | /* Signed dest location allows it to be partially off screen */ | |
136 | __s32 crtc_x, crtc_y; | |
137 | __u32 crtc_w, crtc_h; | |
138 | ||
139 | /* Source values are 16.16 fixed point */ | |
140 | __u32 src_x, src_y; | |
141 | __u32 src_h, src_w; | |
142 | }; | |
143 | ||
144 | struct drm_mode_get_plane { | |
145 | __u32 plane_id; | |
146 | ||
147 | __u32 crtc_id; | |
148 | __u32 fb_id; | |
149 | ||
150 | __u32 possible_crtcs; | |
151 | __u32 gamma_size; | |
152 | ||
153 | __u32 count_format_types; | |
154 | __u64 format_type_ptr; | |
155 | }; | |
156 | ||
157 | struct drm_mode_get_plane_res { | |
158 | __u64 plane_id_ptr; | |
159 | __u32 count_planes; | |
160 | }; | |
161 | ||
162 | #define DRM_MODE_ENCODER_NONE 0 | |
163 | #define DRM_MODE_ENCODER_DAC 1 | |
164 | #define DRM_MODE_ENCODER_TMDS 2 | |
165 | #define DRM_MODE_ENCODER_LVDS 3 | |
166 | #define DRM_MODE_ENCODER_TVDAC 4 | |
a7331e5c | 167 | #define DRM_MODE_ENCODER_VIRTUAL 5 |
f453ba04 DA |
168 | |
169 | struct drm_mode_get_encoder { | |
1d7f83d5 AB |
170 | __u32 encoder_id; |
171 | __u32 encoder_type; | |
f453ba04 | 172 | |
1d7f83d5 | 173 | __u32 crtc_id; /**< Id of crtc */ |
f453ba04 | 174 | |
1d7f83d5 AB |
175 | __u32 possible_crtcs; |
176 | __u32 possible_clones; | |
f453ba04 DA |
177 | }; |
178 | ||
179 | /* This is for connectors with multiple signal types. */ | |
180 | /* Try to match DRM_MODE_CONNECTOR_X as closely as possible. */ | |
e0c8463a JB |
181 | #define DRM_MODE_SUBCONNECTOR_Automatic 0 |
182 | #define DRM_MODE_SUBCONNECTOR_Unknown 0 | |
183 | #define DRM_MODE_SUBCONNECTOR_DVID 3 | |
184 | #define DRM_MODE_SUBCONNECTOR_DVIA 4 | |
185 | #define DRM_MODE_SUBCONNECTOR_Composite 5 | |
186 | #define DRM_MODE_SUBCONNECTOR_SVIDEO 6 | |
187 | #define DRM_MODE_SUBCONNECTOR_Component 8 | |
aeaa1ad3 | 188 | #define DRM_MODE_SUBCONNECTOR_SCART 9 |
e0c8463a JB |
189 | |
190 | #define DRM_MODE_CONNECTOR_Unknown 0 | |
191 | #define DRM_MODE_CONNECTOR_VGA 1 | |
192 | #define DRM_MODE_CONNECTOR_DVII 2 | |
193 | #define DRM_MODE_CONNECTOR_DVID 3 | |
194 | #define DRM_MODE_CONNECTOR_DVIA 4 | |
195 | #define DRM_MODE_CONNECTOR_Composite 5 | |
196 | #define DRM_MODE_CONNECTOR_SVIDEO 6 | |
197 | #define DRM_MODE_CONNECTOR_LVDS 7 | |
198 | #define DRM_MODE_CONNECTOR_Component 8 | |
199 | #define DRM_MODE_CONNECTOR_9PinDIN 9 | |
200 | #define DRM_MODE_CONNECTOR_DisplayPort 10 | |
201 | #define DRM_MODE_CONNECTOR_HDMIA 11 | |
202 | #define DRM_MODE_CONNECTOR_HDMIB 12 | |
74bd3c26 | 203 | #define DRM_MODE_CONNECTOR_TV 13 |
7970e677 | 204 | #define DRM_MODE_CONNECTOR_eDP 14 |
a7331e5c | 205 | #define DRM_MODE_CONNECTOR_VIRTUAL 15 |
f453ba04 DA |
206 | |
207 | struct drm_mode_get_connector { | |
208 | ||
1d7f83d5 AB |
209 | __u64 encoders_ptr; |
210 | __u64 modes_ptr; | |
211 | __u64 props_ptr; | |
212 | __u64 prop_values_ptr; | |
f453ba04 | 213 | |
1d7f83d5 AB |
214 | __u32 count_modes; |
215 | __u32 count_props; | |
216 | __u32 count_encoders; | |
f453ba04 | 217 | |
1d7f83d5 AB |
218 | __u32 encoder_id; /**< Current Encoder */ |
219 | __u32 connector_id; /**< Id */ | |
220 | __u32 connector_type; | |
221 | __u32 connector_type_id; | |
f453ba04 | 222 | |
1d7f83d5 AB |
223 | __u32 connection; |
224 | __u32 mm_width, mm_height; /**< HxW in millimeters */ | |
225 | __u32 subpixel; | |
f453ba04 DA |
226 | }; |
227 | ||
e0c8463a JB |
228 | #define DRM_MODE_PROP_PENDING (1<<0) |
229 | #define DRM_MODE_PROP_RANGE (1<<1) | |
230 | #define DRM_MODE_PROP_IMMUTABLE (1<<2) | |
231 | #define DRM_MODE_PROP_ENUM (1<<3) /* enumerated type with text strings */ | |
232 | #define DRM_MODE_PROP_BLOB (1<<4) | |
49e27545 | 233 | #define DRM_MODE_PROP_BITMASK (1<<5) /* bitmask of enumerated types */ |
f453ba04 DA |
234 | |
235 | struct drm_mode_property_enum { | |
1d7f83d5 | 236 | __u64 value; |
e0c8463a | 237 | char name[DRM_PROP_NAME_LEN]; |
f453ba04 DA |
238 | }; |
239 | ||
240 | struct drm_mode_get_property { | |
1d7f83d5 AB |
241 | __u64 values_ptr; /* values and blob lengths */ |
242 | __u64 enum_blob_ptr; /* enum and blob id ptrs */ | |
f453ba04 | 243 | |
1d7f83d5 AB |
244 | __u32 prop_id; |
245 | __u32 flags; | |
e0c8463a | 246 | char name[DRM_PROP_NAME_LEN]; |
f453ba04 | 247 | |
1d7f83d5 AB |
248 | __u32 count_values; |
249 | __u32 count_enum_blobs; | |
f453ba04 DA |
250 | }; |
251 | ||
252 | struct drm_mode_connector_set_property { | |
1d7f83d5 AB |
253 | __u64 value; |
254 | __u32 prop_id; | |
255 | __u32 connector_id; | |
f453ba04 DA |
256 | }; |
257 | ||
c543188a PZ |
258 | struct drm_mode_obj_get_properties { |
259 | __u64 props_ptr; | |
260 | __u64 prop_values_ptr; | |
261 | __u32 count_props; | |
262 | __u32 obj_id; | |
263 | __u32 obj_type; | |
264 | }; | |
265 | ||
266 | struct drm_mode_obj_set_property { | |
267 | __u64 value; | |
268 | __u32 prop_id; | |
269 | __u32 obj_id; | |
270 | __u32 obj_type; | |
271 | }; | |
272 | ||
f453ba04 | 273 | struct drm_mode_get_blob { |
1d7f83d5 AB |
274 | __u32 blob_id; |
275 | __u32 length; | |
276 | __u64 data; | |
f453ba04 DA |
277 | }; |
278 | ||
279 | struct drm_mode_fb_cmd { | |
1d7f83d5 AB |
280 | __u32 fb_id; |
281 | __u32 width, height; | |
282 | __u32 pitch; | |
283 | __u32 bpp; | |
284 | __u32 depth; | |
e0c8463a | 285 | /* driver specific handle */ |
1d7f83d5 | 286 | __u32 handle; |
f453ba04 DA |
287 | }; |
288 | ||
cc5b6f00 | 289 | #define DRM_MODE_FB_INTERLACED (1<<0) /* for interlaced framebuffers */ |
308e5bcb JB |
290 | |
291 | struct drm_mode_fb_cmd2 { | |
292 | __u32 fb_id; | |
293 | __u32 width, height; | |
294 | __u32 pixel_format; /* fourcc code from drm_fourcc.h */ | |
295 | __u32 flags; /* see above flags */ | |
296 | ||
297 | /* | |
298 | * In case of planar formats, this ioctl allows up to 4 | |
299 | * buffer objects with offets and pitches per plane. | |
300 | * The pitch and offset order is dictated by the fourcc, | |
301 | * e.g. NV12 (http://fourcc.org/yuv.php#NV12) is described as: | |
302 | * | |
303 | * YUV 4:2:0 image with a plane of 8 bit Y samples | |
304 | * followed by an interleaved U/V plane containing | |
305 | * 8 bit 2x2 subsampled colour difference samples. | |
306 | * | |
307 | * So it would consist of Y as offset[0] and UV as | |
308 | * offeset[1]. Note that offset[0] will generally | |
309 | * be 0. | |
310 | */ | |
311 | __u32 handles[4]; | |
312 | __u32 pitches[4]; /* pitch for each plane */ | |
313 | __u32 offsets[4]; /* offset of each plane */ | |
314 | }; | |
315 | ||
884840aa JB |
316 | #define DRM_MODE_FB_DIRTY_ANNOTATE_COPY 0x01 |
317 | #define DRM_MODE_FB_DIRTY_ANNOTATE_FILL 0x02 | |
318 | #define DRM_MODE_FB_DIRTY_FLAGS 0x03 | |
319 | ||
a5cd3351 XW |
320 | #define DRM_MODE_FB_DIRTY_MAX_CLIPS 256 |
321 | ||
884840aa JB |
322 | /* |
323 | * Mark a region of a framebuffer as dirty. | |
324 | * | |
325 | * Some hardware does not automatically update display contents | |
326 | * as a hardware or software draw to a framebuffer. This ioctl | |
327 | * allows userspace to tell the kernel and the hardware what | |
328 | * regions of the framebuffer have changed. | |
329 | * | |
330 | * The kernel or hardware is free to update more then just the | |
331 | * region specified by the clip rects. The kernel or hardware | |
332 | * may also delay and/or coalesce several calls to dirty into a | |
333 | * single update. | |
334 | * | |
335 | * Userspace may annotate the updates, the annotates are a | |
336 | * promise made by the caller that the change is either a copy | |
337 | * of pixels or a fill of a single color in the region specified. | |
338 | * | |
339 | * If the DRM_MODE_FB_DIRTY_ANNOTATE_COPY flag is given then | |
340 | * the number of updated regions are half of num_clips given, | |
341 | * where the clip rects are paired in src and dst. The width and | |
342 | * height of each one of the pairs must match. | |
343 | * | |
344 | * If the DRM_MODE_FB_DIRTY_ANNOTATE_FILL flag is given the caller | |
345 | * promises that the region specified of the clip rects is filled | |
346 | * completely with a single color as given in the color argument. | |
347 | */ | |
348 | ||
349 | struct drm_mode_fb_dirty_cmd { | |
350 | __u32 fb_id; | |
351 | __u32 flags; | |
352 | __u32 color; | |
353 | __u32 num_clips; | |
354 | __u64 clips_ptr; | |
355 | }; | |
356 | ||
f453ba04 | 357 | struct drm_mode_mode_cmd { |
1d7f83d5 | 358 | __u32 connector_id; |
f453ba04 DA |
359 | struct drm_mode_modeinfo mode; |
360 | }; | |
361 | ||
7c4eaca4 JB |
362 | #define DRM_MODE_CURSOR_BO 0x01 |
363 | #define DRM_MODE_CURSOR_MOVE 0x02 | |
364 | #define DRM_MODE_CURSOR_FLAGS 0x03 | |
f453ba04 DA |
365 | |
366 | /* | |
25985edc | 367 | * depending on the value in flags different members are used. |
f453ba04 DA |
368 | * |
369 | * CURSOR_BO uses | |
715f59cc | 370 | * crtc_id |
f453ba04 DA |
371 | * width |
372 | * height | |
715f59cc | 373 | * handle - if 0 turns the cursor off |
f453ba04 DA |
374 | * |
375 | * CURSOR_MOVE uses | |
715f59cc | 376 | * crtc_id |
f453ba04 DA |
377 | * x |
378 | * y | |
379 | */ | |
380 | struct drm_mode_cursor { | |
1d7f83d5 AB |
381 | __u32 flags; |
382 | __u32 crtc_id; | |
383 | __s32 x; | |
384 | __s32 y; | |
385 | __u32 width; | |
386 | __u32 height; | |
e0c8463a | 387 | /* driver specific handle */ |
1d7f83d5 | 388 | __u32 handle; |
f453ba04 DA |
389 | }; |
390 | ||
4c813d4d DA |
391 | struct drm_mode_cursor2 { |
392 | __u32 flags; | |
393 | __u32 crtc_id; | |
394 | __s32 x; | |
395 | __s32 y; | |
396 | __u32 width; | |
397 | __u32 height; | |
398 | /* driver specific handle */ | |
399 | __u32 handle; | |
400 | __s32 hot_x; | |
401 | __s32 hot_y; | |
402 | }; | |
403 | ||
f453ba04 | 404 | struct drm_mode_crtc_lut { |
1d7f83d5 AB |
405 | __u32 crtc_id; |
406 | __u32 gamma_size; | |
f453ba04 DA |
407 | |
408 | /* pointers to arrays */ | |
1d7f83d5 AB |
409 | __u64 red; |
410 | __u64 green; | |
411 | __u64 blue; | |
f453ba04 DA |
412 | }; |
413 | ||
d91d8a3f | 414 | #define DRM_MODE_PAGE_FLIP_EVENT 0x01 |
9bba0c42 KP |
415 | #define DRM_MODE_PAGE_FLIP_ASYNC 0x02 |
416 | #define DRM_MODE_PAGE_FLIP_FLAGS (DRM_MODE_PAGE_FLIP_EVENT|DRM_MODE_PAGE_FLIP_ASYNC) | |
d91d8a3f KH |
417 | |
418 | /* | |
419 | * Request a page flip on the specified crtc. | |
420 | * | |
421 | * This ioctl will ask KMS to schedule a page flip for the specified | |
422 | * crtc. Once any pending rendering targeting the specified fb (as of | |
423 | * ioctl time) has completed, the crtc will be reprogrammed to display | |
424 | * that fb after the next vertical refresh. The ioctl returns | |
425 | * immediately, but subsequent rendering to the current fb will block | |
426 | * in the execbuffer ioctl until the page flip happens. If a page | |
427 | * flip is already pending as the ioctl is called, EBUSY will be | |
428 | * returned. | |
429 | * | |
9bba0c42 KP |
430 | * Flag DRM_MODE_PAGE_FLIP_EVENT requests that drm sends back a vblank |
431 | * event (see drm.h: struct drm_event_vblank) when the page flip is | |
432 | * done. The user_data field passed in with this ioctl will be | |
433 | * returned as the user_data field in the vblank event struct. | |
434 | * | |
435 | * Flag DRM_MODE_PAGE_FLIP_ASYNC requests that the flip happen | |
436 | * 'as soon as possible', meaning that it not delay waiting for vblank. | |
437 | * This may cause tearing on the screen. | |
d91d8a3f KH |
438 | * |
439 | * The reserved field must be zero until we figure out something | |
440 | * clever to use it for. | |
441 | */ | |
442 | ||
443 | struct drm_mode_crtc_page_flip { | |
444 | __u32 crtc_id; | |
445 | __u32 fb_id; | |
446 | __u32 flags; | |
447 | __u32 reserved; | |
448 | __u64 user_data; | |
449 | }; | |
450 | ||
ff72145b DA |
451 | /* create a dumb scanout buffer */ |
452 | struct drm_mode_create_dumb { | |
453 | uint32_t height; | |
454 | uint32_t width; | |
455 | uint32_t bpp; | |
456 | uint32_t flags; | |
457 | /* handle, pitch, size will be returned */ | |
458 | uint32_t handle; | |
459 | uint32_t pitch; | |
460 | uint64_t size; | |
461 | }; | |
462 | ||
463 | /* set up for mmap of a dumb scanout buffer */ | |
464 | struct drm_mode_map_dumb { | |
465 | /** Handle for the object being mapped. */ | |
466 | __u32 handle; | |
467 | __u32 pad; | |
468 | /** | |
469 | * Fake offset to use for subsequent mmap call | |
470 | * | |
471 | * This is a fixed-size type for 32/64 compatibility. | |
472 | */ | |
473 | __u64 offset; | |
474 | }; | |
475 | ||
476 | struct drm_mode_destroy_dumb { | |
477 | uint32_t handle; | |
478 | }; | |
479 | ||
f453ba04 | 480 | #endif |