[mirror_ubuntu-eoan-kernel.git] / include / uapi / drm / exynos_drm.h

/* SPDX-License-Identifier: GPL-2.0+ WITH Linux-syscall-note */
/* exynos_drm.h
 *
 * Copyright (c) 2011 Samsung Electronics Co., Ltd.
 * Authors:
 *	Inki Dae <inki.dae@samsung.com>
 *	Joonyoung Shim <jy0922.shim@samsung.com>
 *	Seung-Woo Kim <sw0312.kim@samsung.com>
 *
 * This program is free software; you can redistribute  it and/or modify it
 * under  the terms of  the GNU General  Public License as published by the
 * Free Software Foundation;  either version 2 of the  License, or (at your
 * option) any later version.
 */

#ifndef _UAPI_EXYNOS_DRM_H_
#define _UAPI_EXYNOS_DRM_H_

#include "drm.h"

#if defined(__cplusplus)
extern "C" {
#endif

/**
 * User-desired buffer creation information structure.
 *
 * @size: user-desired memory allocation size.
 *	- this size value would be page-aligned internally.
 * @flags: user request for setting memory type or cache attributes.
 * @handle: returned a handle to created gem object.
 *	- this handle will be set by gem module of kernel side.
 */
struct drm_exynos_gem_create {
	__u64 size;
	__u32 flags;
	__u32 handle;
};

/**
 * A structure for getting a fake-offset that can be used with mmap.
 *
 * @handle: handle of gem object.
 * @reserved: just padding to be 64-bit aligned.
 * @offset: a fake-offset of gem object.
 */
struct drm_exynos_gem_map {
	__u32 handle;
	__u32 reserved;
	__u64 offset;
};

/**
 * A structure to gem information.
 *
 * @handle: a handle to gem object created.
 * @flags: flag value including memory type and cache attribute and
 *	this value would be set by driver.
 * @size: size to memory region allocated by gem and this size would
 *	be set by driver.
 */
struct drm_exynos_gem_info {
	__u32 handle;
	__u32 flags;
	__u64 size;
};

/**
 * A structure for user connection request of virtual display.
 *
 * @connection: indicate whether doing connetion or not by user.
 * @extensions: if this value is 1 then the vidi driver would need additional
 *	128bytes edid data.
 * @edid: the edid data pointer from user side.
 */
struct drm_exynos_vidi_connection {
	__u32 connection;
	__u32 extensions;
	__u64 edid;
};

/* memory type definitions. */
enum e_drm_exynos_gem_mem_type {
	/* Physically Continuous memory and used as default. */
	EXYNOS_BO_CONTIG	= 0 << 0,
	/* Physically Non-Continuous memory. */
	EXYNOS_BO_NONCONTIG	= 1 << 0,
	/* non-cachable mapping and used as default. */
	EXYNOS_BO_NONCACHABLE	= 0 << 1,
	/* cachable mapping. */
	EXYNOS_BO_CACHABLE	= 1 << 1,
	/* write-combine mapping. */
	EXYNOS_BO_WC		= 1 << 2,
	EXYNOS_BO_MASK		= EXYNOS_BO_NONCONTIG | EXYNOS_BO_CACHABLE |
					EXYNOS_BO_WC
};

struct drm_exynos_g2d_get_ver {
	__u32	major;
	__u32	minor;
};

struct drm_exynos_g2d_cmd {
	__u32	offset;
	__u32	data;
};

enum drm_exynos_g2d_buf_type {
	G2D_BUF_USERPTR = 1 << 31,
};

enum drm_exynos_g2d_event_type {
	G2D_EVENT_NOT,
	G2D_EVENT_NONSTOP,
	G2D_EVENT_STOP,		/* not yet */
};

struct drm_exynos_g2d_userptr {
	unsigned long userptr;
	unsigned long size;
};

struct drm_exynos_g2d_set_cmdlist {
	__u64					cmd;
	__u64					cmd_buf;
	__u32					cmd_nr;
	__u32					cmd_buf_nr;

	/* for g2d event */
	__u64					event_type;
	__u64					user_data;
};

struct drm_exynos_g2d_exec {
	__u64					async;
};

enum drm_exynos_ops_id {
	EXYNOS_DRM_OPS_SRC,
	EXYNOS_DRM_OPS_DST,
	EXYNOS_DRM_OPS_MAX,
};

struct drm_exynos_sz {
	__u32	hsize;
	__u32	vsize;
};

struct drm_exynos_pos {
	__u32	x;
	__u32	y;
	__u32	w;
	__u32	h;
};

enum drm_exynos_flip {
	EXYNOS_DRM_FLIP_NONE = (0 << 0),
	EXYNOS_DRM_FLIP_VERTICAL = (1 << 0),
	EXYNOS_DRM_FLIP_HORIZONTAL = (1 << 1),
	EXYNOS_DRM_FLIP_BOTH = EXYNOS_DRM_FLIP_VERTICAL |
			EXYNOS_DRM_FLIP_HORIZONTAL,
};

enum drm_exynos_degree {
	EXYNOS_DRM_DEGREE_0,
	EXYNOS_DRM_DEGREE_90,
	EXYNOS_DRM_DEGREE_180,
	EXYNOS_DRM_DEGREE_270,
};

enum drm_exynos_planer {
	EXYNOS_DRM_PLANAR_Y,
	EXYNOS_DRM_PLANAR_CB,
	EXYNOS_DRM_PLANAR_CR,
	EXYNOS_DRM_PLANAR_MAX,
};

/**
 * A structure for ipp supported property list.
 *
 * @version: version of this structure.
 * @ipp_id: id of ipp driver.
 * @count: count of ipp driver.
 * @writeback: flag of writeback supporting.
 * @flip: flag of flip supporting.
 * @degree: flag of degree information.
 * @csc: flag of csc supporting.
 * @crop: flag of crop supporting.
 * @scale: flag of scale supporting.
 * @refresh_min: min hz of refresh.
 * @refresh_max: max hz of refresh.
 * @crop_min: crop min resolution.
 * @crop_max: crop max resolution.
 * @scale_min: scale min resolution.
 * @scale_max: scale max resolution.
 */
struct drm_exynos_ipp_prop_list {
	__u32	version;
	__u32	ipp_id;
	__u32	count;
	__u32	writeback;
	__u32	flip;
	__u32	degree;
	__u32	csc;
	__u32	crop;
	__u32	scale;
	__u32	refresh_min;
	__u32	refresh_max;
	__u32	reserved;
	struct drm_exynos_sz	crop_min;
	struct drm_exynos_sz	crop_max;
	struct drm_exynos_sz	scale_min;
	struct drm_exynos_sz	scale_max;
};

/**
 * A structure for ipp config.
 *
 * @ops_id: property of operation directions.
 * @flip: property of mirror, flip.
 * @degree: property of rotation degree.
 * @fmt: property of image format.
 * @sz: property of image size.
 * @pos: property of image position(src-cropped,dst-scaler).
 */
struct drm_exynos_ipp_config {
	__u32 ops_id;
	__u32 flip;
	__u32 degree;
	__u32	fmt;
	struct drm_exynos_sz	sz;
	struct drm_exynos_pos	pos;
};

enum drm_exynos_ipp_cmd {
	IPP_CMD_NONE,
	IPP_CMD_M2M,
	IPP_CMD_WB,
	IPP_CMD_OUTPUT,
	IPP_CMD_MAX,
};

/**
 * A structure for ipp property.
 *
 * @config: source, destination config.
 * @cmd: definition of command.
 * @ipp_id: id of ipp driver.
 * @prop_id: id of property.
 * @refresh_rate: refresh rate.
 */
struct drm_exynos_ipp_property {
	struct drm_exynos_ipp_config config[EXYNOS_DRM_OPS_MAX];
	__u32	cmd;
	__u32	ipp_id;
	__u32	prop_id;
	__u32	refresh_rate;
};

enum drm_exynos_ipp_buf_type {
	IPP_BUF_ENQUEUE,
	IPP_BUF_DEQUEUE,
};

/**
 * A structure for ipp buffer operations.
 *
 * @ops_id: operation directions.
 * @buf_type: definition of buffer.
 * @prop_id: id of property.
 * @buf_id: id of buffer.
 * @handle: Y, Cb, Cr each planar handle.
 * @user_data: user data.
 */
struct drm_exynos_ipp_queue_buf {
	__u32	ops_id;
	__u32	buf_type;
	__u32	prop_id;
	__u32	buf_id;
	__u32	handle[EXYNOS_DRM_PLANAR_MAX];
	__u32	reserved;
	__u64	user_data;
};

enum drm_exynos_ipp_ctrl {
	IPP_CTRL_PLAY,
	IPP_CTRL_STOP,
	IPP_CTRL_PAUSE,
	IPP_CTRL_RESUME,
	IPP_CTRL_MAX,
};

/**
 * A structure for ipp start/stop operations.
 *
 * @prop_id: id of property.
 * @ctrl: definition of control.
 */
struct drm_exynos_ipp_cmd_ctrl {
	__u32	prop_id;
	__u32	ctrl;
};

#define DRM_EXYNOS_GEM_CREATE		0x00
#define DRM_EXYNOS_GEM_MAP		0x01
/* Reserved 0x03 ~ 0x05 for exynos specific gem ioctl */
#define DRM_EXYNOS_GEM_GET		0x04
#define DRM_EXYNOS_VIDI_CONNECTION	0x07

/* G2D */
#define DRM_EXYNOS_G2D_GET_VER		0x20
#define DRM_EXYNOS_G2D_SET_CMDLIST	0x21
#define DRM_EXYNOS_G2D_EXEC		0x22

/* IPP - Image Post Processing */
#define DRM_EXYNOS_IPP_GET_PROPERTY	0x30
#define DRM_EXYNOS_IPP_SET_PROPERTY	0x31
#define DRM_EXYNOS_IPP_QUEUE_BUF	0x32
#define DRM_EXYNOS_IPP_CMD_CTRL	0x33

#define DRM_IOCTL_EXYNOS_GEM_CREATE		DRM_IOWR(DRM_COMMAND_BASE + \
		DRM_EXYNOS_GEM_CREATE, struct drm_exynos_gem_create)
#define DRM_IOCTL_EXYNOS_GEM_MAP		DRM_IOWR(DRM_COMMAND_BASE + \
		DRM_EXYNOS_GEM_MAP, struct drm_exynos_gem_map)
#define DRM_IOCTL_EXYNOS_GEM_GET	DRM_IOWR(DRM_COMMAND_BASE + \
		DRM_EXYNOS_GEM_GET,	struct drm_exynos_gem_info)

#define DRM_IOCTL_EXYNOS_VIDI_CONNECTION	DRM_IOWR(DRM_COMMAND_BASE + \
		DRM_EXYNOS_VIDI_CONNECTION, struct drm_exynos_vidi_connection)

#define DRM_IOCTL_EXYNOS_G2D_GET_VER		DRM_IOWR(DRM_COMMAND_BASE + \
		DRM_EXYNOS_G2D_GET_VER, struct drm_exynos_g2d_get_ver)
#define DRM_IOCTL_EXYNOS_G2D_SET_CMDLIST	DRM_IOWR(DRM_COMMAND_BASE + \
		DRM_EXYNOS_G2D_SET_CMDLIST, struct drm_exynos_g2d_set_cmdlist)
#define DRM_IOCTL_EXYNOS_G2D_EXEC		DRM_IOWR(DRM_COMMAND_BASE + \
		DRM_EXYNOS_G2D_EXEC, struct drm_exynos_g2d_exec)

#define DRM_IOCTL_EXYNOS_IPP_GET_PROPERTY	DRM_IOWR(DRM_COMMAND_BASE + \
		DRM_EXYNOS_IPP_GET_PROPERTY, struct drm_exynos_ipp_prop_list)
#define DRM_IOCTL_EXYNOS_IPP_SET_PROPERTY	DRM_IOWR(DRM_COMMAND_BASE + \
		DRM_EXYNOS_IPP_SET_PROPERTY, struct drm_exynos_ipp_property)
#define DRM_IOCTL_EXYNOS_IPP_QUEUE_BUF	DRM_IOWR(DRM_COMMAND_BASE + \
		DRM_EXYNOS_IPP_QUEUE_BUF, struct drm_exynos_ipp_queue_buf)
#define DRM_IOCTL_EXYNOS_IPP_CMD_CTRL		DRM_IOWR(DRM_COMMAND_BASE + \
		DRM_EXYNOS_IPP_CMD_CTRL, struct drm_exynos_ipp_cmd_ctrl)

/* EXYNOS specific events */
#define DRM_EXYNOS_G2D_EVENT		0x80000000
#define DRM_EXYNOS_IPP_EVENT		0x80000001

struct drm_exynos_g2d_event {
	struct drm_event	base;
	__u64			user_data;
	__u32			tv_sec;
	__u32			tv_usec;
	__u32			cmdlist_no;
	__u32			reserved;
};

struct drm_exynos_ipp_event {
	struct drm_event	base;
	__u64			user_data;
	__u32			tv_sec;
	__u32			tv_usec;
	__u32			prop_id;
	__u32			reserved;
	__u32			buf_id[EXYNOS_DRM_OPS_MAX];
};

#if defined(__cplusplus)
}
#endif

#endif /* _UAPI_EXYNOS_DRM_H_ */
Commit	Line	Data
e2be04c7	1	/* SPDX-License-Identifier: GPL-2.0+ WITH Linux-syscall-note */
718dcedd DH	2	/* exynos_drm.h
	3	*
	4	* Copyright (c) 2011 Samsung Electronics Co., Ltd.
	5	* Authors:
	6	* Inki Dae <inki.dae@samsung.com>
	7	* Joonyoung Shim <jy0922.shim@samsung.com>
	8	* Seung-Woo Kim <sw0312.kim@samsung.com>
	9	*
d81aecb5 ID	10	* This program is free software; you can redistribute it and/or modify it
	11	* under the terms of the GNU General Public License as published by the
	12	* Free Software Foundation; either version 2 of the License, or (at your
	13	* option) any later version.
718dcedd DH	14	*/
	15
	16	#ifndef _UAPI_EXYNOS_DRM_H_
	17	#define _UAPI_EXYNOS_DRM_H_
	18
19b1e97a	19	#include "drm.h"
718dcedd	20
37a96bed EV	21	#if defined(__cplusplus)
	22	extern "C" {
	23	#endif
	24
718dcedd DH	25	/**
	26	* User-desired buffer creation information structure.
	27	*
	28	* @size: user-desired memory allocation size.
	29	* - this size value would be page-aligned internally.
	30	* @flags: user request for setting memory type or cache attributes.
	31	* @handle: returned a handle to created gem object.
	32	* - this handle will be set by gem module of kernel side.
	33	*/
	34	struct drm_exynos_gem_create {
6615b20f	35	__u64 size;
cbf0acef AH	36	__u32 flags;
cbf0acef AH	37	__u32 handle;
718dcedd DH	38	};
718dcedd DH	39
6564c65f JS	40	/**
	41	* A structure for getting a fake-offset that can be used with mmap.
	42	*
	43	* @handle: handle of gem object.
	44	* @reserved: just padding to be 64-bit aligned.
	45	* @offset: a fake-offset of gem object.
	46	*/
	47	struct drm_exynos_gem_map {
	48	__u32 handle;
	49	__u32 reserved;
	50	__u64 offset;
	51	};
	52
718dcedd DH	53	/**
	54	* A structure to gem information.
	55	*
	56	* @handle: a handle to gem object created.
	57	* @flags: flag value including memory type and cache attribute and
	58	* this value would be set by driver.
	59	* @size: size to memory region allocated by gem and this size would
	60	* be set by driver.
	61	*/
	62	struct drm_exynos_gem_info {
cbf0acef AH	63	__u32 handle;
cbf0acef AH	64	__u32 flags;
6615b20f	65	__u64 size;
718dcedd DH	66	};
	67
	68	/**
	69	* A structure for user connection request of virtual display.
	70	*
	71	* @connection: indicate whether doing connetion or not by user.
	72	* @extensions: if this value is 1 then the vidi driver would need additional
	73	* 128bytes edid data.
	74	* @edid: the edid data pointer from user side.
	75	*/
	76	struct drm_exynos_vidi_connection {
cbf0acef AH	77	__u32 connection;
cbf0acef AH	78	__u32 extensions;
6615b20f	79	__u64 edid;
718dcedd DH	80	};
	81
	82	/* memory type definitions. */
	83	enum e_drm_exynos_gem_mem_type {
	84	/* Physically Continuous memory and used as default. */
	85	EXYNOS_BO_CONTIG = 0 << 0,
	86	/* Physically Non-Continuous memory. */
	87	EXYNOS_BO_NONCONTIG = 1 << 0,
	88	/* non-cachable mapping and used as default. */
	89	EXYNOS_BO_NONCACHABLE = 0 << 1,
	90	/* cachable mapping. */
	91	EXYNOS_BO_CACHABLE = 1 << 1,
	92	/* write-combine mapping. */
	93	EXYNOS_BO_WC = 1 << 2,
	94	EXYNOS_BO_MASK = EXYNOS_BO_NONCONTIG \| EXYNOS_BO_CACHABLE \|
	95	EXYNOS_BO_WC
	96	};
	97
	98	struct drm_exynos_g2d_get_ver {
	99	__u32 major;
	100	__u32 minor;
	101	};
	102
	103	struct drm_exynos_g2d_cmd {
	104	__u32 offset;
	105	__u32 data;
	106	};
	107
2a3098ff ID	108	enum drm_exynos_g2d_buf_type {
	109	G2D_BUF_USERPTR = 1 << 31,
	110	};
	111
718dcedd DH	112	enum drm_exynos_g2d_event_type {
	113	G2D_EVENT_NOT,
	114	G2D_EVENT_NONSTOP,
	115	G2D_EVENT_STOP, /* not yet */
	116	};
	117
2a3098ff ID	118	struct drm_exynos_g2d_userptr {
	119	unsigned long userptr;
	120	unsigned long size;
	121	};
	122
718dcedd DH	123	struct drm_exynos_g2d_set_cmdlist {
718dcedd DH	124	__u64 cmd;
2a3098ff	125	__u64 cmd_buf;
718dcedd	126	__u32 cmd_nr;
2a3098ff	127	__u32 cmd_buf_nr;
718dcedd DH	128
	129	/* for g2d event */
	130	__u64 event_type;
	131	__u64 user_data;
	132	};
	133
	134	struct drm_exynos_g2d_exec {
	135	__u64 async;
	136	};
	137
cb471f14 EK	138	enum drm_exynos_ops_id {
	139	EXYNOS_DRM_OPS_SRC,
	140	EXYNOS_DRM_OPS_DST,
	141	EXYNOS_DRM_OPS_MAX,
	142	};
	143
	144	struct drm_exynos_sz {
	145	__u32 hsize;
	146	__u32 vsize;
	147	};
	148
	149	struct drm_exynos_pos {
	150	__u32 x;
	151	__u32 y;
	152	__u32 w;
	153	__u32 h;
	154	};
	155
	156	enum drm_exynos_flip {
	157	EXYNOS_DRM_FLIP_NONE = (0 << 0),
	158	EXYNOS_DRM_FLIP_VERTICAL = (1 << 0),
	159	EXYNOS_DRM_FLIP_HORIZONTAL = (1 << 1),
4f21877c EK	160	EXYNOS_DRM_FLIP_BOTH = EXYNOS_DRM_FLIP_VERTICAL \|
4f21877c EK	161	EXYNOS_DRM_FLIP_HORIZONTAL,
cb471f14 EK	162	};
	163
	164	enum drm_exynos_degree {
	165	EXYNOS_DRM_DEGREE_0,
	166	EXYNOS_DRM_DEGREE_90,
	167	EXYNOS_DRM_DEGREE_180,
	168	EXYNOS_DRM_DEGREE_270,
	169	};
	170
	171	enum drm_exynos_planer {
	172	EXYNOS_DRM_PLANAR_Y,
	173	EXYNOS_DRM_PLANAR_CB,
	174	EXYNOS_DRM_PLANAR_CR,
	175	EXYNOS_DRM_PLANAR_MAX,
	176	};
	177
	178	/**
	179	* A structure for ipp supported property list.
	180	*
	181	* @version: version of this structure.
	182	* @ipp_id: id of ipp driver.
	183	* @count: count of ipp driver.
	184	* @writeback: flag of writeback supporting.
	185	* @flip: flag of flip supporting.
	186	* @degree: flag of degree information.
	187	* @csc: flag of csc supporting.
	188	* @crop: flag of crop supporting.
	189	* @scale: flag of scale supporting.
	190	* @refresh_min: min hz of refresh.
	191	* @refresh_max: max hz of refresh.
	192	* @crop_min: crop min resolution.
	193	* @crop_max: crop max resolution.
	194	* @scale_min: scale min resolution.
	195	* @scale_max: scale max resolution.
	196	*/
	197	struct drm_exynos_ipp_prop_list {
	198	__u32 version;
	199	__u32 ipp_id;
	200	__u32 count;
	201	__u32 writeback;
	202	__u32 flip;
	203	__u32 degree;
	204	__u32 csc;
	205	__u32 crop;
	206	__u32 scale;
	207	__u32 refresh_min;
	208	__u32 refresh_max;
	209	__u32 reserved;
	210	struct drm_exynos_sz crop_min;
	211	struct drm_exynos_sz crop_max;
	212	struct drm_exynos_sz scale_min;
	213	struct drm_exynos_sz scale_max;
	214	};
	215
	216	/**
	217	* A structure for ipp config.
	218	*
	219	* @ops_id: property of operation directions.
	220	* @flip: property of mirror, flip.
	221	* @degree: property of rotation degree.
	222	* @fmt: property of image format.
	223	* @sz: property of image size.
	224	* @pos: property of image position(src-cropped,dst-scaler).
	225	*/
226	struct drm_exynos_ipp_config {
cbf0acef AH	227	__u32 ops_id;
	228	__u32 flip;
	229	__u32 degree;
cb471f14 EK	230	__u32 fmt;
	231	struct drm_exynos_sz sz;
	232	struct drm_exynos_pos pos;
	233	};
	234
	235	enum drm_exynos_ipp_cmd {
	236	IPP_CMD_NONE,
	237	IPP_CMD_M2M,
	238	IPP_CMD_WB,
	239	IPP_CMD_OUTPUT,
	240	IPP_CMD_MAX,
	241	};
	242
	243	/**
	244	* A structure for ipp property.
	245	*
	246	* @config: source, destination config.
	247	* @cmd: definition of command.
	248	* @ipp_id: id of ipp driver.
	249	* @prop_id: id of property.
	250	* @refresh_rate: refresh rate.
	251	*/
	252	struct drm_exynos_ipp_property {
	253	struct drm_exynos_ipp_config config[EXYNOS_DRM_OPS_MAX];
cbf0acef	254	__u32 cmd;
cb471f14 EK	255	__u32 ipp_id;
	256	__u32 prop_id;
	257	__u32 refresh_rate;
	258	};
	259
	260	enum drm_exynos_ipp_buf_type {
	261	IPP_BUF_ENQUEUE,
	262	IPP_BUF_DEQUEUE,
	263	};
	264
	265	/**
	266	* A structure for ipp buffer operations.
	267	*
	268	* @ops_id: operation directions.
	269	* @buf_type: definition of buffer.
	270	* @prop_id: id of property.
	271	* @buf_id: id of buffer.
	272	* @handle: Y, Cb, Cr each planar handle.
	273	* @user_data: user data.
	274	*/
	275	struct drm_exynos_ipp_queue_buf {
cbf0acef AH	276	__u32 ops_id;
cbf0acef AH	277	__u32 buf_type;
cb471f14 EK	278	__u32 prop_id;
	279	__u32 buf_id;
	280	__u32 handle[EXYNOS_DRM_PLANAR_MAX];
	281	__u32 reserved;
	282	__u64 user_data;
	283	};
	284
	285	enum drm_exynos_ipp_ctrl {
	286	IPP_CTRL_PLAY,
	287	IPP_CTRL_STOP,
	288	IPP_CTRL_PAUSE,
	289	IPP_CTRL_RESUME,
	290	IPP_CTRL_MAX,
	291	};
	292
	293	/**
	294	* A structure for ipp start/stop operations.
	295	*
	296	* @prop_id: id of property.
	297	* @ctrl: definition of control.
	298	*/
	299	struct drm_exynos_ipp_cmd_ctrl {
	300	__u32 prop_id;
cbf0acef	301	__u32 ctrl;
cb471f14 EK	302	};
cb471f14 EK	303
718dcedd	304	#define DRM_EXYNOS_GEM_CREATE 0x00
6564c65f	305	#define DRM_EXYNOS_GEM_MAP 0x01
718dcedd DH	306	/* Reserved 0x03 ~ 0x05 for exynos specific gem ioctl */
	307	#define DRM_EXYNOS_GEM_GET 0x04
	308	#define DRM_EXYNOS_VIDI_CONNECTION 0x07
	309
	310	/* G2D */
	311	#define DRM_EXYNOS_G2D_GET_VER 0x20
	312	#define DRM_EXYNOS_G2D_SET_CMDLIST 0x21
	313	#define DRM_EXYNOS_G2D_EXEC 0x22
	314
cb471f14 EK	315	/* IPP - Image Post Processing */
	316	#define DRM_EXYNOS_IPP_GET_PROPERTY 0x30
	317	#define DRM_EXYNOS_IPP_SET_PROPERTY 0x31
	318	#define DRM_EXYNOS_IPP_QUEUE_BUF 0x32
	319	#define DRM_EXYNOS_IPP_CMD_CTRL 0x33
	320
718dcedd DH	321	#define DRM_IOCTL_EXYNOS_GEM_CREATE DRM_IOWR(DRM_COMMAND_BASE + \
718dcedd DH	322	DRM_EXYNOS_GEM_CREATE, struct drm_exynos_gem_create)
6564c65f JS	323	#define DRM_IOCTL_EXYNOS_GEM_MAP DRM_IOWR(DRM_COMMAND_BASE + \
6564c65f JS	324	DRM_EXYNOS_GEM_MAP, struct drm_exynos_gem_map)
718dcedd DH	325	#define DRM_IOCTL_EXYNOS_GEM_GET DRM_IOWR(DRM_COMMAND_BASE + \
	326	DRM_EXYNOS_GEM_GET, struct drm_exynos_gem_info)
	327
	328	#define DRM_IOCTL_EXYNOS_VIDI_CONNECTION DRM_IOWR(DRM_COMMAND_BASE + \
	329	DRM_EXYNOS_VIDI_CONNECTION, struct drm_exynos_vidi_connection)
	330
	331	#define DRM_IOCTL_EXYNOS_G2D_GET_VER DRM_IOWR(DRM_COMMAND_BASE + \
	332	DRM_EXYNOS_G2D_GET_VER, struct drm_exynos_g2d_get_ver)
	333	#define DRM_IOCTL_EXYNOS_G2D_SET_CMDLIST DRM_IOWR(DRM_COMMAND_BASE + \
	334	DRM_EXYNOS_G2D_SET_CMDLIST, struct drm_exynos_g2d_set_cmdlist)
	335	#define DRM_IOCTL_EXYNOS_G2D_EXEC DRM_IOWR(DRM_COMMAND_BASE + \
	336	DRM_EXYNOS_G2D_EXEC, struct drm_exynos_g2d_exec)
	337
cb471f14 EK	338	#define DRM_IOCTL_EXYNOS_IPP_GET_PROPERTY DRM_IOWR(DRM_COMMAND_BASE + \
	339	DRM_EXYNOS_IPP_GET_PROPERTY, struct drm_exynos_ipp_prop_list)
	340	#define DRM_IOCTL_EXYNOS_IPP_SET_PROPERTY DRM_IOWR(DRM_COMMAND_BASE + \
	341	DRM_EXYNOS_IPP_SET_PROPERTY, struct drm_exynos_ipp_property)
	342	#define DRM_IOCTL_EXYNOS_IPP_QUEUE_BUF DRM_IOWR(DRM_COMMAND_BASE + \
	343	DRM_EXYNOS_IPP_QUEUE_BUF, struct drm_exynos_ipp_queue_buf)
	344	#define DRM_IOCTL_EXYNOS_IPP_CMD_CTRL DRM_IOWR(DRM_COMMAND_BASE + \
	345	DRM_EXYNOS_IPP_CMD_CTRL, struct drm_exynos_ipp_cmd_ctrl)
	346
718dcedd DH	347	/* EXYNOS specific events */
718dcedd DH	348	#define DRM_EXYNOS_G2D_EVENT 0x80000000
cb471f14	349	#define DRM_EXYNOS_IPP_EVENT 0x80000001
718dcedd DH	350
	351	struct drm_exynos_g2d_event {
	352	struct drm_event base;
	353	__u64 user_data;
	354	__u32 tv_sec;
	355	__u32 tv_usec;
	356	__u32 cmdlist_no;
	357	__u32 reserved;
	358	};
	359
cb471f14 EK	360	struct drm_exynos_ipp_event {
	361	struct drm_event base;
	362	__u64 user_data;
	363	__u32 tv_sec;
	364	__u32 tv_usec;
	365	__u32 prop_id;
	366	__u32 reserved;
	367	__u32 buf_id[EXYNOS_DRM_OPS_MAX];
	368	};
	369
37a96bed EV	370	#if defined(__cplusplus)
	371	}
	372	#endif
	373
718dcedd	374	#endif /* _UAPI_EXYNOS_DRM_H_ */