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718dcedd DH |
1 | /* |
2 | * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas. | |
3 | * All Rights Reserved. | |
4 | * | |
5 | * Permission is hereby granted, free of charge, to any person obtaining a | |
6 | * copy of this software and associated documentation files (the | |
7 | * "Software"), to deal in the Software without restriction, including | |
8 | * without limitation the rights to use, copy, modify, merge, publish, | |
9 | * distribute, sub license, and/or sell copies of the Software, and to | |
10 | * permit persons to whom the Software is furnished to do so, subject to | |
11 | * the following conditions: | |
12 | * | |
13 | * The above copyright notice and this permission notice (including the | |
14 | * next paragraph) shall be included in all copies or substantial portions | |
15 | * of the Software. | |
16 | * | |
17 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS | |
18 | * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF | |
19 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. | |
20 | * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR | |
21 | * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, | |
22 | * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE | |
23 | * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. | |
24 | * | |
25 | */ | |
26 | ||
27 | #ifndef _UAPI_I915_DRM_H_ | |
28 | #define _UAPI_I915_DRM_H_ | |
29 | ||
1049102f | 30 | #include "drm.h" |
718dcedd | 31 | |
b1c1f5c4 EV |
32 | #if defined(__cplusplus) |
33 | extern "C" { | |
34 | #endif | |
35 | ||
718dcedd DH |
36 | /* Please note that modifications to all structs defined here are |
37 | * subject to backwards-compatibility constraints. | |
38 | */ | |
39 | ||
cce723ed BW |
40 | /** |
41 | * DOC: uevents generated by i915 on it's device node | |
42 | * | |
43 | * I915_L3_PARITY_UEVENT - Generated when the driver receives a parity mismatch | |
44 | * event from the gpu l3 cache. Additional information supplied is ROW, | |
35a85ac6 BW |
45 | * BANK, SUBBANK, SLICE of the affected cacheline. Userspace should keep |
46 | * track of these events and if a specific cache-line seems to have a | |
47 | * persistent error remap it with the l3 remapping tool supplied in | |
48 | * intel-gpu-tools. The value supplied with the event is always 1. | |
cce723ed BW |
49 | * |
50 | * I915_ERROR_UEVENT - Generated upon error detection, currently only via | |
51 | * hangcheck. The error detection event is a good indicator of when things | |
52 | * began to go badly. The value supplied with the event is a 1 upon error | |
53 | * detection, and a 0 upon reset completion, signifying no more error | |
54 | * exists. NOTE: Disabling hangcheck or reset via module parameter will | |
55 | * cause the related events to not be seen. | |
56 | * | |
57 | * I915_RESET_UEVENT - Event is generated just before an attempt to reset the | |
58 | * the GPU. The value supplied with the event is always 1. NOTE: Disable | |
59 | * reset via module parameter will cause this event to not be seen. | |
60 | */ | |
61 | #define I915_L3_PARITY_UEVENT "L3_PARITY_ERROR" | |
62 | #define I915_ERROR_UEVENT "ERROR" | |
63 | #define I915_RESET_UEVENT "RESET" | |
718dcedd | 64 | |
3373ce2e ID |
65 | /* |
66 | * MOCS indexes used for GPU surfaces, defining the cacheability of the | |
67 | * surface data and the coherency for this data wrt. CPU vs. GPU accesses. | |
68 | */ | |
69 | enum i915_mocs_table_index { | |
70 | /* | |
71 | * Not cached anywhere, coherency between CPU and GPU accesses is | |
72 | * guaranteed. | |
73 | */ | |
74 | I915_MOCS_UNCACHED, | |
75 | /* | |
76 | * Cacheability and coherency controlled by the kernel automatically | |
77 | * based on the DRM_I915_GEM_SET_CACHING IOCTL setting and the current | |
78 | * usage of the surface (used for display scanout or not). | |
79 | */ | |
80 | I915_MOCS_PTE, | |
81 | /* | |
82 | * Cached in all GPU caches available on the platform. | |
83 | * Coherency between CPU and GPU accesses to the surface is not | |
84 | * guaranteed without extra synchronization. | |
85 | */ | |
86 | I915_MOCS_CACHED, | |
87 | }; | |
88 | ||
718dcedd DH |
89 | /* Each region is a minimum of 16k, and there are at most 255 of them. |
90 | */ | |
91 | #define I915_NR_TEX_REGIONS 255 /* table size 2k - maximum due to use | |
92 | * of chars for next/prev indices */ | |
93 | #define I915_LOG_MIN_TEX_REGION_SIZE 14 | |
94 | ||
95 | typedef struct _drm_i915_init { | |
96 | enum { | |
97 | I915_INIT_DMA = 0x01, | |
98 | I915_CLEANUP_DMA = 0x02, | |
99 | I915_RESUME_DMA = 0x03 | |
100 | } func; | |
101 | unsigned int mmio_offset; | |
102 | int sarea_priv_offset; | |
103 | unsigned int ring_start; | |
104 | unsigned int ring_end; | |
105 | unsigned int ring_size; | |
106 | unsigned int front_offset; | |
107 | unsigned int back_offset; | |
108 | unsigned int depth_offset; | |
109 | unsigned int w; | |
110 | unsigned int h; | |
111 | unsigned int pitch; | |
112 | unsigned int pitch_bits; | |
113 | unsigned int back_pitch; | |
114 | unsigned int depth_pitch; | |
115 | unsigned int cpp; | |
116 | unsigned int chipset; | |
117 | } drm_i915_init_t; | |
118 | ||
119 | typedef struct _drm_i915_sarea { | |
120 | struct drm_tex_region texList[I915_NR_TEX_REGIONS + 1]; | |
121 | int last_upload; /* last time texture was uploaded */ | |
122 | int last_enqueue; /* last time a buffer was enqueued */ | |
123 | int last_dispatch; /* age of the most recently dispatched buffer */ | |
124 | int ctxOwner; /* last context to upload state */ | |
125 | int texAge; | |
126 | int pf_enabled; /* is pageflipping allowed? */ | |
127 | int pf_active; | |
128 | int pf_current_page; /* which buffer is being displayed? */ | |
129 | int perf_boxes; /* performance boxes to be displayed */ | |
130 | int width, height; /* screen size in pixels */ | |
131 | ||
132 | drm_handle_t front_handle; | |
133 | int front_offset; | |
134 | int front_size; | |
135 | ||
136 | drm_handle_t back_handle; | |
137 | int back_offset; | |
138 | int back_size; | |
139 | ||
140 | drm_handle_t depth_handle; | |
141 | int depth_offset; | |
142 | int depth_size; | |
143 | ||
144 | drm_handle_t tex_handle; | |
145 | int tex_offset; | |
146 | int tex_size; | |
147 | int log_tex_granularity; | |
148 | int pitch; | |
149 | int rotation; /* 0, 90, 180 or 270 */ | |
150 | int rotated_offset; | |
151 | int rotated_size; | |
152 | int rotated_pitch; | |
153 | int virtualX, virtualY; | |
154 | ||
155 | unsigned int front_tiled; | |
156 | unsigned int back_tiled; | |
157 | unsigned int depth_tiled; | |
158 | unsigned int rotated_tiled; | |
159 | unsigned int rotated2_tiled; | |
160 | ||
161 | int pipeA_x; | |
162 | int pipeA_y; | |
163 | int pipeA_w; | |
164 | int pipeA_h; | |
165 | int pipeB_x; | |
166 | int pipeB_y; | |
167 | int pipeB_w; | |
168 | int pipeB_h; | |
169 | ||
170 | /* fill out some space for old userspace triple buffer */ | |
171 | drm_handle_t unused_handle; | |
172 | __u32 unused1, unused2, unused3; | |
173 | ||
174 | /* buffer object handles for static buffers. May change | |
175 | * over the lifetime of the client. | |
176 | */ | |
177 | __u32 front_bo_handle; | |
178 | __u32 back_bo_handle; | |
179 | __u32 unused_bo_handle; | |
180 | __u32 depth_bo_handle; | |
181 | ||
182 | } drm_i915_sarea_t; | |
183 | ||
184 | /* due to userspace building against these headers we need some compat here */ | |
185 | #define planeA_x pipeA_x | |
186 | #define planeA_y pipeA_y | |
187 | #define planeA_w pipeA_w | |
188 | #define planeA_h pipeA_h | |
189 | #define planeB_x pipeB_x | |
190 | #define planeB_y pipeB_y | |
191 | #define planeB_w pipeB_w | |
192 | #define planeB_h pipeB_h | |
193 | ||
194 | /* Flags for perf_boxes | |
195 | */ | |
196 | #define I915_BOX_RING_EMPTY 0x1 | |
197 | #define I915_BOX_FLIP 0x2 | |
198 | #define I915_BOX_WAIT 0x4 | |
199 | #define I915_BOX_TEXTURE_LOAD 0x8 | |
200 | #define I915_BOX_LOST_CONTEXT 0x10 | |
201 | ||
21631f10 DL |
202 | /* |
203 | * i915 specific ioctls. | |
204 | * | |
205 | * The device specific ioctl range is [DRM_COMMAND_BASE, DRM_COMMAND_END) ie | |
206 | * [0x40, 0xa0) (a0 is excluded). The numbers below are defined as offset | |
207 | * against DRM_COMMAND_BASE and should be between [0x0, 0x60). | |
718dcedd DH |
208 | */ |
209 | #define DRM_I915_INIT 0x00 | |
210 | #define DRM_I915_FLUSH 0x01 | |
211 | #define DRM_I915_FLIP 0x02 | |
212 | #define DRM_I915_BATCHBUFFER 0x03 | |
213 | #define DRM_I915_IRQ_EMIT 0x04 | |
214 | #define DRM_I915_IRQ_WAIT 0x05 | |
215 | #define DRM_I915_GETPARAM 0x06 | |
216 | #define DRM_I915_SETPARAM 0x07 | |
217 | #define DRM_I915_ALLOC 0x08 | |
218 | #define DRM_I915_FREE 0x09 | |
219 | #define DRM_I915_INIT_HEAP 0x0a | |
220 | #define DRM_I915_CMDBUFFER 0x0b | |
221 | #define DRM_I915_DESTROY_HEAP 0x0c | |
222 | #define DRM_I915_SET_VBLANK_PIPE 0x0d | |
223 | #define DRM_I915_GET_VBLANK_PIPE 0x0e | |
224 | #define DRM_I915_VBLANK_SWAP 0x0f | |
225 | #define DRM_I915_HWS_ADDR 0x11 | |
226 | #define DRM_I915_GEM_INIT 0x13 | |
227 | #define DRM_I915_GEM_EXECBUFFER 0x14 | |
228 | #define DRM_I915_GEM_PIN 0x15 | |
229 | #define DRM_I915_GEM_UNPIN 0x16 | |
230 | #define DRM_I915_GEM_BUSY 0x17 | |
231 | #define DRM_I915_GEM_THROTTLE 0x18 | |
232 | #define DRM_I915_GEM_ENTERVT 0x19 | |
233 | #define DRM_I915_GEM_LEAVEVT 0x1a | |
234 | #define DRM_I915_GEM_CREATE 0x1b | |
235 | #define DRM_I915_GEM_PREAD 0x1c | |
236 | #define DRM_I915_GEM_PWRITE 0x1d | |
237 | #define DRM_I915_GEM_MMAP 0x1e | |
238 | #define DRM_I915_GEM_SET_DOMAIN 0x1f | |
239 | #define DRM_I915_GEM_SW_FINISH 0x20 | |
240 | #define DRM_I915_GEM_SET_TILING 0x21 | |
241 | #define DRM_I915_GEM_GET_TILING 0x22 | |
242 | #define DRM_I915_GEM_GET_APERTURE 0x23 | |
243 | #define DRM_I915_GEM_MMAP_GTT 0x24 | |
244 | #define DRM_I915_GET_PIPE_FROM_CRTC_ID 0x25 | |
245 | #define DRM_I915_GEM_MADVISE 0x26 | |
246 | #define DRM_I915_OVERLAY_PUT_IMAGE 0x27 | |
247 | #define DRM_I915_OVERLAY_ATTRS 0x28 | |
248 | #define DRM_I915_GEM_EXECBUFFER2 0x29 | |
249 | #define DRM_I915_GET_SPRITE_COLORKEY 0x2a | |
250 | #define DRM_I915_SET_SPRITE_COLORKEY 0x2b | |
251 | #define DRM_I915_GEM_WAIT 0x2c | |
252 | #define DRM_I915_GEM_CONTEXT_CREATE 0x2d | |
253 | #define DRM_I915_GEM_CONTEXT_DESTROY 0x2e | |
254 | #define DRM_I915_GEM_SET_CACHING 0x2f | |
255 | #define DRM_I915_GEM_GET_CACHING 0x30 | |
256 | #define DRM_I915_REG_READ 0x31 | |
b6359918 | 257 | #define DRM_I915_GET_RESET_STATS 0x32 |
5cc9ed4b | 258 | #define DRM_I915_GEM_USERPTR 0x33 |
c9dc0f35 CW |
259 | #define DRM_I915_GEM_CONTEXT_GETPARAM 0x34 |
260 | #define DRM_I915_GEM_CONTEXT_SETPARAM 0x35 | |
eec688e1 | 261 | #define DRM_I915_PERF_OPEN 0x36 |
718dcedd DH |
262 | |
263 | #define DRM_IOCTL_I915_INIT DRM_IOW( DRM_COMMAND_BASE + DRM_I915_INIT, drm_i915_init_t) | |
264 | #define DRM_IOCTL_I915_FLUSH DRM_IO ( DRM_COMMAND_BASE + DRM_I915_FLUSH) | |
265 | #define DRM_IOCTL_I915_FLIP DRM_IO ( DRM_COMMAND_BASE + DRM_I915_FLIP) | |
266 | #define DRM_IOCTL_I915_BATCHBUFFER DRM_IOW( DRM_COMMAND_BASE + DRM_I915_BATCHBUFFER, drm_i915_batchbuffer_t) | |
267 | #define DRM_IOCTL_I915_IRQ_EMIT DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_IRQ_EMIT, drm_i915_irq_emit_t) | |
268 | #define DRM_IOCTL_I915_IRQ_WAIT DRM_IOW( DRM_COMMAND_BASE + DRM_I915_IRQ_WAIT, drm_i915_irq_wait_t) | |
269 | #define DRM_IOCTL_I915_GETPARAM DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GETPARAM, drm_i915_getparam_t) | |
270 | #define DRM_IOCTL_I915_SETPARAM DRM_IOW( DRM_COMMAND_BASE + DRM_I915_SETPARAM, drm_i915_setparam_t) | |
271 | #define DRM_IOCTL_I915_ALLOC DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_ALLOC, drm_i915_mem_alloc_t) | |
272 | #define DRM_IOCTL_I915_FREE DRM_IOW( DRM_COMMAND_BASE + DRM_I915_FREE, drm_i915_mem_free_t) | |
273 | #define DRM_IOCTL_I915_INIT_HEAP DRM_IOW( DRM_COMMAND_BASE + DRM_I915_INIT_HEAP, drm_i915_mem_init_heap_t) | |
274 | #define DRM_IOCTL_I915_CMDBUFFER DRM_IOW( DRM_COMMAND_BASE + DRM_I915_CMDBUFFER, drm_i915_cmdbuffer_t) | |
275 | #define DRM_IOCTL_I915_DESTROY_HEAP DRM_IOW( DRM_COMMAND_BASE + DRM_I915_DESTROY_HEAP, drm_i915_mem_destroy_heap_t) | |
276 | #define DRM_IOCTL_I915_SET_VBLANK_PIPE DRM_IOW( DRM_COMMAND_BASE + DRM_I915_SET_VBLANK_PIPE, drm_i915_vblank_pipe_t) | |
277 | #define DRM_IOCTL_I915_GET_VBLANK_PIPE DRM_IOR( DRM_COMMAND_BASE + DRM_I915_GET_VBLANK_PIPE, drm_i915_vblank_pipe_t) | |
278 | #define DRM_IOCTL_I915_VBLANK_SWAP DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_VBLANK_SWAP, drm_i915_vblank_swap_t) | |
279 | #define DRM_IOCTL_I915_HWS_ADDR DRM_IOW(DRM_COMMAND_BASE + DRM_I915_HWS_ADDR, struct drm_i915_gem_init) | |
280 | #define DRM_IOCTL_I915_GEM_INIT DRM_IOW(DRM_COMMAND_BASE + DRM_I915_GEM_INIT, struct drm_i915_gem_init) | |
281 | #define DRM_IOCTL_I915_GEM_EXECBUFFER DRM_IOW(DRM_COMMAND_BASE + DRM_I915_GEM_EXECBUFFER, struct drm_i915_gem_execbuffer) | |
282 | #define DRM_IOCTL_I915_GEM_EXECBUFFER2 DRM_IOW(DRM_COMMAND_BASE + DRM_I915_GEM_EXECBUFFER2, struct drm_i915_gem_execbuffer2) | |
283 | #define DRM_IOCTL_I915_GEM_PIN DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_PIN, struct drm_i915_gem_pin) | |
284 | #define DRM_IOCTL_I915_GEM_UNPIN DRM_IOW(DRM_COMMAND_BASE + DRM_I915_GEM_UNPIN, struct drm_i915_gem_unpin) | |
285 | #define DRM_IOCTL_I915_GEM_BUSY DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_BUSY, struct drm_i915_gem_busy) | |
286 | #define DRM_IOCTL_I915_GEM_SET_CACHING DRM_IOW(DRM_COMMAND_BASE + DRM_I915_GEM_SET_CACHING, struct drm_i915_gem_caching) | |
287 | #define DRM_IOCTL_I915_GEM_GET_CACHING DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_GET_CACHING, struct drm_i915_gem_caching) | |
288 | #define DRM_IOCTL_I915_GEM_THROTTLE DRM_IO ( DRM_COMMAND_BASE + DRM_I915_GEM_THROTTLE) | |
289 | #define DRM_IOCTL_I915_GEM_ENTERVT DRM_IO(DRM_COMMAND_BASE + DRM_I915_GEM_ENTERVT) | |
290 | #define DRM_IOCTL_I915_GEM_LEAVEVT DRM_IO(DRM_COMMAND_BASE + DRM_I915_GEM_LEAVEVT) | |
291 | #define DRM_IOCTL_I915_GEM_CREATE DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_CREATE, struct drm_i915_gem_create) | |
292 | #define DRM_IOCTL_I915_GEM_PREAD DRM_IOW (DRM_COMMAND_BASE + DRM_I915_GEM_PREAD, struct drm_i915_gem_pread) | |
293 | #define DRM_IOCTL_I915_GEM_PWRITE DRM_IOW (DRM_COMMAND_BASE + DRM_I915_GEM_PWRITE, struct drm_i915_gem_pwrite) | |
294 | #define DRM_IOCTL_I915_GEM_MMAP DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_MMAP, struct drm_i915_gem_mmap) | |
295 | #define DRM_IOCTL_I915_GEM_MMAP_GTT DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_MMAP_GTT, struct drm_i915_gem_mmap_gtt) | |
296 | #define DRM_IOCTL_I915_GEM_SET_DOMAIN DRM_IOW (DRM_COMMAND_BASE + DRM_I915_GEM_SET_DOMAIN, struct drm_i915_gem_set_domain) | |
297 | #define DRM_IOCTL_I915_GEM_SW_FINISH DRM_IOW (DRM_COMMAND_BASE + DRM_I915_GEM_SW_FINISH, struct drm_i915_gem_sw_finish) | |
298 | #define DRM_IOCTL_I915_GEM_SET_TILING DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_GEM_SET_TILING, struct drm_i915_gem_set_tiling) | |
299 | #define DRM_IOCTL_I915_GEM_GET_TILING DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_GEM_GET_TILING, struct drm_i915_gem_get_tiling) | |
300 | #define DRM_IOCTL_I915_GEM_GET_APERTURE DRM_IOR (DRM_COMMAND_BASE + DRM_I915_GEM_GET_APERTURE, struct drm_i915_gem_get_aperture) | |
301 | #define DRM_IOCTL_I915_GET_PIPE_FROM_CRTC_ID DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GET_PIPE_FROM_CRTC_ID, struct drm_i915_get_pipe_from_crtc_id) | |
302 | #define DRM_IOCTL_I915_GEM_MADVISE DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_MADVISE, struct drm_i915_gem_madvise) | |
303 | #define DRM_IOCTL_I915_OVERLAY_PUT_IMAGE DRM_IOW(DRM_COMMAND_BASE + DRM_I915_OVERLAY_PUT_IMAGE, struct drm_intel_overlay_put_image) | |
304 | #define DRM_IOCTL_I915_OVERLAY_ATTRS DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_OVERLAY_ATTRS, struct drm_intel_overlay_attrs) | |
305 | #define DRM_IOCTL_I915_SET_SPRITE_COLORKEY DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_SET_SPRITE_COLORKEY, struct drm_intel_sprite_colorkey) | |
2c60fae1 | 306 | #define DRM_IOCTL_I915_GET_SPRITE_COLORKEY DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GET_SPRITE_COLORKEY, struct drm_intel_sprite_colorkey) |
718dcedd DH |
307 | #define DRM_IOCTL_I915_GEM_WAIT DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_WAIT, struct drm_i915_gem_wait) |
308 | #define DRM_IOCTL_I915_GEM_CONTEXT_CREATE DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_GEM_CONTEXT_CREATE, struct drm_i915_gem_context_create) | |
309 | #define DRM_IOCTL_I915_GEM_CONTEXT_DESTROY DRM_IOW (DRM_COMMAND_BASE + DRM_I915_GEM_CONTEXT_DESTROY, struct drm_i915_gem_context_destroy) | |
310 | #define DRM_IOCTL_I915_REG_READ DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_REG_READ, struct drm_i915_reg_read) | |
b6359918 | 311 | #define DRM_IOCTL_I915_GET_RESET_STATS DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_GET_RESET_STATS, struct drm_i915_reset_stats) |
5cc9ed4b | 312 | #define DRM_IOCTL_I915_GEM_USERPTR DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_GEM_USERPTR, struct drm_i915_gem_userptr) |
c9dc0f35 CW |
313 | #define DRM_IOCTL_I915_GEM_CONTEXT_GETPARAM DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_GEM_CONTEXT_GETPARAM, struct drm_i915_gem_context_param) |
314 | #define DRM_IOCTL_I915_GEM_CONTEXT_SETPARAM DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_GEM_CONTEXT_SETPARAM, struct drm_i915_gem_context_param) | |
eec688e1 | 315 | #define DRM_IOCTL_I915_PERF_OPEN DRM_IOW(DRM_COMMAND_BASE + DRM_I915_PERF_OPEN, struct drm_i915_perf_open_param) |
718dcedd DH |
316 | |
317 | /* Allow drivers to submit batchbuffers directly to hardware, relying | |
318 | * on the security mechanisms provided by hardware. | |
319 | */ | |
320 | typedef struct drm_i915_batchbuffer { | |
321 | int start; /* agp offset */ | |
322 | int used; /* nr bytes in use */ | |
323 | int DR1; /* hw flags for GFX_OP_DRAWRECT_INFO */ | |
324 | int DR4; /* window origin for GFX_OP_DRAWRECT_INFO */ | |
325 | int num_cliprects; /* mulitpass with multiple cliprects? */ | |
326 | struct drm_clip_rect __user *cliprects; /* pointer to userspace cliprects */ | |
327 | } drm_i915_batchbuffer_t; | |
328 | ||
329 | /* As above, but pass a pointer to userspace buffer which can be | |
330 | * validated by the kernel prior to sending to hardware. | |
331 | */ | |
332 | typedef struct _drm_i915_cmdbuffer { | |
333 | char __user *buf; /* pointer to userspace command buffer */ | |
334 | int sz; /* nr bytes in buf */ | |
335 | int DR1; /* hw flags for GFX_OP_DRAWRECT_INFO */ | |
336 | int DR4; /* window origin for GFX_OP_DRAWRECT_INFO */ | |
337 | int num_cliprects; /* mulitpass with multiple cliprects? */ | |
338 | struct drm_clip_rect __user *cliprects; /* pointer to userspace cliprects */ | |
339 | } drm_i915_cmdbuffer_t; | |
340 | ||
341 | /* Userspace can request & wait on irq's: | |
342 | */ | |
343 | typedef struct drm_i915_irq_emit { | |
344 | int __user *irq_seq; | |
345 | } drm_i915_irq_emit_t; | |
346 | ||
347 | typedef struct drm_i915_irq_wait { | |
348 | int irq_seq; | |
349 | } drm_i915_irq_wait_t; | |
350 | ||
351 | /* Ioctl to query kernel params: | |
352 | */ | |
353 | #define I915_PARAM_IRQ_ACTIVE 1 | |
354 | #define I915_PARAM_ALLOW_BATCHBUFFER 2 | |
355 | #define I915_PARAM_LAST_DISPATCH 3 | |
356 | #define I915_PARAM_CHIPSET_ID 4 | |
357 | #define I915_PARAM_HAS_GEM 5 | |
358 | #define I915_PARAM_NUM_FENCES_AVAIL 6 | |
359 | #define I915_PARAM_HAS_OVERLAY 7 | |
360 | #define I915_PARAM_HAS_PAGEFLIPPING 8 | |
361 | #define I915_PARAM_HAS_EXECBUF2 9 | |
362 | #define I915_PARAM_HAS_BSD 10 | |
363 | #define I915_PARAM_HAS_BLT 11 | |
364 | #define I915_PARAM_HAS_RELAXED_FENCING 12 | |
365 | #define I915_PARAM_HAS_COHERENT_RINGS 13 | |
366 | #define I915_PARAM_HAS_EXEC_CONSTANTS 14 | |
367 | #define I915_PARAM_HAS_RELAXED_DELTA 15 | |
368 | #define I915_PARAM_HAS_GEN7_SOL_RESET 16 | |
369 | #define I915_PARAM_HAS_LLC 17 | |
370 | #define I915_PARAM_HAS_ALIASING_PPGTT 18 | |
371 | #define I915_PARAM_HAS_WAIT_TIMEOUT 19 | |
372 | #define I915_PARAM_HAS_SEMAPHORES 20 | |
373 | #define I915_PARAM_HAS_PRIME_VMAP_FLUSH 21 | |
a1f2cc73 | 374 | #define I915_PARAM_HAS_VEBOX 22 |
c2fb7916 | 375 | #define I915_PARAM_HAS_SECURE_BATCHES 23 |
b45305fc | 376 | #define I915_PARAM_HAS_PINNED_BATCHES 24 |
ed5982e6 | 377 | #define I915_PARAM_HAS_EXEC_NO_RELOC 25 |
eef90ccb | 378 | #define I915_PARAM_HAS_EXEC_HANDLE_LUT 26 |
651d794f | 379 | #define I915_PARAM_HAS_WT 27 |
d728c8ef | 380 | #define I915_PARAM_CMD_PARSER_VERSION 28 |
6a2c4232 | 381 | #define I915_PARAM_HAS_COHERENT_PHYS_GTT 29 |
1816f923 | 382 | #define I915_PARAM_MMAP_VERSION 30 |
08e16dc8 | 383 | #define I915_PARAM_HAS_BSD2 31 |
27cd4461 | 384 | #define I915_PARAM_REVISION 32 |
a1559ffe JM |
385 | #define I915_PARAM_SUBSLICE_TOTAL 33 |
386 | #define I915_PARAM_EU_TOTAL 34 | |
49e4d842 | 387 | #define I915_PARAM_HAS_GPU_RESET 35 |
a9ed33ca | 388 | #define I915_PARAM_HAS_RESOURCE_STREAMER 36 |
506a8e87 | 389 | #define I915_PARAM_HAS_EXEC_SOFTPIN 37 |
37f501af | 390 | #define I915_PARAM_HAS_POOLED_EU 38 |
391 | #define I915_PARAM_MIN_EU_IN_POOL 39 | |
4cc69075 | 392 | #define I915_PARAM_MMAP_GTT_VERSION 40 |
718dcedd | 393 | |
0de9136d CW |
394 | /* Query whether DRM_I915_GEM_EXECBUFFER2 supports user defined execution |
395 | * priorities and the driver will attempt to execute batches in priority order. | |
396 | */ | |
397 | #define I915_PARAM_HAS_SCHEDULER 41 | |
5464cd65 | 398 | #define I915_PARAM_HUC_STATUS 42 |
0de9136d | 399 | |
718dcedd | 400 | typedef struct drm_i915_getparam { |
16f7249d | 401 | __s32 param; |
346add78 DV |
402 | /* |
403 | * WARNING: Using pointers instead of fixed-size u64 means we need to write | |
404 | * compat32 code. Don't repeat this mistake. | |
405 | */ | |
718dcedd DH |
406 | int __user *value; |
407 | } drm_i915_getparam_t; | |
408 | ||
409 | /* Ioctl to set kernel params: | |
410 | */ | |
411 | #define I915_SETPARAM_USE_MI_BATCHBUFFER_START 1 | |
412 | #define I915_SETPARAM_TEX_LRU_LOG_GRANULARITY 2 | |
413 | #define I915_SETPARAM_ALLOW_BATCHBUFFER 3 | |
414 | #define I915_SETPARAM_NUM_USED_FENCES 4 | |
415 | ||
416 | typedef struct drm_i915_setparam { | |
417 | int param; | |
418 | int value; | |
419 | } drm_i915_setparam_t; | |
420 | ||
421 | /* A memory manager for regions of shared memory: | |
422 | */ | |
423 | #define I915_MEM_REGION_AGP 1 | |
424 | ||
425 | typedef struct drm_i915_mem_alloc { | |
426 | int region; | |
427 | int alignment; | |
428 | int size; | |
429 | int __user *region_offset; /* offset from start of fb or agp */ | |
430 | } drm_i915_mem_alloc_t; | |
431 | ||
432 | typedef struct drm_i915_mem_free { | |
433 | int region; | |
434 | int region_offset; | |
435 | } drm_i915_mem_free_t; | |
436 | ||
437 | typedef struct drm_i915_mem_init_heap { | |
438 | int region; | |
439 | int size; | |
440 | int start; | |
441 | } drm_i915_mem_init_heap_t; | |
442 | ||
443 | /* Allow memory manager to be torn down and re-initialized (eg on | |
444 | * rotate): | |
445 | */ | |
446 | typedef struct drm_i915_mem_destroy_heap { | |
447 | int region; | |
448 | } drm_i915_mem_destroy_heap_t; | |
449 | ||
450 | /* Allow X server to configure which pipes to monitor for vblank signals | |
451 | */ | |
452 | #define DRM_I915_VBLANK_PIPE_A 1 | |
453 | #define DRM_I915_VBLANK_PIPE_B 2 | |
454 | ||
455 | typedef struct drm_i915_vblank_pipe { | |
456 | int pipe; | |
457 | } drm_i915_vblank_pipe_t; | |
458 | ||
459 | /* Schedule buffer swap at given vertical blank: | |
460 | */ | |
461 | typedef struct drm_i915_vblank_swap { | |
462 | drm_drawable_t drawable; | |
463 | enum drm_vblank_seq_type seqtype; | |
464 | unsigned int sequence; | |
465 | } drm_i915_vblank_swap_t; | |
466 | ||
467 | typedef struct drm_i915_hws_addr { | |
468 | __u64 addr; | |
469 | } drm_i915_hws_addr_t; | |
470 | ||
471 | struct drm_i915_gem_init { | |
472 | /** | |
473 | * Beginning offset in the GTT to be managed by the DRM memory | |
474 | * manager. | |
475 | */ | |
476 | __u64 gtt_start; | |
477 | /** | |
478 | * Ending offset in the GTT to be managed by the DRM memory | |
479 | * manager. | |
480 | */ | |
481 | __u64 gtt_end; | |
482 | }; | |
483 | ||
484 | struct drm_i915_gem_create { | |
485 | /** | |
486 | * Requested size for the object. | |
487 | * | |
488 | * The (page-aligned) allocated size for the object will be returned. | |
489 | */ | |
490 | __u64 size; | |
491 | /** | |
492 | * Returned handle for the object. | |
493 | * | |
494 | * Object handles are nonzero. | |
495 | */ | |
496 | __u32 handle; | |
497 | __u32 pad; | |
498 | }; | |
499 | ||
500 | struct drm_i915_gem_pread { | |
501 | /** Handle for the object being read. */ | |
502 | __u32 handle; | |
503 | __u32 pad; | |
504 | /** Offset into the object to read from */ | |
505 | __u64 offset; | |
506 | /** Length of data to read */ | |
507 | __u64 size; | |
508 | /** | |
509 | * Pointer to write the data into. | |
510 | * | |
511 | * This is a fixed-size type for 32/64 compatibility. | |
512 | */ | |
513 | __u64 data_ptr; | |
514 | }; | |
515 | ||
516 | struct drm_i915_gem_pwrite { | |
517 | /** Handle for the object being written to. */ | |
518 | __u32 handle; | |
519 | __u32 pad; | |
520 | /** Offset into the object to write to */ | |
521 | __u64 offset; | |
522 | /** Length of data to write */ | |
523 | __u64 size; | |
524 | /** | |
525 | * Pointer to read the data from. | |
526 | * | |
527 | * This is a fixed-size type for 32/64 compatibility. | |
528 | */ | |
529 | __u64 data_ptr; | |
530 | }; | |
531 | ||
532 | struct drm_i915_gem_mmap { | |
533 | /** Handle for the object being mapped. */ | |
534 | __u32 handle; | |
535 | __u32 pad; | |
536 | /** Offset in the object to map. */ | |
537 | __u64 offset; | |
538 | /** | |
539 | * Length of data to map. | |
540 | * | |
541 | * The value will be page-aligned. | |
542 | */ | |
543 | __u64 size; | |
544 | /** | |
545 | * Returned pointer the data was mapped at. | |
546 | * | |
547 | * This is a fixed-size type for 32/64 compatibility. | |
548 | */ | |
549 | __u64 addr_ptr; | |
1816f923 AG |
550 | |
551 | /** | |
552 | * Flags for extended behaviour. | |
553 | * | |
554 | * Added in version 2. | |
555 | */ | |
556 | __u64 flags; | |
557 | #define I915_MMAP_WC 0x1 | |
718dcedd DH |
558 | }; |
559 | ||
560 | struct drm_i915_gem_mmap_gtt { | |
561 | /** Handle for the object being mapped. */ | |
562 | __u32 handle; | |
563 | __u32 pad; | |
564 | /** | |
565 | * Fake offset to use for subsequent mmap call | |
566 | * | |
567 | * This is a fixed-size type for 32/64 compatibility. | |
568 | */ | |
569 | __u64 offset; | |
570 | }; | |
571 | ||
572 | struct drm_i915_gem_set_domain { | |
573 | /** Handle for the object */ | |
574 | __u32 handle; | |
575 | ||
576 | /** New read domains */ | |
577 | __u32 read_domains; | |
578 | ||
579 | /** New write domain */ | |
580 | __u32 write_domain; | |
581 | }; | |
582 | ||
583 | struct drm_i915_gem_sw_finish { | |
584 | /** Handle for the object */ | |
585 | __u32 handle; | |
586 | }; | |
587 | ||
588 | struct drm_i915_gem_relocation_entry { | |
589 | /** | |
590 | * Handle of the buffer being pointed to by this relocation entry. | |
591 | * | |
592 | * It's appealing to make this be an index into the mm_validate_entry | |
593 | * list to refer to the buffer, but this allows the driver to create | |
594 | * a relocation list for state buffers and not re-write it per | |
595 | * exec using the buffer. | |
596 | */ | |
597 | __u32 target_handle; | |
598 | ||
599 | /** | |
600 | * Value to be added to the offset of the target buffer to make up | |
601 | * the relocation entry. | |
602 | */ | |
603 | __u32 delta; | |
604 | ||
605 | /** Offset in the buffer the relocation entry will be written into */ | |
606 | __u64 offset; | |
607 | ||
608 | /** | |
609 | * Offset value of the target buffer that the relocation entry was last | |
610 | * written as. | |
611 | * | |
612 | * If the buffer has the same offset as last time, we can skip syncing | |
613 | * and writing the relocation. This value is written back out by | |
614 | * the execbuffer ioctl when the relocation is written. | |
615 | */ | |
616 | __u64 presumed_offset; | |
617 | ||
618 | /** | |
619 | * Target memory domains read by this operation. | |
620 | */ | |
621 | __u32 read_domains; | |
622 | ||
623 | /** | |
624 | * Target memory domains written by this operation. | |
625 | * | |
626 | * Note that only one domain may be written by the whole | |
627 | * execbuffer operation, so that where there are conflicts, | |
628 | * the application will get -EINVAL back. | |
629 | */ | |
630 | __u32 write_domain; | |
631 | }; | |
632 | ||
633 | /** @{ | |
634 | * Intel memory domains | |
635 | * | |
636 | * Most of these just align with the various caches in | |
637 | * the system and are used to flush and invalidate as | |
638 | * objects end up cached in different domains. | |
639 | */ | |
640 | /** CPU cache */ | |
641 | #define I915_GEM_DOMAIN_CPU 0x00000001 | |
642 | /** Render cache, used by 2D and 3D drawing */ | |
643 | #define I915_GEM_DOMAIN_RENDER 0x00000002 | |
644 | /** Sampler cache, used by texture engine */ | |
645 | #define I915_GEM_DOMAIN_SAMPLER 0x00000004 | |
646 | /** Command queue, used to load batch buffers */ | |
647 | #define I915_GEM_DOMAIN_COMMAND 0x00000008 | |
648 | /** Instruction cache, used by shader programs */ | |
649 | #define I915_GEM_DOMAIN_INSTRUCTION 0x00000010 | |
650 | /** Vertex address cache */ | |
651 | #define I915_GEM_DOMAIN_VERTEX 0x00000020 | |
652 | /** GTT domain - aperture and scanout */ | |
653 | #define I915_GEM_DOMAIN_GTT 0x00000040 | |
654 | /** @} */ | |
655 | ||
656 | struct drm_i915_gem_exec_object { | |
657 | /** | |
658 | * User's handle for a buffer to be bound into the GTT for this | |
659 | * operation. | |
660 | */ | |
661 | __u32 handle; | |
662 | ||
663 | /** Number of relocations to be performed on this buffer */ | |
664 | __u32 relocation_count; | |
665 | /** | |
666 | * Pointer to array of struct drm_i915_gem_relocation_entry containing | |
667 | * the relocations to be performed in this buffer. | |
668 | */ | |
669 | __u64 relocs_ptr; | |
670 | ||
671 | /** Required alignment in graphics aperture */ | |
672 | __u64 alignment; | |
673 | ||
674 | /** | |
675 | * Returned value of the updated offset of the object, for future | |
676 | * presumed_offset writes. | |
677 | */ | |
678 | __u64 offset; | |
679 | }; | |
680 | ||
681 | struct drm_i915_gem_execbuffer { | |
682 | /** | |
683 | * List of buffers to be validated with their relocations to be | |
684 | * performend on them. | |
685 | * | |
686 | * This is a pointer to an array of struct drm_i915_gem_validate_entry. | |
687 | * | |
688 | * These buffers must be listed in an order such that all relocations | |
689 | * a buffer is performing refer to buffers that have already appeared | |
690 | * in the validate list. | |
691 | */ | |
692 | __u64 buffers_ptr; | |
693 | __u32 buffer_count; | |
694 | ||
695 | /** Offset in the batchbuffer to start execution from. */ | |
696 | __u32 batch_start_offset; | |
697 | /** Bytes used in batchbuffer from batch_start_offset */ | |
698 | __u32 batch_len; | |
699 | __u32 DR1; | |
700 | __u32 DR4; | |
701 | __u32 num_cliprects; | |
702 | /** This is a struct drm_clip_rect *cliprects */ | |
703 | __u64 cliprects_ptr; | |
704 | }; | |
705 | ||
706 | struct drm_i915_gem_exec_object2 { | |
707 | /** | |
708 | * User's handle for a buffer to be bound into the GTT for this | |
709 | * operation. | |
710 | */ | |
711 | __u32 handle; | |
712 | ||
713 | /** Number of relocations to be performed on this buffer */ | |
714 | __u32 relocation_count; | |
715 | /** | |
716 | * Pointer to array of struct drm_i915_gem_relocation_entry containing | |
717 | * the relocations to be performed in this buffer. | |
718 | */ | |
719 | __u64 relocs_ptr; | |
720 | ||
721 | /** Required alignment in graphics aperture */ | |
722 | __u64 alignment; | |
723 | ||
724 | /** | |
506a8e87 CW |
725 | * When the EXEC_OBJECT_PINNED flag is specified this is populated by |
726 | * the user with the GTT offset at which this object will be pinned. | |
727 | * When the I915_EXEC_NO_RELOC flag is specified this must contain the | |
728 | * presumed_offset of the object. | |
729 | * During execbuffer2 the kernel populates it with the value of the | |
730 | * current GTT offset of the object, for future presumed_offset writes. | |
718dcedd DH |
731 | */ |
732 | __u64 offset; | |
733 | ||
9e2793f6 DG |
734 | #define EXEC_OBJECT_NEEDS_FENCE (1<<0) |
735 | #define EXEC_OBJECT_NEEDS_GTT (1<<1) | |
736 | #define EXEC_OBJECT_WRITE (1<<2) | |
101b506a | 737 | #define EXEC_OBJECT_SUPPORTS_48B_ADDRESS (1<<3) |
9e2793f6 | 738 | #define EXEC_OBJECT_PINNED (1<<4) |
91b2db6f | 739 | #define EXEC_OBJECT_PAD_TO_SIZE (1<<5) |
9e2793f6 | 740 | /* All remaining bits are MBZ and RESERVED FOR FUTURE USE */ |
91b2db6f | 741 | #define __EXEC_OBJECT_UNKNOWN_FLAGS -(EXEC_OBJECT_PAD_TO_SIZE<<1) |
718dcedd | 742 | __u64 flags; |
ed5982e6 | 743 | |
91b2db6f CW |
744 | union { |
745 | __u64 rsvd1; | |
746 | __u64 pad_to_size; | |
747 | }; | |
718dcedd DH |
748 | __u64 rsvd2; |
749 | }; | |
750 | ||
751 | struct drm_i915_gem_execbuffer2 { | |
752 | /** | |
753 | * List of gem_exec_object2 structs | |
754 | */ | |
755 | __u64 buffers_ptr; | |
756 | __u32 buffer_count; | |
757 | ||
758 | /** Offset in the batchbuffer to start execution from. */ | |
759 | __u32 batch_start_offset; | |
760 | /** Bytes used in batchbuffer from batch_start_offset */ | |
761 | __u32 batch_len; | |
762 | __u32 DR1; | |
763 | __u32 DR4; | |
764 | __u32 num_cliprects; | |
765 | /** This is a struct drm_clip_rect *cliprects */ | |
766 | __u64 cliprects_ptr; | |
767 | #define I915_EXEC_RING_MASK (7<<0) | |
768 | #define I915_EXEC_DEFAULT (0<<0) | |
769 | #define I915_EXEC_RENDER (1<<0) | |
770 | #define I915_EXEC_BSD (2<<0) | |
771 | #define I915_EXEC_BLT (3<<0) | |
82f91b6e | 772 | #define I915_EXEC_VEBOX (4<<0) |
718dcedd DH |
773 | |
774 | /* Used for switching the constants addressing mode on gen4+ RENDER ring. | |
775 | * Gen6+ only supports relative addressing to dynamic state (default) and | |
776 | * absolute addressing. | |
777 | * | |
778 | * These flags are ignored for the BSD and BLT rings. | |
779 | */ | |
780 | #define I915_EXEC_CONSTANTS_MASK (3<<6) | |
781 | #define I915_EXEC_CONSTANTS_REL_GENERAL (0<<6) /* default */ | |
782 | #define I915_EXEC_CONSTANTS_ABSOLUTE (1<<6) | |
783 | #define I915_EXEC_CONSTANTS_REL_SURFACE (2<<6) /* gen4/5 only */ | |
784 | __u64 flags; | |
785 | __u64 rsvd1; /* now used for context info */ | |
786 | __u64 rsvd2; | |
787 | }; | |
788 | ||
789 | /** Resets the SO write offset registers for transform feedback on gen7. */ | |
790 | #define I915_EXEC_GEN7_SOL_RESET (1<<8) | |
791 | ||
c2fb7916 DV |
792 | /** Request a privileged ("secure") batch buffer. Note only available for |
793 | * DRM_ROOT_ONLY | DRM_MASTER processes. | |
794 | */ | |
795 | #define I915_EXEC_SECURE (1<<9) | |
796 | ||
b45305fc DV |
797 | /** Inform the kernel that the batch is and will always be pinned. This |
798 | * negates the requirement for a workaround to be performed to avoid | |
799 | * an incoherent CS (such as can be found on 830/845). If this flag is | |
800 | * not passed, the kernel will endeavour to make sure the batch is | |
801 | * coherent with the CS before execution. If this flag is passed, | |
802 | * userspace assumes the responsibility for ensuring the same. | |
803 | */ | |
804 | #define I915_EXEC_IS_PINNED (1<<10) | |
805 | ||
c3d19d3c | 806 | /** Provide a hint to the kernel that the command stream and auxiliary |
ed5982e6 DV |
807 | * state buffers already holds the correct presumed addresses and so the |
808 | * relocation process may be skipped if no buffers need to be moved in | |
809 | * preparation for the execbuffer. | |
810 | */ | |
811 | #define I915_EXEC_NO_RELOC (1<<11) | |
812 | ||
eef90ccb CW |
813 | /** Use the reloc.handle as an index into the exec object array rather |
814 | * than as the per-file handle. | |
815 | */ | |
816 | #define I915_EXEC_HANDLE_LUT (1<<12) | |
817 | ||
8d360dff | 818 | /** Used for switching BSD rings on the platforms with two BSD rings */ |
d9da6aa0 TU |
819 | #define I915_EXEC_BSD_SHIFT (13) |
820 | #define I915_EXEC_BSD_MASK (3 << I915_EXEC_BSD_SHIFT) | |
821 | /* default ping-pong mode */ | |
822 | #define I915_EXEC_BSD_DEFAULT (0 << I915_EXEC_BSD_SHIFT) | |
823 | #define I915_EXEC_BSD_RING1 (1 << I915_EXEC_BSD_SHIFT) | |
824 | #define I915_EXEC_BSD_RING2 (2 << I915_EXEC_BSD_SHIFT) | |
8d360dff | 825 | |
a9ed33ca AJ |
826 | /** Tell the kernel that the batchbuffer is processed by |
827 | * the resource streamer. | |
828 | */ | |
829 | #define I915_EXEC_RESOURCE_STREAMER (1<<15) | |
830 | ||
831 | #define __I915_EXEC_UNKNOWN_FLAGS -(I915_EXEC_RESOURCE_STREAMER<<1) | |
ed5982e6 | 832 | |
718dcedd DH |
833 | #define I915_EXEC_CONTEXT_ID_MASK (0xffffffff) |
834 | #define i915_execbuffer2_set_context_id(eb2, context) \ | |
835 | (eb2).rsvd1 = context & I915_EXEC_CONTEXT_ID_MASK | |
836 | #define i915_execbuffer2_get_context_id(eb2) \ | |
837 | ((eb2).rsvd1 & I915_EXEC_CONTEXT_ID_MASK) | |
838 | ||
839 | struct drm_i915_gem_pin { | |
840 | /** Handle of the buffer to be pinned. */ | |
841 | __u32 handle; | |
842 | __u32 pad; | |
843 | ||
844 | /** alignment required within the aperture */ | |
845 | __u64 alignment; | |
846 | ||
847 | /** Returned GTT offset of the buffer. */ | |
848 | __u64 offset; | |
849 | }; | |
850 | ||
851 | struct drm_i915_gem_unpin { | |
852 | /** Handle of the buffer to be unpinned. */ | |
853 | __u32 handle; | |
854 | __u32 pad; | |
855 | }; | |
856 | ||
857 | struct drm_i915_gem_busy { | |
858 | /** Handle of the buffer to check for busy */ | |
859 | __u32 handle; | |
860 | ||
426960be CW |
861 | /** Return busy status |
862 | * | |
863 | * A return of 0 implies that the object is idle (after | |
864 | * having flushed any pending activity), and a non-zero return that | |
865 | * the object is still in-flight on the GPU. (The GPU has not yet | |
866 | * signaled completion for all pending requests that reference the | |
1255501d CW |
867 | * object.) An object is guaranteed to become idle eventually (so |
868 | * long as no new GPU commands are executed upon it). Due to the | |
869 | * asynchronous nature of the hardware, an object reported | |
870 | * as busy may become idle before the ioctl is completed. | |
871 | * | |
872 | * Furthermore, if the object is busy, which engine is busy is only | |
873 | * provided as a guide. There are race conditions which prevent the | |
874 | * report of which engines are busy from being always accurate. | |
875 | * However, the converse is not true. If the object is idle, the | |
876 | * result of the ioctl, that all engines are idle, is accurate. | |
426960be CW |
877 | * |
878 | * The returned dword is split into two fields to indicate both | |
879 | * the engines on which the object is being read, and the | |
880 | * engine on which it is currently being written (if any). | |
881 | * | |
882 | * The low word (bits 0:15) indicate if the object is being written | |
883 | * to by any engine (there can only be one, as the GEM implicit | |
884 | * synchronisation rules force writes to be serialised). Only the | |
885 | * engine for the last write is reported. | |
886 | * | |
887 | * The high word (bits 16:31) are a bitmask of which engines are | |
888 | * currently reading from the object. Multiple engines may be | |
889 | * reading from the object simultaneously. | |
890 | * | |
891 | * The value of each engine is the same as specified in the | |
892 | * EXECBUFFER2 ioctl, i.e. I915_EXEC_RENDER, I915_EXEC_BSD etc. | |
893 | * Note I915_EXEC_DEFAULT is a symbolic value and is mapped to | |
894 | * the I915_EXEC_RENDER engine for execution, and so it is never | |
895 | * reported as active itself. Some hardware may have parallel | |
896 | * execution engines, e.g. multiple media engines, which are | |
897 | * mapped to the same identifier in the EXECBUFFER2 ioctl and | |
898 | * so are not separately reported for busyness. | |
1255501d CW |
899 | * |
900 | * Caveat emptor: | |
901 | * Only the boolean result of this query is reliable; that is whether | |
902 | * the object is idle or busy. The report of which engines are busy | |
903 | * should be only used as a heuristic. | |
718dcedd DH |
904 | */ |
905 | __u32 busy; | |
906 | }; | |
907 | ||
35c7ab42 DV |
908 | /** |
909 | * I915_CACHING_NONE | |
910 | * | |
911 | * GPU access is not coherent with cpu caches. Default for machines without an | |
912 | * LLC. | |
913 | */ | |
718dcedd | 914 | #define I915_CACHING_NONE 0 |
35c7ab42 DV |
915 | /** |
916 | * I915_CACHING_CACHED | |
917 | * | |
918 | * GPU access is coherent with cpu caches and furthermore the data is cached in | |
919 | * last-level caches shared between cpu cores and the gpu GT. Default on | |
920 | * machines with HAS_LLC. | |
921 | */ | |
718dcedd | 922 | #define I915_CACHING_CACHED 1 |
35c7ab42 DV |
923 | /** |
924 | * I915_CACHING_DISPLAY | |
925 | * | |
926 | * Special GPU caching mode which is coherent with the scanout engines. | |
927 | * Transparently falls back to I915_CACHING_NONE on platforms where no special | |
928 | * cache mode (like write-through or gfdt flushing) is available. The kernel | |
929 | * automatically sets this mode when using a buffer as a scanout target. | |
930 | * Userspace can manually set this mode to avoid a costly stall and clflush in | |
931 | * the hotpath of drawing the first frame. | |
932 | */ | |
933 | #define I915_CACHING_DISPLAY 2 | |
718dcedd DH |
934 | |
935 | struct drm_i915_gem_caching { | |
936 | /** | |
937 | * Handle of the buffer to set/get the caching level of. */ | |
938 | __u32 handle; | |
939 | ||
940 | /** | |
941 | * Cacheing level to apply or return value | |
942 | * | |
943 | * bits0-15 are for generic caching control (i.e. the above defined | |
944 | * values). bits16-31 are reserved for platform-specific variations | |
945 | * (e.g. l3$ caching on gen7). */ | |
946 | __u32 caching; | |
947 | }; | |
948 | ||
949 | #define I915_TILING_NONE 0 | |
950 | #define I915_TILING_X 1 | |
951 | #define I915_TILING_Y 2 | |
deeb1519 | 952 | #define I915_TILING_LAST I915_TILING_Y |
718dcedd DH |
953 | |
954 | #define I915_BIT_6_SWIZZLE_NONE 0 | |
955 | #define I915_BIT_6_SWIZZLE_9 1 | |
956 | #define I915_BIT_6_SWIZZLE_9_10 2 | |
957 | #define I915_BIT_6_SWIZZLE_9_11 3 | |
958 | #define I915_BIT_6_SWIZZLE_9_10_11 4 | |
959 | /* Not seen by userland */ | |
960 | #define I915_BIT_6_SWIZZLE_UNKNOWN 5 | |
961 | /* Seen by userland. */ | |
962 | #define I915_BIT_6_SWIZZLE_9_17 6 | |
963 | #define I915_BIT_6_SWIZZLE_9_10_17 7 | |
964 | ||
965 | struct drm_i915_gem_set_tiling { | |
966 | /** Handle of the buffer to have its tiling state updated */ | |
967 | __u32 handle; | |
968 | ||
969 | /** | |
970 | * Tiling mode for the object (I915_TILING_NONE, I915_TILING_X, | |
971 | * I915_TILING_Y). | |
972 | * | |
973 | * This value is to be set on request, and will be updated by the | |
974 | * kernel on successful return with the actual chosen tiling layout. | |
975 | * | |
976 | * The tiling mode may be demoted to I915_TILING_NONE when the system | |
977 | * has bit 6 swizzling that can't be managed correctly by GEM. | |
978 | * | |
979 | * Buffer contents become undefined when changing tiling_mode. | |
980 | */ | |
981 | __u32 tiling_mode; | |
982 | ||
983 | /** | |
984 | * Stride in bytes for the object when in I915_TILING_X or | |
985 | * I915_TILING_Y. | |
986 | */ | |
987 | __u32 stride; | |
988 | ||
989 | /** | |
990 | * Returned address bit 6 swizzling required for CPU access through | |
991 | * mmap mapping. | |
992 | */ | |
993 | __u32 swizzle_mode; | |
994 | }; | |
995 | ||
996 | struct drm_i915_gem_get_tiling { | |
997 | /** Handle of the buffer to get tiling state for. */ | |
998 | __u32 handle; | |
999 | ||
1000 | /** | |
1001 | * Current tiling mode for the object (I915_TILING_NONE, I915_TILING_X, | |
1002 | * I915_TILING_Y). | |
1003 | */ | |
1004 | __u32 tiling_mode; | |
1005 | ||
1006 | /** | |
1007 | * Returned address bit 6 swizzling required for CPU access through | |
1008 | * mmap mapping. | |
1009 | */ | |
1010 | __u32 swizzle_mode; | |
70f2f5c7 CW |
1011 | |
1012 | /** | |
1013 | * Returned address bit 6 swizzling required for CPU access through | |
1014 | * mmap mapping whilst bound. | |
1015 | */ | |
1016 | __u32 phys_swizzle_mode; | |
718dcedd DH |
1017 | }; |
1018 | ||
1019 | struct drm_i915_gem_get_aperture { | |
1020 | /** Total size of the aperture used by i915_gem_execbuffer, in bytes */ | |
1021 | __u64 aper_size; | |
1022 | ||
1023 | /** | |
1024 | * Available space in the aperture used by i915_gem_execbuffer, in | |
1025 | * bytes | |
1026 | */ | |
1027 | __u64 aper_available_size; | |
1028 | }; | |
1029 | ||
1030 | struct drm_i915_get_pipe_from_crtc_id { | |
1031 | /** ID of CRTC being requested **/ | |
1032 | __u32 crtc_id; | |
1033 | ||
1034 | /** pipe of requested CRTC **/ | |
1035 | __u32 pipe; | |
1036 | }; | |
1037 | ||
1038 | #define I915_MADV_WILLNEED 0 | |
1039 | #define I915_MADV_DONTNEED 1 | |
1040 | #define __I915_MADV_PURGED 2 /* internal state */ | |
1041 | ||
1042 | struct drm_i915_gem_madvise { | |
1043 | /** Handle of the buffer to change the backing store advice */ | |
1044 | __u32 handle; | |
1045 | ||
1046 | /* Advice: either the buffer will be needed again in the near future, | |
1047 | * or wont be and could be discarded under memory pressure. | |
1048 | */ | |
1049 | __u32 madv; | |
1050 | ||
1051 | /** Whether the backing store still exists. */ | |
1052 | __u32 retained; | |
1053 | }; | |
1054 | ||
1055 | /* flags */ | |
1056 | #define I915_OVERLAY_TYPE_MASK 0xff | |
1057 | #define I915_OVERLAY_YUV_PLANAR 0x01 | |
1058 | #define I915_OVERLAY_YUV_PACKED 0x02 | |
1059 | #define I915_OVERLAY_RGB 0x03 | |
1060 | ||
1061 | #define I915_OVERLAY_DEPTH_MASK 0xff00 | |
1062 | #define I915_OVERLAY_RGB24 0x1000 | |
1063 | #define I915_OVERLAY_RGB16 0x2000 | |
1064 | #define I915_OVERLAY_RGB15 0x3000 | |
1065 | #define I915_OVERLAY_YUV422 0x0100 | |
1066 | #define I915_OVERLAY_YUV411 0x0200 | |
1067 | #define I915_OVERLAY_YUV420 0x0300 | |
1068 | #define I915_OVERLAY_YUV410 0x0400 | |
1069 | ||
1070 | #define I915_OVERLAY_SWAP_MASK 0xff0000 | |
1071 | #define I915_OVERLAY_NO_SWAP 0x000000 | |
1072 | #define I915_OVERLAY_UV_SWAP 0x010000 | |
1073 | #define I915_OVERLAY_Y_SWAP 0x020000 | |
1074 | #define I915_OVERLAY_Y_AND_UV_SWAP 0x030000 | |
1075 | ||
1076 | #define I915_OVERLAY_FLAGS_MASK 0xff000000 | |
1077 | #define I915_OVERLAY_ENABLE 0x01000000 | |
1078 | ||
1079 | struct drm_intel_overlay_put_image { | |
1080 | /* various flags and src format description */ | |
1081 | __u32 flags; | |
1082 | /* source picture description */ | |
1083 | __u32 bo_handle; | |
1084 | /* stride values and offsets are in bytes, buffer relative */ | |
1085 | __u16 stride_Y; /* stride for packed formats */ | |
1086 | __u16 stride_UV; | |
1087 | __u32 offset_Y; /* offset for packet formats */ | |
1088 | __u32 offset_U; | |
1089 | __u32 offset_V; | |
1090 | /* in pixels */ | |
1091 | __u16 src_width; | |
1092 | __u16 src_height; | |
1093 | /* to compensate the scaling factors for partially covered surfaces */ | |
1094 | __u16 src_scan_width; | |
1095 | __u16 src_scan_height; | |
1096 | /* output crtc description */ | |
1097 | __u32 crtc_id; | |
1098 | __u16 dst_x; | |
1099 | __u16 dst_y; | |
1100 | __u16 dst_width; | |
1101 | __u16 dst_height; | |
1102 | }; | |
1103 | ||
1104 | /* flags */ | |
1105 | #define I915_OVERLAY_UPDATE_ATTRS (1<<0) | |
1106 | #define I915_OVERLAY_UPDATE_GAMMA (1<<1) | |
ea9da4e4 | 1107 | #define I915_OVERLAY_DISABLE_DEST_COLORKEY (1<<2) |
718dcedd DH |
1108 | struct drm_intel_overlay_attrs { |
1109 | __u32 flags; | |
1110 | __u32 color_key; | |
1111 | __s32 brightness; | |
1112 | __u32 contrast; | |
1113 | __u32 saturation; | |
1114 | __u32 gamma0; | |
1115 | __u32 gamma1; | |
1116 | __u32 gamma2; | |
1117 | __u32 gamma3; | |
1118 | __u32 gamma4; | |
1119 | __u32 gamma5; | |
1120 | }; | |
1121 | ||
1122 | /* | |
1123 | * Intel sprite handling | |
1124 | * | |
1125 | * Color keying works with a min/mask/max tuple. Both source and destination | |
1126 | * color keying is allowed. | |
1127 | * | |
1128 | * Source keying: | |
1129 | * Sprite pixels within the min & max values, masked against the color channels | |
1130 | * specified in the mask field, will be transparent. All other pixels will | |
1131 | * be displayed on top of the primary plane. For RGB surfaces, only the min | |
1132 | * and mask fields will be used; ranged compares are not allowed. | |
1133 | * | |
1134 | * Destination keying: | |
1135 | * Primary plane pixels that match the min value, masked against the color | |
1136 | * channels specified in the mask field, will be replaced by corresponding | |
1137 | * pixels from the sprite plane. | |
1138 | * | |
1139 | * Note that source & destination keying are exclusive; only one can be | |
1140 | * active on a given plane. | |
1141 | */ | |
1142 | ||
1143 | #define I915_SET_COLORKEY_NONE (1<<0) /* disable color key matching */ | |
1144 | #define I915_SET_COLORKEY_DESTINATION (1<<1) | |
1145 | #define I915_SET_COLORKEY_SOURCE (1<<2) | |
1146 | struct drm_intel_sprite_colorkey { | |
1147 | __u32 plane_id; | |
1148 | __u32 min_value; | |
1149 | __u32 channel_mask; | |
1150 | __u32 max_value; | |
1151 | __u32 flags; | |
1152 | }; | |
1153 | ||
1154 | struct drm_i915_gem_wait { | |
1155 | /** Handle of BO we shall wait on */ | |
1156 | __u32 bo_handle; | |
1157 | __u32 flags; | |
1158 | /** Number of nanoseconds to wait, Returns time remaining. */ | |
1159 | __s64 timeout_ns; | |
1160 | }; | |
1161 | ||
1162 | struct drm_i915_gem_context_create { | |
1163 | /* output: id of new context*/ | |
1164 | __u32 ctx_id; | |
1165 | __u32 pad; | |
1166 | }; | |
1167 | ||
1168 | struct drm_i915_gem_context_destroy { | |
1169 | __u32 ctx_id; | |
1170 | __u32 pad; | |
1171 | }; | |
1172 | ||
1173 | struct drm_i915_reg_read { | |
8697600b VS |
1174 | /* |
1175 | * Register offset. | |
1176 | * For 64bit wide registers where the upper 32bits don't immediately | |
1177 | * follow the lower 32bits, the offset of the lower 32bits must | |
1178 | * be specified | |
1179 | */ | |
718dcedd DH |
1180 | __u64 offset; |
1181 | __u64 val; /* Return value */ | |
1182 | }; | |
648a9bc5 CW |
1183 | /* Known registers: |
1184 | * | |
1185 | * Render engine timestamp - 0x2358 + 64bit - gen7+ | |
1186 | * - Note this register returns an invalid value if using the default | |
1187 | * single instruction 8byte read, in order to workaround that use | |
1188 | * offset (0x2538 | 1) instead. | |
1189 | * | |
1190 | */ | |
b6359918 MK |
1191 | |
1192 | struct drm_i915_reset_stats { | |
1193 | __u32 ctx_id; | |
1194 | __u32 flags; | |
1195 | ||
1196 | /* All resets since boot/module reload, for all contexts */ | |
1197 | __u32 reset_count; | |
1198 | ||
1199 | /* Number of batches lost when active in GPU, for this context */ | |
1200 | __u32 batch_active; | |
1201 | ||
1202 | /* Number of batches lost pending for execution, for this context */ | |
1203 | __u32 batch_pending; | |
1204 | ||
1205 | __u32 pad; | |
1206 | }; | |
1207 | ||
5cc9ed4b CW |
1208 | struct drm_i915_gem_userptr { |
1209 | __u64 user_ptr; | |
1210 | __u64 user_size; | |
1211 | __u32 flags; | |
1212 | #define I915_USERPTR_READ_ONLY 0x1 | |
1213 | #define I915_USERPTR_UNSYNCHRONIZED 0x80000000 | |
1214 | /** | |
1215 | * Returned handle for the object. | |
1216 | * | |
1217 | * Object handles are nonzero. | |
1218 | */ | |
1219 | __u32 handle; | |
1220 | }; | |
1221 | ||
c9dc0f35 CW |
1222 | struct drm_i915_gem_context_param { |
1223 | __u32 ctx_id; | |
1224 | __u32 size; | |
1225 | __u64 param; | |
fa8848f2 CW |
1226 | #define I915_CONTEXT_PARAM_BAN_PERIOD 0x1 |
1227 | #define I915_CONTEXT_PARAM_NO_ZEROMAP 0x2 | |
1228 | #define I915_CONTEXT_PARAM_GTT_SIZE 0x3 | |
bc3d6744 | 1229 | #define I915_CONTEXT_PARAM_NO_ERROR_CAPTURE 0x4 |
84102171 | 1230 | #define I915_CONTEXT_PARAM_BANNABLE 0x5 |
c9dc0f35 CW |
1231 | __u64 value; |
1232 | }; | |
1233 | ||
d7965152 RB |
1234 | enum drm_i915_oa_format { |
1235 | I915_OA_FORMAT_A13 = 1, | |
1236 | I915_OA_FORMAT_A29, | |
1237 | I915_OA_FORMAT_A13_B8_C8, | |
1238 | I915_OA_FORMAT_B4_C8, | |
1239 | I915_OA_FORMAT_A45_B8_C8, | |
1240 | I915_OA_FORMAT_B4_C8_A16, | |
1241 | I915_OA_FORMAT_C4_B8, | |
1242 | ||
1243 | I915_OA_FORMAT_MAX /* non-ABI */ | |
1244 | }; | |
1245 | ||
eec688e1 RB |
1246 | enum drm_i915_perf_property_id { |
1247 | /** | |
1248 | * Open the stream for a specific context handle (as used with | |
1249 | * execbuffer2). A stream opened for a specific context this way | |
1250 | * won't typically require root privileges. | |
1251 | */ | |
1252 | DRM_I915_PERF_PROP_CTX_HANDLE = 1, | |
1253 | ||
d7965152 RB |
1254 | /** |
1255 | * A value of 1 requests the inclusion of raw OA unit reports as | |
1256 | * part of stream samples. | |
1257 | */ | |
1258 | DRM_I915_PERF_PROP_SAMPLE_OA, | |
1259 | ||
1260 | /** | |
1261 | * The value specifies which set of OA unit metrics should be | |
1262 | * be configured, defining the contents of any OA unit reports. | |
1263 | */ | |
1264 | DRM_I915_PERF_PROP_OA_METRICS_SET, | |
1265 | ||
1266 | /** | |
1267 | * The value specifies the size and layout of OA unit reports. | |
1268 | */ | |
1269 | DRM_I915_PERF_PROP_OA_FORMAT, | |
1270 | ||
1271 | /** | |
1272 | * Specifying this property implicitly requests periodic OA unit | |
1273 | * sampling and (at least on Haswell) the sampling frequency is derived | |
1274 | * from this exponent as follows: | |
1275 | * | |
1276 | * 80ns * 2^(period_exponent + 1) | |
1277 | */ | |
1278 | DRM_I915_PERF_PROP_OA_EXPONENT, | |
1279 | ||
eec688e1 RB |
1280 | DRM_I915_PERF_PROP_MAX /* non-ABI */ |
1281 | }; | |
1282 | ||
1283 | struct drm_i915_perf_open_param { | |
1284 | __u32 flags; | |
1285 | #define I915_PERF_FLAG_FD_CLOEXEC (1<<0) | |
1286 | #define I915_PERF_FLAG_FD_NONBLOCK (1<<1) | |
1287 | #define I915_PERF_FLAG_DISABLED (1<<2) | |
1288 | ||
1289 | /** The number of u64 (id, value) pairs */ | |
1290 | __u32 num_properties; | |
1291 | ||
1292 | /** | |
1293 | * Pointer to array of u64 (id, value) pairs configuring the stream | |
1294 | * to open. | |
1295 | */ | |
cd8bddc4 | 1296 | __u64 properties_ptr; |
eec688e1 RB |
1297 | }; |
1298 | ||
d7965152 RB |
1299 | /** |
1300 | * Enable data capture for a stream that was either opened in a disabled state | |
1301 | * via I915_PERF_FLAG_DISABLED or was later disabled via | |
1302 | * I915_PERF_IOCTL_DISABLE. | |
1303 | * | |
1304 | * It is intended to be cheaper to disable and enable a stream than it may be | |
1305 | * to close and re-open a stream with the same configuration. | |
1306 | * | |
1307 | * It's undefined whether any pending data for the stream will be lost. | |
1308 | */ | |
eec688e1 | 1309 | #define I915_PERF_IOCTL_ENABLE _IO('i', 0x0) |
d7965152 RB |
1310 | |
1311 | /** | |
1312 | * Disable data capture for a stream. | |
1313 | * | |
1314 | * It is an error to try and read a stream that is disabled. | |
1315 | */ | |
eec688e1 RB |
1316 | #define I915_PERF_IOCTL_DISABLE _IO('i', 0x1) |
1317 | ||
1318 | /** | |
1319 | * Common to all i915 perf records | |
1320 | */ | |
1321 | struct drm_i915_perf_record_header { | |
1322 | __u32 type; | |
1323 | __u16 pad; | |
1324 | __u16 size; | |
1325 | }; | |
1326 | ||
1327 | enum drm_i915_perf_record_type { | |
1328 | ||
1329 | /** | |
1330 | * Samples are the work horse record type whose contents are extensible | |
1331 | * and defined when opening an i915 perf stream based on the given | |
1332 | * properties. | |
1333 | * | |
1334 | * Boolean properties following the naming convention | |
1335 | * DRM_I915_PERF_SAMPLE_xyz_PROP request the inclusion of 'xyz' data in | |
1336 | * every sample. | |
1337 | * | |
1338 | * The order of these sample properties given by userspace has no | |
d7965152 | 1339 | * affect on the ordering of data within a sample. The order is |
eec688e1 RB |
1340 | * documented here. |
1341 | * | |
1342 | * struct { | |
1343 | * struct drm_i915_perf_record_header header; | |
1344 | * | |
d7965152 | 1345 | * { u32 oa_report[]; } && DRM_I915_PERF_PROP_SAMPLE_OA |
eec688e1 RB |
1346 | * }; |
1347 | */ | |
1348 | DRM_I915_PERF_RECORD_SAMPLE = 1, | |
1349 | ||
d7965152 RB |
1350 | /* |
1351 | * Indicates that one or more OA reports were not written by the | |
1352 | * hardware. This can happen for example if an MI_REPORT_PERF_COUNT | |
1353 | * command collides with periodic sampling - which would be more likely | |
1354 | * at higher sampling frequencies. | |
1355 | */ | |
1356 | DRM_I915_PERF_RECORD_OA_REPORT_LOST = 2, | |
1357 | ||
1358 | /** | |
1359 | * An error occurred that resulted in all pending OA reports being lost. | |
1360 | */ | |
1361 | DRM_I915_PERF_RECORD_OA_BUFFER_LOST = 3, | |
1362 | ||
eec688e1 RB |
1363 | DRM_I915_PERF_RECORD_MAX /* non-ABI */ |
1364 | }; | |
1365 | ||
b1c1f5c4 EV |
1366 | #if defined(__cplusplus) |
1367 | } | |
1368 | #endif | |
1369 | ||
718dcedd | 1370 | #endif /* _UAPI_I915_DRM_H_ */ |